Based on slides/material by…
‹
J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html
“Digital Integrated Circuits: A Design Perspective”, Prentice Hall
‹
D. Harris http://www.cmosvlsi.com/coursematerials.html
Weste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”,
Addison Wesley
‹
W. Wolf http://www.princeton.edu/~wolf/modern-vlsi/Overheads.html
“Modern VLSI Design: System-on-Chip Design”, Prentice Hall
Topic 4
Sequential Circuits
Peter Y. K. Cheung
Department of Electrical & Electronic Engineering
Imperial College London
Recommended Reading:
‹ J. Rabaey et. al. “Digital Integrated Circuits: A Design Perspective”: Chapter 7
‹
URL: www.ee.ic.ac.uk/pcheung
E-mail: p.cheung@imperial.ac.uk
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 1
Weste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”:
Chapter 1 (1.4.9), Chapter 7 (7.3.1 – 7.3.5)
Sequential Circuits
Outline
‹
Bi – Stability / Meta – Stability
‹
Latches
‹
Flip – flops
‹
Schmitt Trigger
‹
Multivibrator circuits
Digital Integrated Circuit Design
Topic 4 - 2
Combinational vs. Sequential Logic
In
Logic
In
Circuit
Logic
Out
Out
Circuit
State
(a) Combinational
‹
(b) Sequential
Counters and sequential machines
Output = f(In)
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 3
Sequential Circuits
Output = f(In, Previous In)
Digital Integrated Circuit Design
Topic 4 - 4
Sequential Logic
Positive Feedback: Bi-Stability
Vo1 =Vi2
φ
Vi1
Vo1
Vi2 = Vo1
FF’s
Vo2
LOGIC
tp,comb
In
Vi1
Vi2 = Vo1
Out
2 storage mechanisms
• positive feedback
Vo2
A
C
• charge-based
B
Vi1 = Vo2
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 5
Sequential Circuits
Digital Integrated Circuit Design
Vi2 = Vo1
Vi2 = Vo1
Meta-Stability
Topic 4 - 6
Outline
‹
Bi – Stability / Meta – Stability
‹
Latches
‹
Flip – flops
‹
Schmitt Trigger
‹
Multivibrator circuits
‹
Counters and sequential machines
B
C
δ
‹
Vi1 = Vo2
δ
Vi1 = Vo2
Gain should be larger than 1 in the transition region
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 7
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 8
D Latch
‹
D Latch Design
When CLK = 1, latch is transparent
‹
• D flows through to Q like a buffer
‹
Multiplexer chooses D or old Q
When CLK = 0, the latch is opaque
• Q holds its old value independent of D
‹
CLK
transparent latch or level-sensitive latch
D
1
Q
Latch
CLK
D
Sequential Circuits
CLK
D
Q
CLK
CLK
D
Q
CLK
Q
Digital Integrated Circuit Design
Q
CLK = 1
Q
0
Topic 4 - 9
Sequential Circuits
D Latch Operation
D
CLK
Q
Q
D
Digital Integrated Circuit Design
Topic 4 - 10
Latch Design
Q
‹
Q
‹
Pass Transistor Latch
Pros
φ
+ Tiny
+ Low clock load
CLK = 0
‹
Cons
-
CLK
D
Vt drop
nonrestoring
backdriving
output noise sensitivity
dynamic
diffusion input
D
Q
Used in 1970’s
Q
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 11
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 12
Latch Design
‹
Latch Design
φ
Transmission gate
+ No Vt drop
- Requires inverted clock
D
‹
φ
Inverting buffer
+ Restoring
+ No backdriving
+ Fixes either
Q
Ê Output noise sensitivity
Ê Or diffusion input
φ
X
D
Q
φ
φ
- Inverted output
D
Q
φ
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 13
Sequential Circuits
Latch Design
‹
+ Static
- Backdriving risk
‹
‹
X
D
Static latches are now essential
Topic 4 - 14
Latch Design
φ
Tristate feedback
Digital Integrated Circuit Design
φ
Q
Buffered input
+ Fixes diffusion input
+ Noninverting
φ
X
D
φ
φ
Q
φ
φ
φ
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 15
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 16
Latch Design
‹
Buffered output
Latch Design
φ
+ No backdriving
‹
Datapath latch
φ
φ
φ
Very robust (most important)
Rather large
Rather slow
High clock loading
Sequential Circuits
φ
Digital Integrated Circuit Design
Topic 4 - 17
Sequential Circuits
Digital Integrated Circuit Design
‹
‹
‹
Flip – flops
‹
Schmitt Trigger
Topic 4 - 18
D Flip-flop
Bi – Stability / Meta – Stability
Latches
φ
φ
Outline
‹
Q
X
D
Widely used in standard cells
+
-
‹
φ
+ Smaller, faster
- unbuffered input
X
D
‹
Q
‹
When CLK rises, D is copied to Q
At all other times, Q holds its value
positive edge-triggered flip-flop, master-slave flip-flop
CLK
CLK
D
Multivibrator circuits
D
‹
Flop
‹
Q
Counters and sequential machines
Sequential Circuits
Digital Integrated Circuit Design
Q
Topic 4 - 19
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 20
D Flip-flop Design
‹
D Flip-flop Operation
Built from master and slave D latches
QM
D
Q
CLK = 0
CLK
CLK
CLK
QM
D
CLK
QM
Latch
D
Latch
CLK
CLK
Q
CLK
QM
D
Q
CLK
CLK = 1
Q
CLK
CLK
CLK
D
Q
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 21
Sequential Circuits
Flip-Flop: Timing Definitions
Digital Integrated Circuit Design
Topic 4 - 22
Maximum Clock Frequency
φ
FF’s
φ
t
tsetup
thold
In
DATA
LOGIC
STABLE
Out
t
tp,comb
tpFF
DATA
STABLE
Sequential Circuits
Digital Integrated Circuit Design
t
Topic 4 - 23
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 24
Flip-Flop Design
‹
Enable
Flip-flop is built as pair of back-to-back latches
Enable: ignore clock when en = 0
• Mux: increase latch D-Q delay
• Clock Gating: increase en setup time, skew
φ
φ
X
D
‹
Q
Symbol
Multiplexer Design
Clock Gating Design
φ en
D
Q
φ
1
D
Q
0
en
X
Q
en
Q
φ
D
φ
φ en
φ
φ
D
1
0
Q
Q
D
en
Flop
φ
φ
Flop
φ
φ
Flop
D
D
Q
Latch
φ
φ
Latch
φ
Latch
φ
φ
Q
en
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 25
Sequential Circuits
Digital Integrated Circuit Design
Reset
Set / Reset
D
φ
Q
D
reset
Synchronous Reset
φ
‹
Flip-flop with asynchronous set and reset
Q
φ
Q
φ
φ
φ
φ
φ
φ
reset
set
φ
φ
Asynchronous Reset
Q
φ
D
φ
φ
Q
φ
φ
φ
φ
Q
φ
set
reset
reset
D
D
φ
φ
φ
φ
φ
Digital Integrated Circuit Design
reset
φ
φ
reset
reset
φ
Sequential Circuits
Set forces output high when enabled
Q
φ
Q
reset
D
φ
‹
reset
φ
reset
D
Flop
φ
Symbol
‹
Force output
low when reset
asserted
Synchronous
vs.
asynchronous
Latch
‹
Topic 4 - 26
φ
φ
φ
Topic 4 - 27
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 28
SR-Flip Flop
S
Q
S
Q
R
Q
Q
R
JK- Flip Flop
S
R
Q
Q
0
1
0
1
0
0
1
1
Q
1
0
0
Q
0
1
0
J
S
Q
R
Q
S
R
Q
Q
R
Sequential Circuits
S
R
1
0
1
0
1
1
0
0
Q
Q
Q
Q
1
0
1
Q
0
1
1
Digital Integrated Circuit Design
J
φ
K
Q
Topic 4 - 29
D
Q
K
Q
Sequential Circuits
Digital Integrated Circuit Design
Q
φ
Q
Topic 4 - 30
Master-Slave Flip-Flop
J
φ
Qn
0
1
Qn
(c)
J
φ
SLAVE
MASTER
φ
0
0
1
1
(b)
Other Flip-Flops
T
Qn+1
Q
(a)
Q
Kn
0
1
0
1
φ
K
S
Jn
Q
J
S
Q
K
R
Q
SI
S
Q
Q
R
Q
Q
Q
K
T
Q
D
Q
φ
Q
φ
Q
RI
φ
PRESET
Toggle Flip-Flop
Delay Flip-Flop
J
φ
K
Q
Q
CLEAR
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 31
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 32
Edge Triggered Flip-Flop
Race Condition
‹
• Second flip-flop fires late
• Sees first flip-flop change and captures its result
• Called hold-time failure or race condition
J
S
Q
Q
R
Q
Q
Back-to-back flops can malfunction from clock skew
φ
CLK1
K
D
Q
CLK2
CLK2
Flop
J
Flop
CLK1
Q1
Q1
Q2
Q2
>φ
K
Sequential Circuits
Q
Digital Integrated Circuit Design
Topic 4 - 33
Sequential Circuits
Nonoverlapping Clocks
‹
Nonoverlapping clocks can prevent races
‹
Can be used for safe design
Digital Integrated Circuit Design
CMOS Clocked SR- FlipFlop
• As long as nonoverlap exceeds clock skew
VDD
• Industry manages skew more carefully instead
φ2
φ2
Q
Q
φ1
φ
φ1
S
φ2
M4
Q
QM
φ2
M2
φ1
D
Topic 4 - 34
M6
M1
M5
M8
φ
M7
R
M3
φ1
φ1
φ2
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 35
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 36
Flip-Flop: Transistor Sizing
6 Transistor CMOS SR-Flip Flop
VDD
(1.8/1.2)
4.0
(3.6/1.2)
(7.2/1.2)
M2
φ
φ
M4
Q
S
Q
R
VQ
M5
M1
2.0
0.0
0.0
1.0
Sequential Circuits
2.0
3.0
4.0
M3
5.0
Digital Integrated Circuit Design
Topic 4 - 37
Sequential Circuits
Digital Integrated Circuit Design
Charge-Based Storage
Master-Slave Flip-Flop
φ
φ
φ
D
In
Topic 4 - 38
φ
D
A
In
B
D
φ
φ
φ
φ
(b) Non-overlapping clocks
φ
φ
(a) Schematic diagram
Overlapping Clocks Can Cause
• Race Conditions
Pseudo-static Latch
Sequential Circuits
Digital Integrated Circuit Design
• Undefined Signals
Topic 4 - 39
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 40
2-phase dynamic flip-flop
2 phase non-overlapping clocks
φ1
φ2
φ1
D
In
φ2
In
φ2
D
φ1
Input Sampled
φ1
φ1
φ2
φ2
Output Enable
tφ12
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 41
Sequential Circuits
Digital Integrated Circuit Design
C2MOS avoids Race Conditions
Flip-flop insensitive to clock overlap
VDD
VD D
M2
φ
M4
φ
M3
VDD
M6
X
In
CL1
φ
φ
M2
VD D
VDD
VDD
M6
M2
M6
M8
M7
D
CL2
0
X
In
1
M1
Topic 4 - 42
M3
D
1
M4
X
In
0
M8
D
M7
M5
M1
φ−section
M1
M5
M5
φ−section
(a) (1-1) overlap
(b) (0-0) overlap
C2MOS LATCH
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 43
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 44
Pipelined Logic using C2MOS
b
Non-pipelined version
φ
φ
.
log
φ
REG
REG
φ
REG
Out
φ
REG
b
log
REG
.
φ
VDD
REG
a
REG
a
REG
Pipelining
Out
φ
In
φ
φ
φ
F
φ
Pipelined version
φ
VDD
VDD
Out
G
φ
C1
φ
C2
C3
NORA CMOS
What are the constraints on F and G?
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 45
Sequential Circuits
Digital Integrated Circuit Design
Doubled C2MOS Latches
NORA CMOS Modules
VD D
φ
In1
In2
In3
VDD
VDD
PUN
φ
φ
φ
(a) φ-module
VDD
VDD
In
φ
φ
φ
φ
Out
VD D
In 4
PDN
φ
In
Latch
φ
In 1
In 2
In 3
Sequential Circuits
Out
φ
VDD
VDD
Out
φ
Combinational logic
VDD
VDD
VDD
φ
PDN
Topic 4 - 46
Out
Doubled n-C2MOS latch
φ
In4
Digital Integrated Circuit Design
Doubled n-C2 MOS latch
(b) φ-module
Topic 4 - 47
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 48
TSPC - True Single Phase Clock Logic
VD D
VDD
VDD
Master-Slave Flip-flops
VDD
φ
PUN
D
In
φ
VDD
VDD
φ
Logic
φ
Out
D
φ
VDD
D
φ
φ
φ
D
VDD
(b) Negative edge-triggered D flip-flop
VDD
D
φ
Inserting logic between
Including logic into
latches
the latch
Digital Integrated Circuit Design
(c) Positive edge-triggered D flip-flop
using split-output latches
Topic 4 - 49
Sequential Circuits
Digital Integrated Circuit Design
Outline
‹
Bi – Stability / Meta – Stability
‹
Latches
‹
Flip – flops
‹
Schmitt Trigger
Topic 4 - 50
Schmitt Trigger
V OH
Vou t
In
‹
‹
‹
Multivibrator circuits
‹
Counters and sequential machines
Out
VTC with hysteresis
Restores signal slopes
V OL
VM–
Sequential Circuits
VD D
φ
(a) Positive edge-triggered D flip-flop
PDN
Sequential Circuits
D
φ
Static
φ
VDD
φ
Y
X
φ
VDD
VDD
Digital Integrated Circuit Design
Topic 4 - 51
Sequential Circuits
Digital Integrated Circuit Design
VM+
Vi n
Topic 4 - 52
Noise Suppression using Schmitt Trigger
CMOS Schmitt Trigger
VDD
Vin
Vout
VM+
M2
X
Vin
VM–
M1
t0
t 0 + tp
t
Sequential Circuits
Vout
M3
t
Digital Integrated Circuit Design
Topic 4 - 53
Sequential Circuits
Schmitt Trigger Simulated VTC
5.0
M4
Digital Integrated Circuit Design
Topic 4 - 54
CMOS Schmitt Trigger (2)
6.0
VDD
4.0
M4
4.0
Vout (V)
VX (V)
3.0
2.0
M6
V M+
M3
In
2.0
V M-
1.0
0.0
0.0
Sequential Circuits
Out
M2
X
1.0
2.0
3.0
Vin (V)
4.0
5.0
0.0
0.0
Digital Integrated Circuit Design
M5
VD D
M1
1.0
2.0
3.0
V in (V)
4.0
5.0
Topic 4 - 55
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 56
Outline
‹
Bi – Stability / Meta – Stability
‹
Latches
Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
‹
Flip – flops
‹
Schmitt Trigger
‹
Multivibrator circuits
‹
Counters and sequential machines
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 57
Sequential Circuits
Digital Integrated Circuit Design
Transition-Triggered Monostable
Topic 4 - 58
Monostable Trigger (RC-based)
VDD
R
In
In
A
B
Out
(a) Trigger circuit.
C
DELAY
td
Out
td
In
B
VM
Out
t
t1
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 59
Sequential Circuits
(b) Waveforms.
t2
Digital Integrated Circuit Design
Topic 4 - 60
Astable Multivibrators (Oscillators)
0
1
2
Voltage Controller Oscillator (VCO)
N-1
VD D
VDD
M6
M4
Schmitt Trigger
restores signal slopes
M2
Ring Oscillator
In
M1
Iref
V1
V3
V5
Vcontr
V (Volt)
5.0
M5
Current starved inverter
3.0
6
-1.0
0
1
2
3
4
t pH L (nsec)
1.0
5
t (nsec)
4
2
0.0
0.5
simulated response of 5-stage oscillator
Sequential Circuits
Iref
M3
Digital Integrated Circuit Design
Topic 4 - 61
Sequential Circuits
1.5
V co ntr (V)
2.5
Digital Integrated Circuit Design
Relaxation Oscillator
Out1
Out2
R
Topic 4 - 62
Outline
I2
I1
propagation delay as a function
of control voltage
‹
Bi – Stability / Meta – Stability
‹
Latches
‹
Flip – flops
‹
Schmitt Trigger
‹
Multivibrator circuits
‹
Counters and sequential machines
C
Int
T = 2 (log3) RC
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 63
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 64
One-bit counter implementation
One-bit counter operation
‹
‹
‹
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 65
All operations are performed as sφ2.
XOR computes next value of this bit of counter.
NAND/inverter compute carry-out.
Sequential Circuits
n-bit counter structure
Digital Integrated Circuit Design
Topic 4 - 66
Sequential machines
‹
‹
Use memory elements to make primary output values depend on state +
primary inputs.
Varieties:
• Mealy—outputs function of present state, inputs;
• Moore—outputs depend only on state.
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 67
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 68
Sequential machine definition
FSM structure
‹
Machine computes next state N, primary outputs O from current state S,
primary inputs I.
Next-state function:
‹
Output function (Mealy):
‹
• N = δ(I,S).
• O = λ(I,S).
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 69
Summary
‹
Bi-stable sequential circuits
• Latches (level sensitive circuits)
• Flip – flops (edge triggered circuits)
‹
Non bi-stable sequential circuits
• Schmitt Trigger (responds fast to a slowly changing input)
• Multivibrator circuits
Ê Monostable (only one stable state – generates pulse of predetermined width)
Ê Astable (no stable states – output oscillates between two quasi stable states)
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 71
Sequential Circuits
Digital Integrated Circuit Design
Topic 4 - 70