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This paper illustrates the complex, inter-related design optimization choices required to achieve efficient, high speed silicon bipolar ECL VLSI ASICs. We present three possible design choices for ECL internal circuit design, and briefly discuss the trade-offs involved in our final choice. We then show the impact of this optimization on output driver circuit design, and for example, the need for a new analytical framework to understand the lOOK performance of the chosen output circuit design. An analytical framework for the
temperature compensation of an effective threelevel series-gated ECL output driver is then presented. This analysis was developed during the design of the output cell of a bipolar VLSI gate array IC. Results from this analysis have been shown to agree quite well with actual measurements and computer-aided simulations.
Overview
Internal Comparator Design
Output Driver Design
Circuit Design Choices - Overview
Input Receiver Circuit Design
Input Receiver Circuit
Internal Comparator Circuit Design
Optimal ECL Internal Logic Swing
Standard VBB-based Internal Comparator
Common Mode VBB-based Internal Comparator
Vrl-based Internal Comparator lOOK Output Driver Design - Diode Stacking Considerations
Circuit Design Optimization - Conclusions lOOK Output Temperature Compensation
ECL lOOK VOH and dVOH/dT Equations
ECL lOOK VOL and dVOL/dT Equations
RC/RCM Optimization
Conclusions
7
9
13
13
14
15
16
4
4
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2

OVERVIEW
Silicon bipolar ECL circuits attain fast switching speeds partially due to their small, well-controlled logic voltage swing. Since the delay perfonnance of a digital circuit is proportional to its' logic swing, we note that excessive logic swing creates a delay penalty. However, if the logic voltage swing is too small compared to the total potential noise losses, we can attain marginal noise margins, and consequently suffer from poor signal integrity. Thus a well-balanced logic voltage swing is optimized to provide reliable high speed operation with assured signal integrity.
Internal Comparator Design: System level electrical signals usually contain transient noise due to a variety of sources such as, impedance variation, reflection, crosstalk, etc. This design example illustrates how internal circuit design can have a major impact on output driver design.
Let us define input receiver and internal comparator circuit functions. An IC input receiver circuit receives off-chip signal inputs and provides buffered output signals with well-defined voltage levels. It also provides good driving capability for driving other circuits within the IC. This circuit uses the standard ECL first level comparator reference voltage, called VBB, to arbitrate high and low level signals from inputs. Since the incoming system level signals are coded around this reference voltage, our design choices are restricted to utilizing to VBB reference only. On the other hand, internal comparator circuits are used to perfonn a variety of logic functions within the
IC. Such circuits receive signals from, and source signals to, other logic circuits within the IC.
Since we have control of both the source and destination circuits, we can design any appropriate logic swing, high and low levels, and comparator reference voltages. There are three options for internal comparator circuit design:
1. Use standard VBB as Vr1. (Fig 1)
2. Use standard VBB and a common mode resistor offset. (Fig 2)
3. Use non-standard Vrl optimized to provide comparable
VNML. (Fig 3)
The first choice ensures signal compatibility with off-chip inputs. This enables a gate array architecture design which can accept off-chip inputs to any arbitrary location within the Ie, thus providing usage flexibility, and reduced output driver cells' utilization. However, this technique makes the total logic swing too large, thus incurring a delay penalty.
The second choice also ensures signal compatibililty with off-chip inputs, thus providing usage flexibility, etc., as discussed above. Since the common mode offset resistor is used to tune the total logic swing to an optimal level, this technique does not incur a delay penalty. However, the need for an extra component raises the silicon real estate cost of this solution, and also adds to routing complexity.
In the third design choice, we develop and use a non-standard ECL reference voltage, called Vrl, to optimize the total voltage swing without requiring a common mode offset resistor. This .:hoice has the added benefit of facilitating three-level lOOK series-gating, thus providing enhanced circuit functionality at no incremental power. However, this choice restricts the ability of the array architecture to allow off-chip signal inputs to any location inside the IC, unless suitable CAD programs are developed to provide appropriate reference voltages which depend upon the source of input signals. Further, this technique requires two separate voltage regulators, versus one in the ftrst two cases.
However, this approach ensures an optimal logic swing, eliminates the need for repetitive common mode resistors, and provides an improved ECL three-level series-gating perfonnance. Our choice in this regard was further strengthened by our ability to get CAD software support which made appropriate reference selection an automated function. Consequently, we reduced the total logic
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swing by 30%. This reduction is achieved without any loss in noise margin. It leads to a faster propagation time for no incremental power.
Output Driver Design: Having selected the non-standard Vrl-based circuit as our internal ECL design, we find that this significantly channels our output driver design choices, especially for a series-gated lOOK ECL output driver.
In the lOOK output driver (Fig 3), Vrl cannot be applied directly to the output current switch first level reference transistor, since this introduces a base/collector saturation hazard for the input transistor. Thus Vr2, which is the internal second level reference, is applied as the first level reference voltage.
Vr2
=
Vr1 - Vbe(Q9)
Therefore Vr3 becomes the second-level reference. However, note that Vr3 is offset from Vrl by
2 Vbe, and thus represents a true third-level series-gating reference.
Vr3
=
Vr2 - Vbe(Q13)
In a conventional ECL output driver design, Vr3 is not a viable voltage reference because three level deep series gating is not allowable. This follows from diode stacking considerations, as described later. We are able to overcome this constraint only because we developed a current mirror based comparator current mechanism. This allows an acceptable diode stacking, since a current mirror reduces ECL VEE min. requirements by
mV under nominal condition.
Diode stacking refers to a minimum ECL VEE requirement which depends on the number of series gating stages utilized in comparator design. In ECL, all reference voltage - Vrl, Vr2, Vr3, etc. are developed with respect to ECL VCC. Further, all current source voltages are developed with respect to ECL VEE. The current source transistor is set-up so that its' base follows ECL VEE, while its' collector follows ECL VCe. If ECL VCC - ECL VEE falls below a critical minimum, defined as the diode stack, the current source can saturate. Such saturation causes unacceptable circuit behaviour. Fig. 4 represents the conventional lOOK current source based approach. In this case,
ECL VEE min.
=
-4.48
V - 0.12 V
=
-4.60 V
Where 4.48V is the ECL VEE applied to the IC and 0.l2V is the Ohmic voltage loss in the Ie package.
Fig. 3 represents our lOOK current mirror based approach.
In this case,
ECL VEE min.
=
V - 0.12 V
=
-4.04 V which is well below the ECL VEE min. requirement for commercial range lOOK ECL VLSI ICs, and therefore represents an acceptable design.
Circuit Design Choices· Overview: In this section, the basic theme of this paper - design optimization inter-relationships - has been presented in overview form. The following sections discuss the design trade-offs in more detail.
ECL signals transmitted across digital systems' interconnect media follow well-defmed, standard
ECL VOH and VOL levels. On the driving side, ECL output drivers deliver digital information encoded within specific high and low level voltage ranges. Usually however, such signals also pick up unwanted transient noise spikes due to PCB impedance variation, reflection, crosstalk, etc.
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On the receiving side, ECL receiverlbuffer circuits decode incoming system voltages and provide buffered driving capability within an IC. The receiverlbuffer comparator circuits arbitrate high and low level inputs with respect to a reference voltage centred around the nominal ECL logic voltage swing. This voltage level, commonly called VBB, ensures adequate high and low level noise margins, when nominal VIR, Vn... levels are input to the IC.
Input Receiver Circuit: A conventional ECL input receiver is presented in Fig.
1.
This ECL switch performs a buffer/driver function. It receives off-chip signal inputs at A and provides a buffered output at YA, such that YA = A. Standard ECL levels are input to this circuit. For lOOK, these levels are:
-880 mV
-1625 mV
> VIH> -1025 mV
> VIL > -1810 mV
In order to ensure adequate noise margin levels when standard ECL I/O input levels are applied to this input buffer, the reference voltage, Vrl = VBB, is chosen. At room temperature, nominal
VBB is set to --1305mV.
In this case, minimum noise margins can be defined as:
VNMHmin.
=
VIHmin. - VBBnom.
=
(-1025) - (-1305)
=
280 mV
VNMLmin.
= VBBnom. - VILmax.
=
(-1305) - (-1625)
=
320 mV
INTERNAL COMPARATOR CIRCUIT DESIGN
Using VBB as the reference voltage for the internal comparator creates a sub-optimal design.
Essentially, this follows because internal data transmission voltages can be better controlled than external, PCB level data transmission voltages. Thus, VOH, VOL levels within an IC can be designed to a smaller voltage swing. Optimal internal circuit design techniques also lead to internal
VOH levels that differ from external VOH levels, making the use of the external VBB reference sub-optimal. In this section, we explore several design approaches to internal circuit optimization, and the impact these choices have on output driver design.
Optimal ECL Internal Logic Swing: The logic swing chosen for IC-internal logic circuits must ensure signal intergrity with fast operation. We can view the logic swing, VI, as made up of two components,
VI = VNMLoss + Vlmin.
In this equation, VNMLoss represents the potential worst-case noise margin losses and Vlmin represents the minimum voltage difference required to ensure proper comparator operation. Vlmin can be understood as follows.
If we assume matched devices, then comparator behaviour depends on the voltage difference between the input applied to one comparator transistor's base, and the reference voltage applied to the other transistor's base. So,
Delta V = Yin - V,1 = VT*ln(IClIIC2)
This equation illustrates a fundamental aspect of the comparator function. For example, as the input voltage rises 60 mV above the reference voltage, the current, ICS, is split in a 10: I ratio between ICI and IC2. The following table illustrates this aspect more comprehensively. The nominal forward conduction voltage of the ECL switch transistors, Vbe, varies inversely with temperature, which requires higher delta voltages at higher junction temperature.
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lcl:lc2
Ratio
Delta V
= f[Tj] (mV)
-550C 270C 1250C
10:1
100:1
1000:1
45
90
135
60
120
180
90
180
270
If we accpet Vlmin. as 180 mY, then we can expect a 1 % error in internal VOL at a junction temperature of 125 degrees C.
This is an acceptable design target. The other factor, VNMLoss, is used to account for noise margin loss mechanisms present within a large ASIC device. Such mechanisms include Ohmic voltage losses on long routed signal nets, delta Vbe effects dut to ICS,
IOEF programming, Wire-OR voltage losses, Vref variations, etc. Let us approximate the total impact of these factors to be 120 mV worst case, which is a reasonable target. Then we can derme the optimal logic swing for our VLSI ASIC design to be,
VI
=
Optimal Logic Swing
=
600 mY.
Standard VBB-based internal comparator: Inside a VLSI IC, ECL VOH and VOL levels differ from external input levels. With reference to Fig. 1, note that when input A is at a high level with respect to Vrl, the OR output YA attains,
VOH
=
ECL VCC - Vbe(Q4) and,
VNMH
=
VOH - Vr1
Conversely, when input A is at a low level with respect to VBB, the OR output YA attains, where, and,
VOL = ECL VCC - VI- Vbe(Q4)
VI
= lCS*Rc
VNML
=
Vr1 - VOL
Usually, VNML = 300 mV is considered adequate.
If the same reference voltage, VBB, is used inside the IC, the internal high and low level noise margins can be defined as:
VNMHnom.
=
VOHnom. - VBBnom.
=
-760 mV + 1305 mV
=
545 mV
VNMLnom.
=
VBBnom. - VOLnom.
= -
1305 mV + [845 mV + 760 mV]
=
300 mV
While such a design methodology ensures adequate VNMH and VNML values, it creates an excessively large total logic voltage swing, VI. This follows because,
VI
=
VOH - VOL
=
VNMH + VNML
=
845 mV and VNMH is over-designed at 545 mY.
Since the delay performance of this circuit is proportional to its logic swing, this excessive logic swing creates a delay penalty.
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YA
One design technique used to balance the VNMH and VNML values, and thus optimize the total logic swing, is to use a common mode offset resistor. Such an ECL current switch is shown in Fig. 2. In this case, where, where,
VI
=
VOH - VOL
VOH =
VOL
vee -
Vem - Vbe(Q4)
= vee -
(Vem + Vdm) - Vbe(Q4)
Vem
Vdm
=
Ies
*
Rem
=
Ies
*
Rdm and, by design,
VI
=
Vdm
This circuit reduces the excessive VNMH by developing a common mode offset voltage, Vern, across Rem. While this technique successfully addressses the excessive swing issue, it creates the need for an additional component in each ECL current switch. In a large VLSI IC, such additional components can consume considerable Silicon real estate.
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A
RDM
VBB
YA
EeL
third design technique used to balance the VNMH and
VNML values, and thus optimize the total logic swing, is to use a non-standard ECL reference voltage. Such an ECL current switch is identical to the conventional circuit presented in Fig. 1, except that the reference voltage, Vrl, is chosen to balance both VNMH and VNML with an optimally minimized total logic swing. In this case, with reference to Fig. 1, when input A is at a high level with respect to Vrl, the OR output YA attains, so,
VOH = ECL VCC - Vbe(Q4)
VNMH
=
VOH - Vr]
Conversely, when input A is at a low level with respect to Vrl, the OR output YA attains, where, and,
VOL
=
ECL VCC - VI- Vbe(Q4)
VI
=
ICS*Rc
VNML
=
Vr] - VOL
Usually, VNML = 300 mV is considered adequate at room temperature. The optimal reference voltage, Vr!, to be used inside the IC, can be developed as follows:
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Vr1nom.
=
VOHnom. - VNMHnom.
= -760 mV - 300 mV
=
-1060 mV
Then,
VNMHnom.
=
VOHnom. - Vr1nom.
=
-760 mV + 1060 mV
=
300 mV and, where,
VNMLnom.
=
Vr1nom. - VOLnom.
VI
=
ICS*Rc
=
600 mV
=-
1060 mV + 600 mV + 760 mV
=
300 mV
This design methodology ensures adequate VNMH and VNML values and creates an optimal total logic voltage swing, VI, without requiring a common mode resistor. It reduces the excessive
VNMH of the conventional approach by developing a reference voltage optimized for internal voltage swing values.
The benefits of this technique are a 30% reduction - from 845 mV to 600 mV - in the total logic swing, without any loss of high or low noise margin. Thus the delay performance of the circuit is improved significantly without requiring any increase in power dissipation.
lOOK OUTPUT DRIVER DESIGN - DIODE STACKING CONSIDERATIONS
Our choice of the third design technique mentioned above places some new constraints on the design of a series-gated lOOK ECL output driver. Specifically, the internal reference voltage, Vrl, cannot be applied directly to the output current switch first level reference transistor, sincc~ this introduces a base/collector saturation hazard when the current ICM (Fig. 3) is switched to place the output at a low level.
order to eliminate this saturation hazard, Vr2 ( which is usually a second level reference) is applied as the first level reference voltage.
Vr2
=
Vr1 - Vbe(Q9)
Consequently, the internal input voltage levels, which are normally centred around Vrl, are emitter follower shifted to switch properly against Vr2. The use of Vr2 as the primary reference requires the use of Vr3 as the second-level reference.
this case,
Vr3
=
Vr2 - Vbe(Q13)
Note that Vr3 is offset from Vrl by 2 Vbe voltages, and thus represents a true third level seriesgating reference. This low voltage reference necessitates the use of a current mirror circuit in order to ensure an acceptable diode stacking for lOOK operation.
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B
!I2
U!
llCH
(=
l
The diode stacking can be illustrated with reference to Fig. 4, which represents the conventional lOOK current source based approach as in [1], [2], and [3].
In this circuit, note that Vr2 and Vr3 follow ECL VCC, while VCS follows ECL VEE. So the lowest voltage on the collector of the current source transistor, Q8, with respect to ECL VCC, is:
=
Now, the voltage at the base of this current source transistor, Q8, with respect to ECL VCC is:
=
+ VCS
Therefore,
=
+
=
+ VCS - ECL VCC + /VrJ/ + Vbe(Q12)
=
+ VCS + /Vr3/ + Vbe(Q12)
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Let us nonnalize our reference voltages in tenns of the nominal bipolar transistor forward conduction voltage, Vbe. Further, let,
Vbe = Vbe(Q12)
Then, and,
VCS =
Vbe
IVr31 = 3.4 Vbe
Therefore,
Vbc(Q8)
=-
JECL VEEj + VCS + jVr3j + Vbe(Q12)
=-
JECL VEEj +
Vbe +
Vbe + Vbe
=-
JECL VEEj + 6.1
Vbe
This means that,
ECL VEE = -6.1
Vbe + Vbc(Q8)
If we restrict the maximum forward bias voltage on the base collector junction of transistor Q8 to less than 0.5 Vbe, then,
ECL VEE min.
=
-6.1
Vbe + O. 5Vbe
=
-5.6
Vbe
The nominal forward conduction voltage of the ECL switch transistors, Vbe, varies inversely with temperature. In our design, transistors are designed to conduct nominal ICS with Vbe
76Q mV at room temperature. Typically, this Vbe will vary with temperature at - -1.6mV
10C.
Temp. (oC)
-55 o
125
Vbe (mV)
890
800
760
600
Since our design is required to operate at 0 oC, we can defme the ECL VEE min. requirement.
ECL VEE min.
= -5.6
Vbe
=
-5.6
*
800 mV
=
-4.48
V
Typically, a VLSI IC device is housed in a package. In our case, a pin grid array (PGA) package is used. Studies indicate that we can expect an
mV IR voltage drop each on the ECL vec and
ECL VEE pins. Also, the power distribution scheme on our IC creates a load-dependent IR gradient of
mVeach on the ECL VCC and ECL VEE busses. These IR drops must be properly accounted for in the ECL VEE min. requirement,
ECL VEE min.
=
V - 0.12 V = -4.60 V
The minimum ECL VEE in [3] is -4.7V. This ECL VEE min. requirement exceeds the lOOK ECL
VEE min requirement of -4.2V at the package power inputs. Therefore, we cannot use the conventional circuit of Fig. 4 for our lOOK output driver.
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!I2
n!
!
B
VX
+ CI»
(=
.Q8
We developed the schematic shown in Fig. 3 to improve the ECL VEE min. functionality of our
VLSI IC design. The use of a current mirror effectively reduces the ECL VEE min. require:ments to acceptable levels. The diode stacking can be illustrated with reference to Fig. 3, which represents our lOOK approach. In this circuit, the lowest voltage on the collector of the (:urrent source transistor, Q8, with respect to ECL VCC, is:
Vc(Q8)
=
ECL VCC - /Vr3/ - Vbe(Q12)
Now, the voltage at the base of this current source transistor, Q8, with respect to ECL VCC is:
Vb(Q8)
=
ECL VCC - JECL VEEj + Vbe(Q8)
Therefore,
Vbc(Q8) = [ECL VCC - /ECL VEE/
= ECL VCC - /ECL VEE/
+ Vbe(Q8)] - [ECL VCC - /Vr3/ - Vbe(Q12)]
+ Vbe(Q8) - ECL VCC
=-
/ECL VEE/ + Vbe(Q8) + /Vr3/ + Vbe(Q12)
+ /Vr3/ + Vbe(Q12)
Let us nonnalize our reference voltages in tenns of the nominal forward conduction voltage, Vbe.
Further, let,
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and,
Vbe = Vbe(Q12) = Vbe(Q8)
/VrJ/
=-
3.4
Vbe
Therefore,
Vbc(Q8)
=-
/ECL VEE/ + Vbe(Q8) + /VrJ/ + Vbe(Q12)
=-
/ECL VEE/ + Vbe + 3.4
Vbe + Vbe
=-
/ECL VEE/ + 5.4
Vbe
This means that.
ECL VEE
=
-5.4
Vbe + Vbc(Q8)
If we restrict the maximum forward bias voltage on the base collector junction of transistor Q8 to less than 0.5 Vbe. then.
ECL VEE min.
=
-5.4
Vbe + O.
5Vbe
=
-4.9
Vbe
Our design is required to operate at 0 oC. we can define the ECL VEE min. requirement.
ECL VEE min.
=
-4.9
Vbe
=
-4.9
*
800 mV
=
-3.92
V
Accounting for IR voltage drops,
ECL VEE min.
=
-3.92
V· 0.12 V
=
-4.04 V
This ECL VEE min. requirement is well within the lOOK ECL VEE min requirement of -4.2V at the package power inputs.
We have shown the impact of internal ECL circuit optimization - with respect to logic swing and component count· on ECL output circuit design. The additional design constraints added by lOOK operation requirements are also addressed. We find that the resulting circuit requires a new framework for effective lOOK optimization of VOH, VOL temperature dependence. The following section develops this framework, and provides some guidelines for lOOK optimization.
Thus far, we have presented design trade-offs based on functionality and diode stacking considerations, which have led to the use of an effectively three-level series-gated ECL output driver. In order to accommodate three-level deep series-gating, this circuit employed a current mirror technique to reduce maximum voltage diode stacking to within lOOK ECL VEE min. limits.
lOOK output levels, as distinct from lOKH output levels. exhibit near-perfect independence from temperature and power supply voltage variations. In particular, as the IC junction temperature is varied from 0 degrees C to 125 degrees C, we find that the IC output lOOK levels remain within the temperature invariant bounds,
-880 mV
-1625mV
<= VOH <= -1025 mY,
<= VOL <= -1810 mY.
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Now we explore the design trade-offs required for successful lOOK operation of this circuit.
VOH, VOL equations are first presented, followed by dVOH/dT and dVOljdT equations. The design trade-offs inherent in these equations are then discussed, and some optimization recommendations made.
The VOH, VOL equations for the lOOK series-gated ECL output driver as shown in Fig. 3, are:
VOH= -{n
* h**2
*
RC
(h+l)**2 RCM
(VCS-VBE) - 2RC*VIT - VDH
(h+l)RT
+ 3VBEH}/{3 + 2RC )
(h+l)RT
VOL= -{2n
* h**2
*
RC
(h+l)**2 RCM
(VCS-VBE) - 2RC*VIT
(h+1)RT
+ VDL + 3VBEH}I{3 + 2RC )
(h+l)RT
In these equations, h n = Number of Emitters in the current mirror transistor. Defines Irefvs. ICM ratio.
=
Transistor forward conduction current gain, commonly referred to as "Beta".
RC = Output comparator collector resistor (See Fig. 3).
RCM
Current mirror resistor (See Fig. 3).
VCS = Current Source voltage reference. VX-VBE = VCS. (See Fig. 3)
VBE = Transistor forward conduction voltage, for Q7 (See Fig. 3).
VTI
=
Output termination voltage, typically -2V.
RT = Output termination resistor, typically 50 Ohms.
VOH
=
Transistor forward conduction voltage for Q5 (See Fig. 3).
VOL = Transistor forward conduction voltage for Q4 (See Fig. 3).
VBEH = Transistor forward conduction voltage for Q6 (See Fig. 3).
Through these equations, we find that the temperature dependence of VOH and VOL can be adjusted by tuning the RC/RCM ratio. This is a unique aspect of this circuit. It effectively invalidates the application of conventional lOOK output circuit temperature analysis to this problem. Therefore, we develop a new analysis which can be used to successfully design the appropriate lOOK temperature independence. In order to do this, we must first select the desired
VOH and VOL levels. Once these are known, we can solve for RC and RCM from the equations presented above. Since RCM defines the output comparator current, ICM, it effectively controls the propagation delay of the output circuit also. Throught the use of computer-based circuit simulators, such as SPICE, we can determine the appropriate ICM required to meet delay performance objectives. This required ICM dictates the appropriate RCM value. The RC value is then determined based on the required output logic swing. Since RC has a direct impact on the
VOHmax. requirement, in practice IeM is over-designed to ensure an acceptably small value for
RC. Typically, RC is less than 300 Ohms.
Once initial RC, RCM and n values have been determined, we can find anew, more optimized,
RC/RCM ratio by solving the equations given below simultaneously. Note that the RC/RCM ratio affects not only VOH and VOL, but also dVOH/dT and dVOljdT. Thus the new RC/RCM ratio derived above is not optimized for VOH, VOL temperature compensation. VOH, VOL, dVOH/dT and dVOL/dT need to be solved simultaneously in order to obtain minimal temperature dependence. Therefore, we develop a unique technique to achieve desired VOH, VOL with minimal dVOH/DT and dVOljdT as follows.
ECL
VOH & dVOH/dT EQUATIONS
Assume A and B are both at a logic H (high) in order to obtain a logic H at the output
VOH= -{n * h**2 * RC
(h+1)**2 RCM
(VCS-VBE) - 2RC*VIT - VDH
(h+l)RT
+ 3VBEH}I{3 + 2RC )
(h+1)RT
(1)
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dVQH= - rLl{n* h**2 dT
*
Re (VeS-VBE) - 2Rc*m - VDH + 3VBEH}/{3+ 2Re )} dT (h+1)**2 ReM (h+l)RT (h+l')RT
(2)
VBE = (KTlq) IN {(VX 2*VBE)I(IS*ReM)}
VDH
=
KL*ln{ n*k**2*RC*IS*EXP(VBE/VT) - RC*UVOH-WU((h+J)*RTH - VDH} q 3*Re~S
(4)
VBEH
=
(KT/q) *In{k*(YOH WU
RT*IS where k = [h/(h+l)} (5)
In equation 4, IS represents the transistor saturation leakage current. With RC and RCM known, equation (1), (3), (4) and (5) require a simultaneous iterative solution of VOH, VBE, VBEH and
VDH. Once VBE, VBEH and VDH are known, their temperature coefficients can be obtained using the general equation as follows: dYBE =.YllE-- YI.13
+ V~Q
dT T T T*VT
=
VBE w-lK
T T q
Where VBE is the nominal base emitter forward voltage of any transistor.
With the RC, RCM, VCS, VBE, VBEH, VDH and RT temperature coefficients known, and since
VCS, VBE, VBEH and RT temperature coefficients do not depend on the ECL output circuit, dVOH/dT can be best adjusted to zero by tuning the RCM and RC values without changing the
VOH level. This can be done by solving VOH and dVOH/dT equations for RC and RCM.
However, the new RC and RCM values affect the VBE, VBEH and VD values, whkh are proportional to their temperature coefficients. For an accurate result, more iterations are needed by substituting RC and RCM values into the equations (1), (3), (4) and (5) and repeating the above calculation steps until an acceptable convergence is achieved.
ECL
VOL & dVOL/dT EQUATIONS
The output is at a logic L when either A or B is low or both A and B are low. However, depending on the logic of A and B, the VOL equation is derived differently. The following are the two cases:
CASE
When A is low or high, and B is low, VOL is observed at the output of this circuit.
VOL and dVOljdT equations are obtained as follows:
VOL= -(2n
* --h..*
Re
(h+l) ReM
(VeS-VBE) - 2Re*m + VDL + 3VBEH}/{3 + 2RC )
(h+l)RT (h+l)RT
(7)
dY..QL.= -.Ji.[(2n *--h..-* Re (VeS-VBE) - 2Re*w + VDL + 3VBEH}I{3 + 2Re
dT dT (h+1) ReM (h+1)RT (h+l)RT
Tandem Computers 8/9/88 15

When B is high and A is low, VOL is observed at the output of this circuit. VOL and dVOUdT equations are obtained as follows:
VOL= -{2n
* h**2
*
RC
(h+
ReM
(VCS-VBE) - 2RC*YIT + VDL + 3VBEH}/{3 + 2RC }
(h+1)RT (h+1)RT
dY.QL.= -.d.
[{2n
h**2
Re (VeS-VBE) - 2Re*m + VDL + 3VBEH}/{3 + 2Re }] ar ar
(h+1)**2 RCM (h+1)RT (h+1)RT
(10)
The only difference between Eq.
(8) and Eq. (10) is the additional h/(h+ 1) factor in Eq. (10) which is always smaller than one. Therefore, Eq. (8) is greater than Eq.
(10).
Since Eq. (8) is greater than the Eq.(lO), there is a very negligible error obtained if Eq.(10) is ignored. Therefore, we will use Eq.(8) to obtain a desirable VOL level with minimal dVOUdT.
With equations (11), (12), (13), the RC and RCM values are solved using the same method as explained in the VOH section.
VBE = (KT/q)
*
In {(VX - 2*VBE)/(IS*RCM)}
VDL = KI.
q
*
In ( n*k*RC*IS*EXP(YBE/VT) + RC*UVOL-WU((h+ll*RT)l - VDU
*
RC
*
IS
(11)
(12)
VBEL
=
(KT/q)
*
In (k*(VOL-W)/(RT*IS)} (13)
To achieve dVOH/dT =
and dVOL/dT =
two different ratios of RC/RCM are required, as can be seen from our analysis. This means that we cannot simultaneously get zero temperature dependence for both VOH and VOL. Since we have to choose one ratio of RC/RCM to get the physical RC and RCM values, an optimal way to determine this ratio is to equate dVOH/dT and dVOUdT, dVOH/dT = dVOUdT, and solve for RClRCM. By using this criterion, desirable VOH and VOL and minimal dVOH/dT and dVOUdT can be achieved.
In the following graph, titled VOH & VOL VS. RC/RCM, we present various RC/RCM ratios, and show their impact on VOH, VOL, dVOH/dT and dVOUdT. We find that the optimal values for our application are,
RC = 269 Ohms
RCM = 631 Ohms
RC/RCM
=
0.43.
Tandem Computers 8/9/88 16

VOH at VOL VS. RC/RCM
With these optimized values, the perfonnance of the output driver is,
Output Levels
= f(Junction Temperature, degrees C) Comments
0 25 125
VOH(mV)
VOH(mV)
VOH(mV)
VOL(mV)
VOL (mV)
VOL(mV)
= -979
= -1000
= -995
= -1778
= -1775
= -1755
-959
-975
-980
-1752
-1750
-1735
-892
-910
-920
-1681
-1645
-1660
Predicted
Simulated
Measured
Predicted
Simulated
Measured
In the next graph, titled PREDICTION VS. SIMULATION VS. MEASUREMENT, we present predicted, simulated and measured perfonnance of our output circuit based on the values stated above. In general, we find good agreement between prediction and measurement. Since our simulations are for the nominal process, and do not acount for long metal interconnect between the base of
and
in Fig.
we find some deviation between measured and predicted perfonnance. This slight deviation also reflects upon the accuracy of computer models for our devices.
Tandem Computers 8/9/88 17

PREDICTION VS. SIMULATION VS. MEASUREMENT
We conclude that our analytical framework, as presented in this paper, has thus been verified by actual measurements.
In this paper, we have attempted to illustrate the complex, inter-related design optimization choices required to achieve efficient, high speed silicon bipolar ECL VLSI ASICs. We presented three possible design choices for an IC-internal comparator circuit, and then showed how our chosen design methodology ensures adequate VNMH and VNML values and creates an optimal total logic voltage swing, VI, without requiring a common mode resistor. It reduces the excessive VNMH of the conventional approach by developing a reference voltage optimized for internal voltage swing values. The benefits of this technique are a 30% reduction - from 845 mV to 600 mV - in the total logic swing, without any loss of high or low noise margin. Thus the delay performance of the circuit is improved significantly without requiring any increase in power dissipation.
We then showed the impact of this optimization on output driver circuit design, and for example, the need for a new analytical framework to understand the lOOK performance of the chosen output circuit design. An analytical framework for the WOK temperature compensation of an effective three-level series-gated ECL output driver was then developed and presented. To minimize overall temperature dependence of VOH and VOL, we proposed, dVOH/dT = dVOL/dT as the optimization criterion. This is a requirement because, in order to achieve dVOH/dT = 0 and dVOl../dT = 0, two different ratios of RC/RCM are required. Since we have to choose one I1ltio of
Tandem Computers 8/9188 18

RC/RCM to get RC and RCM values, the best way to determine this ratio is to equate dVOH/dT and dVOLJdT (dVOH/dT
= dVOLJdT) and solve for RC/RCM. By this method desirable VOH and VOL and minimal dVOH/dT and dVOLJdT can be achieved.
The actual circuit used in our ECL VLSI ASIC devices conformed to this criterion. Thes devices are the basis of a high speed digital system currently under development. Results from this analysis have been shown to agree quite well with actual measurements made on such VLSI devices, as well as computer-aided simulations.
REFERENCES
[1] P. R. Marley, "On-chip Temperature Compensation for ECL," Electron Products, Mar. 1,
1971.
[2] P.
R. Marley, "Design Considerations of Temperature Compensated Emitter Coupled Logic," presented at the IEEE Int. Conv., Mar. 1971.
[3] H. H. Muller, W. K. Owens, and P. W. J. Verhofstadt, "Fully Compensated Emitter-Couple
Logic: Eliminating the Drawbacks of Conventional ECL," IEEE Journal of Solid-State Circu:lts, vol. SC-8, No.5, Oct. 1973.
AUTHORS
A. Khan is Manager of Bipolar VLSI Development at Tandem Computers,
Inc.
He has been at Tandem since October, 1983, where he has been involved with chip architecture, circuit design and CAD methodology aspects of high performance bipolar ECL ASIC design, as well as high speed system interconnect issues. In March 1988, he received Tandem
TOPS, and in May 1988, he received the Tandem TSD Award for Technical Excellence. He holds several patents in high speed circuit desigin for ECL VLSI ICs.
In December 1975, Aurangzeb completed a B.Sc. at the University of The Punjab, in Pakistan, in
Physics/Mathematics, with highest academic honors. He then attended University of Califomia at
Berkeley, completing a double major BSEECS, BSNE (Electrical Engineeering and Nuclear
Engineering) in December 1978.
In January 1979, he joined Fairchild Semiconductor to design high speed ECL static RAMs. Concurrently, he attended Stanford University where, in March
1981, he obtained an MSEE, and in June 1984, an MSEM.
Aurangzeb played varsity and competitive Squash Racquets in Pakistan, at Berkeley and at Stanford.
He is interested in photography and travel.
Duc Le was born in Vietnam, on July 29, 1961. As a result of the war, he left his own country and arrived in the USA in June 1980. Mr. Le received the B.S. degree in Electrical
Engineering and Computer Science from University of California at Berkeley. In June 1988, he completed an MSEE degree at Stanford University in Electrical Engineering and Computer
Science.
Mr.
Le is a bipolar VLSI Development Engineer at Tandem Computers, Inc. in
Cupertino, California. His work includes analysis and design of Bipolar ECL gate arrays. He also contributes to CAD tool development. Mr.
Le is a member of the IEEE.
D. V. Nguyen graduated with a B.S. degree in Electrical Engineering and
Computer Science from University of California at Berkeley in 1986. Currently, he is pursuing a
M.S. degree in EECS at University of Santa Clara. In 1986 he joined Tandem Computer Inc., where he has been involved in high-speed ECL circuit design and development. His main areas of interest
high-speed circuit design and VLSI technology. Mr. Nguyen is a member of the IEEE and Tau Beta Pi.
Tandem Computers 8/9/88 19

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