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1
Analyzing the Inherent Reliability of Moderately
Sized Magnetic and Electrostatic QCA Circuits via
Probabilistic Transfer Matrices
Timothy J. Dysart, Student Member, IEEE, and Peter M. Kogge, Fellow, IEEE
Abstract—As computing technology delves deeper into the
nanoscale regime, reliability is becoming a significant concern,
and in response, Teramac-like systems will be the model for
many early non-CMOS nanosystems. Engineering systems of
this type requires understanding the inherent reliability of both
the functional cells and the interconnect used to build the
system, and which components are most critical. One particular
nanodevice, quantum-dot cellular automata (QCA), offers unique
challenges in understanding the reliability of its basic circuits
since the device used for logic is also used for interconnect. In
this paper, we analyze the reliability properties of two classes
of QCA devices: molecular electrostatic-based and magneticdomain based. We use an analytic model, probabilistic transfer
matrices (PTMs), to compute the inherent reliability of various
non-trivial circuits. Additionally, linear regression is used to
determine which components are most critical and estimated the
reliability gains that may be achieved by improving the reliability
of just a critical component. The results show the critical
importance of different structures, especially interconnect, as
used by the two classes of QCA.
Index Terms—Nanoelectronics, circuit reliability, probabilistic
transfer matrices, quantum-dot cellular automata (QCA)
I. I NTRODUCTION
P
OWER dissipation, defects, and process variations are
only a few of the factors that challenge silicon technology
as it continues scaling into the nanoscale regime. Today,
research is continuing on materials, devices, and architectures
that can augment, and potentially replace, silicon technology
to limit the impact of these factors. One significant challenge facing both silicon and these new technologies is that
of reliable computation. A variety of techniques like spare
devices and error correcting codes are frequently used today in
memory structures, while other techniques like von Neumann
multiplexing, modular redundancy, and reconfigurable systems
are in use or proposed for use with new nanoscale logic
architectures. References [1]–[5] offer a sampling of this work.
With the majority of proposed nanoscale architectures using
reconfigurable logic blocks, many early nanoscale systems
using augmented silicon technology or other nanoelectronic
devices will probably take the form of the Teramac [6] to
provide a capable, reliable system. To build such a system
successfully, a strong subset of these logic blocks will need to
Manuscript received February 1, 2008; revised July 12, 2008. This work
was supported by the National Science Foundation under grant CCF-0541324
and the U.S. Department of Defense.
T. J. Dysart and P. M. Kogge are with the Department of Computer Science
and Engineering, University of Notre Dame, Notre Dame, IN, 46556 USA email: {tdysart,kogge}@nd.edu.
be operational in the presence of defects introduced during the
manufacturing process. As a result, methods for computing the
reliability of these logic blocks and identifying potential reliability improvements is necessary. These reliability calculations
may need to consider both logic and interconnect, rather than
just logic as is commonly done, since some nanoelectronic
devices utilize the same device for logic and interconnect.
A particular nanoelectronic architecture, quantum-dot cellular
automata (QCA), is a specific example of this case because
logic and interconnect components are both built from specifically arranged device cells. This device sharing has significant
implications when computing circuit reliability.
To complicate matters further, QCA has been implemented
in both electrostatic and magnetic technologies. Electrostatic
QCA depends on charge configuration to transmit information,
while magnetic QCA uses magnetic dipoles to transmit information [7]. The choice of implementation has a significant
impact on circuit reliability since each implementation has
its own method of routing signals, particularly when signals
must cross “perpendicularly”. In particular, an electrostatic
wire crossing is replaced by a logical circuit [8] while a simple
configuration of a few nanomagnets accomplishing the same
task may be available for a magnetic implementation [7].
The circuits considered here, adders, multiplexers, and parity trees all of varying sizes, are likely to be either contained
in or similar in size to a logic block in a Teramac-like system.
In this paper, we will determine the inherent reliability of
these moderately sized QCA circuits when considering both
electrostatic and magnetic implementations. This reliability
will first be calculated with all components having the same
error rate. However, doing this only tells part of the story
because component error rates may not be well known and
different components may influence the overall circuit reliability differently. To address these concerns and to guide
future research on improving circuit reliability via device
and/or component reliability enhancement we utilize linear
regression as a structured method for discerning which circuit
components have the largest impact on circuit reliability. The
regression results are then used to show how component
reliability enhancement can impact overall circuit reliability.
In this work, we expand and generalize our initial results,
presented in [9], [10], on this topic.
To compute circuit reliabilities, we use the probabilistic
transfer matrix approach of [11], [12] which has also been
used in [13], [14]. This analytical method is preferred since
it is both quick and eliminates the need for physical QCA
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cell details. Other models, such as the Bayesian networks
of [15], [16] can estimate circuit reliability rapidly, but still
require physical parameters such as cell size and temperature.
Abstracting away physical details allows the results generated
here to be applicable to a wider range of circuits, which is
beneficial because implementations for each class of QCA
may vary significantly. For example, in electrostatic QCA,
molecular cells may be densely packed or be located on a
DNA substrate with wider spacings between cells. In magnetic
implementations, the nanomagnet size and spacing may vary.
Section II discusses background material. An example of
the PTM method is presented in Sec. III. Section IV shows
the circuits used in this work. Section V discusses circuit reliability with uniform error rates for the components. Reliability
as a function of circuit complexity is presented in Sec. VI.
Linear regression is used in Sec. VII to determine which
components are most important while Sec. VIII shows how
circuit reliability can be improved by increasing the reliability
of the most important component. Section IX concludes.
II. BACKGROUND M ATERIAL
Fig. 1.
Electrostatic wire crossing.
and rotated cells (45 degree wire). However, if molecular cells
are used, then sub-Angstrom level precision will be required
to place each cell for the crossover to function properly [28].
However, a simple combinational circuit capable of crossing
wires without using 45 degree wires can be formed [8], and
is described in more detail in Sec. IV. Since a magnetic QCA
implementation might be able to have an explicit wire crossing
component [7] similar to a logic gate, this paper examines the
reliability differences in several circuits when using the logical
crossover and the crossing component.
A. Introduction to QCA
The quantum-dot cellular automata (QCA) architecture is
built upon a foundation of simple, identical, bistable devices
that interact with one another via electromagnetic forces. The
initial devices for QCA were charge based (electrostatic) and
utilized a square cell of four quantum dots with potential
barriers between the dots. Within the cell are two free electrons
capable of tunneling through the potential barrier, which could
be clock-controlled, that settle on different quantum dots due
to Coulombic interaction [17]. The energetically favorable
states of these cells would have the electrons in opposing
corners (along a diagonal). Since there are two diagonal
configurations available, the cell is bistable. Neighboring cells
interact by Coulombic forces, and by aligning multiple cells
in specific configurations a universal set of logic gates can be
constructed. Electrostatic QCA devices have been developed
and tested using metal-dot cells [18]–[20] and molecular QCA
devices have been investigated [21]–[25].
A non-charge based QCA implementation, namely magnetic
QCA, is currently being investigated and shows significant
promise [26], [27]. Within magnetic QCA the magnetization
state of a nanomagnet provides a stable value. A single,
rectangularly shaped, nanomagnet will have its magnetization
align along the long axis (longer side of the rectangle) of
the nanomagnet. Depending on the external forces, the magnetization of a nanomagnet with its long axis being vertical
will be either straight up or down, thus satisfying the bistable
constraint required by the QCA architecture. In general, two
nanomagnets are roughly equivalent to a four dot electrostatic
cell. Similar to the electrostatic QCA implementations, the
positioning and alignment of multiple nanomagnets will determine the specific function that is implemented.
We refer the reader to [9] for a simple cartoon showing the
basic QCA components in electrostatic and magnetic forms.
The wire crossing structure shown in Fig. 1 can be utilized for
electrostatic implementations with unrotated (90 degree wire)
B. Introduction to PTMs
Probabilistic transfer matrices (PTMs) were described in
[11] as a method for accurately computing the reliability of
a combinational circuit given error prone components. Each
component has its own PTM, and by combining these matrices, based on the circuit structure, using Kronecker products
and matrix-matrix products, a PTM for the circuit is formed.
A series of operations are then performed on the circuit PTM
to calculate the circuit’s reliability.
The PTM for a component (circuit) with m inputs and n
outputs is a 2m × 2n matrix that, when error-free, is the truth
table for the component. This matrix shows the relationship for
all combinations of inputs and outputs for the component and
with the specific relationship between input combination i and
output combination j located at (i, j) in the matrix. The errorfree PTM is generally referred to as an ideal transfer matrix
(ITM). If the component produces an incorrect output with
probability p (error rate), regardless of input values, erroneous
input/output combinations are represented by p in the PTM and
desired input/output combinations are represented by 1 − p.
Note that within a PTM the sum for all of the entries in a row
must be ≤ 1, in other words, for a given input combination,
the potential outputs cannot have a probability greater than
one of occurring. The PTM and ITM for a majority gate with
error rate p is shown in Fig. 2(a).
A circuit PTM is generated by first dividing the circuit into
slices that are one component level each, i.e. no level has
a series of components. Within a level the components are
in parallel, and the Kronecker product1 is calculated for the
level, thus giving each level a PTM. These level PTMs are then
1 The Kronecker product, denoted by ⊗, is block matrix multiplication
where with a m × n matrix A and a p × q matrix B results in a mp × nq
matrix. For example, consider A and B to each be a 2 ×h2 matrix. In this case
i
a1,1 B a1,2 B
a 4 × 4 matrix of the following form results: A ⊗ B =
a2,1 B a2,2 B
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(RCR). This point is equivalent to 1/2n where n is the number
of output bits and is obtained when component error rates are
50%. This value tends to act as a soft, but not absolute, lower
bound on the circuit reliabilities shown here. Increasing the
component error rate beyond 50% can increase the circuit
reliability, albeit very slightly, since PTM modeling does
account for multiple failures generating a correct answer (i.e.
two wrongs make a right).
3
(a) ETM calculation
C. Related Work
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(b) Reliability calculation
Fig. 2. Reliability calculation for a majority gate with error rate p and a
uniform input distribution.
multiplied, from circuit inputs to outputs, using normal matrixmatrix multiplication to generate the circuit PTM. At each
stage of this process, the size of the PTM corresponds to the
number of inputs and outputs as discussed above. Examples
of circuit PTM construction can be found in [9], [10].
To generate the reliability for a circuit from its PTM [12],
the PTM is element-wise multiplied (ai,j ∗ bi,j = ci,j ) with
its ITM to form an element transfer matrix (ETM). This
multiplication is shown in Fig. 2(a) using just a single error
term p for example purposes. The ETM zeros out erroneous
input/output combinations, thus leaving only desirable input/output combinations. The ETM is then left-multiplied by
an input row vector, v, whose values are the probability of
each input combination occurring. To continue the example,
assume v is a 1x8 row vector with each element being 0.125,
which gives each input combination an equal probability of
occurrence. This multiplication, shown in Fig. 2(b) leaves
v ∗ ET M = [0.625(1 − p) 0.375(1 − p)] with each entry
of v ∗ ET M corresponding to the probability of a specific
output occurring. The total circuit reliability is the result of
summing the elements of v ∗ ET M , 1 − p in this example.
Another example of this computation is provided in Sec. III.
The component PTMs used here are: AND, OR, and MAJ
gates; inverters; wires; single bend wires; T-shaped fanouts;
regular fanouts; and wire crossing devices (magnetic implementations only). For this work, the error rate for the AND
and OR gates matches that of the majority gates. By assuming
that the fixed input to a majority gate (which would turn it into
an AND or OR gate) is error-free, the overall complexity of
the PTMs are reduced. In order to properly derive the PTM
for the fanouts and the wire crossing component, the error rate
p is divided by 3 for incorrect output combinations to prevent
the row sum from being greater than one.
An interesting point when computing circuit reliability via
PTMs is what we have termed the random circuit reliability
1) Reliability Enhancements: This work can guide future
research on improving circuit reliability since it will specify
which components should be made more robust first. A
significant body of work is available in the literature that
observes the impact of defects on the operation of a component
or a circuit, but work addressing how component reliability
may be improved has been more limited. It should be noted
that reliability enhancement studies have been limited to
electrostatic QCA and that we are unaware of any work on this
topic for magnetic QCA. A brief survey of this work is below,
but a significant question remains: how much enhancement is
good enough? This paper begins to address that question.
Fijany and Toomarian [29] centered their efforts on detailing
how the basic majority gate can be modified into a “block
majority gate” where multiple cells are arranged in a rectangle
and operate as a single gate. The block majority gate is found
to be more resistant to defects like cell misalignment, cell
rotation, and missing cells. This work also demonstrated that
thick input wires may also be beneficial to the operation of
a block majority gate. However, this work did not 1) identify
an ideal block majority gate size, 2) provide any guidance as
to error rates for the majority gate, nor 3) determine the ideal
locations for the inputs of the majority gate.
[30]–[34] examine how straight wires can be made more
robust. The common trait among these works, similar to the
results of [29], is that increasing the “thickness” of the wire
by having multiple cells in parallel, increases its resilience to
defects. [30] observes the impact of stray charge on a metal-dot
cell wire. [31] examines temperature and misalignment defects
for metal-dot cells. [32] considers rotations and displacements
for clocked molecular cells. [33] and [34] consider missing
cells in straight and bent wires for clocked molecular cells. For
[33], [34], error rates for the components have been estimated,
but these results are limited since defect rates for molecular
QCA are not know and the tested wires were of a fixed length.
2) QCA Circuit Reliability: Bayesian networks have recently been proposed as a method for computing the probability of obtaining the correct output of an electrostatic QCA
circuit [15], [16]. While this method is computationally significantly quicker than the coherence vector model of QCADesigner [35], both rely on quantum mechanical principles. In
doing so, physical parameters such as temperature, cell size
and spacing, and clock strength are required. The method in
this paper is purely analytical; thus the electrostatic results
are applicable to a wider range of potential implementations.
However, Bayesian modeling may be appropriate for quickly
exploring the physical design space (i.e. cell size and spacing)
4
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h
h
0.865 0.135
0.135 0.865
(a) Wire PTM
i
0.8652 + 0.1352 = 0.7665
2 ∗ (0.865 ∗ 0.135) = 0.2335
2 ∗ (0.865 ∗ 0.135) = 0.2335
0.8652 + 0.1352 = 0.7665
(b) Two wire segment (circuit) PTM
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(c) Final reliability calculation for the two segment wire
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Calculating circuit reliability from a PTM
of a component, and may enable refinements to this work by
providing more data on component error rates.
A method for estimating the yield of electrostatic and magnetic QCA programmable logic arrays (PLAs) can be found in
[36]. This work utilizes a new parameter, the effective defect
rate (EDR), to capture the probability that a specific defect
type (i.e. displacement) causes a QCA cell to malfunction
since not all defects will cause a QCA cell failure. The EDR
is then used to compute the probability that a defect of type x
will cause a fault in the PLA cell. The probability of a fault in
the PLA cell is then computed using the probability of a fault
for all defect types. The yield of the PLA is then computed
as a function of the PLA cell probabilities. The results of
[36] demonstrate that PLA yield can drop significantly once
a certain EDR is reached. The EDR causing this drop varies
based on the circuit size; larger circuits require lower EDRs
than smaller circuits to have the same yield.
III. PTM E XAMPLE
In this section, we compare PTM results to those obtained
by physical simulation for two straight wire segments connected in series. This comparison also provides a concrete
example of PTM construction and computing the resulting
circuit reliability. Before a PTM for a wire segment can be
constructed, computing the wire error rate is required.
The experimental setup of [33] is reused here to determine
the reliability of a short wire segment built from densely
packed molecular QCA cells. In [33], physical simulation
determined the reliability of wire segments when cells were
randomly dropped from the wire segments. For this experiment, a wire segment of ten cells long and three cells wide
was constructed. 20% of the cells were then randomly dropped
from the wire. Simulation was then performed to determine if
the wire transmitted both a logical 0 and a logical 1 properly;
if so, the wire passed, else it failed. After completing 5000
iterations, a failure rate of approximately 13.5% was observed.
Using this failure rate, the reliability of two wire segments
connected serially is calculated to be 76.65% using the method
described in Sec. II-B. Figure 3 shows the wire segment PTM,
circuit PTM, and final reliability calculation for this circuit.
The ITM for the wire (used to calculate the ETM) is simply
the 2 × 2 identity matrix. In this example, we have assumed
that logical 0 and 1 have equal input probabilities.
A twenty cell long, three cell wide wire was then created
for physical simulation in the same manner as the single wire
segment. In order to treat this as two separate wire segments
linked in series when dropping cells, 20% of the cells in the
the first ten cells (long) were dropped along with 20% of the
cells in the second ten cells (long). Again, 5000 iterations of
this wire were considered and a failure rate of 17.5% (pass
rate of 82.5%) was observed.
This passing rate is higher than both that of the PTM
model of 76.65% and that of a simple combinatorial model
which predicts a pass rate of 74.82%. The value for the
simple combinatorial model is the product of the pass rate
for each wire segment since the segments are connected in
series. The difference between the combinatorial and PTM
models is explained by the extra terms in the (1,1) and (2,2)
locations of Fig. 3(b). In the combinatorial model, only the
two correct cases are considered (0.865*0.865), whereas in
the PTM model, the correct case is considered along with the
possibility that both wire segments fail, thus a proper result is
still obtained. The probability of two wrongs making a right
is captured in the 0.135*0.135 terms in Fig. 3(b).
Since the pass rate obtained by physical simulation is
higher than both models, it suggests that the two wrongs
making a right case may occur more frequently than the PTM
model suggests. There is also the possibility that some of the
variation between the reliability values is a result of 1) limited
or no overlap in the physical simulations and 2) doing so
few iterations with physical simulation. Respectively, approximately 0.85% and 1.4×10−6% of possible combinations were
considered for the single and two segment circuits. Further
studies correlating circuit reliabilities from physical simulation
and PTM modeling are necessary.
A significant advantage of using analytical modeling is that
physical simulation is slow. To compute the error rates for
the single and double wire segments, over 10,000 hours of
computation on a mixture of 2.2 GHz and 2.6 GHz AMD
Opteron servers was needed with approximately one-third
of the computational time going to the single wire segment
results. In comparison, given an error rate for the single wire
segment, computing the reliability for the two wire segment
via PTM analysis required approximately a minute by hand.
While the reliability of the circuit tested in this section
is rather quick to compute, the time required by the PTM
method varies significantly. Matlab, rather than the decision
diagram method described in [11], [12], has been used here.
When selecting circuits to test, the limiting factor is the width
(number of signals) in a slice of the circuit. Using Matlab
limits the width to about 17 or 18 signals as opposed to
the approximately 40 suggested by [11], [12]. With Matlab,
these larger matrices take significantly longer (on the order
of minutes) to compute, especially if memory swapping is
required, than smaller ones. If a large number of slices are of
this maximum width, computing the circuit reliability can be
rather computationally expensive.
IV. C IRCUITS
In this paper, a total of three circuit types are considered:
parity tree, multiplexer, and adder. Additionally, the input sizes
of these circuits are varied to provide four parity tree circuits,
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5
three multiplexers, and four adders for a total of eleven
circuits. Since the magnetic and electrostatic implementations
differ for the multiplexer and adder due to the need for
wire crossings, all seven of these circuits are designed in
both technologies. This gives a total of 18 circuits that are
considered in this work. These circuits are diagrammed with an
approximate layout using the components listed in Sec. II-B.
A. Logical Wire Crossings
The crossover circuit, needed only for the electrostatic
circuits, uses the axiom that A XOR B XOR A = B (similarly,
A XOR B XOR B = A). This circuit, which can be built
entirely from unrotated cells, is shown in Fig. 4(a) with a
single XOR gate being identified in the dotted polygon. The
XOR gate consists of the following components: three AND
gates, an OR gate, an inverter, seven straight wires, two single
bend wires, and a T-fanout. Having to use this logical circuit
to cross wires significantly increases the complexity of the
electrostatic circuits as will be shown shortly.
Several variations of the XOR gate and wire crossing circuit
have been created in order to properly route signals. These
versions differ in which types of wire (straight or single bend)
are used as inputs and as a result, do not impact the complexity
of the circuit. Further details on the wire crossing circuit can
also be found in [9], [10].
B. Circuits Tested
Parity trees, multiplexers, and ripple-carry adders are studied in this work. These circuits demonstrate a variety of
properties, especially as we vary the sizes of each circuit by
increasing the number of inputs. The parity tree circuits under
test calculate the even parity bit which is 0 if the number of
ones in the input vector is even and 1 otherwise. The two input
version of the parity tree is the XOR gate shown above. Four,
six, and eight input parity trees are also considered. Since
these circuits do not require wire crossings, the electrostatic
and magnetic implementations are equivalent.
The multiplexer circuits considered have two, four
(Fig. 4(b), or eight input bits (excluding select bits). An
interesting comparison between these multiplexers is that
the smallest requires only one wire crossing, the four input multiplexer requires eight wire crossings and the eight
input multiplexer requires twenty-seven wire crossings. This
explosion in the number of crossings needed has significant
implications when considering the total number of components
needed to implement each circuit with electrostatic QCA.
The adder circuits tested here are based on the design in
[37] and were also utilized in [10]. A two bit-slice adder is
shown in Figure 4(c).
For the remainder of this paper, the parity tree (Ptree) and
multiplexer (Mux) circuits are identified by the number of
input bits (excluding the select bits for the multiplexers) or
the number of bit-slices for the adder circuits.
C. Circuit Complexity
Figure 5 shows the number of components versus the
number of input bits for the circuits considered here. Unsur-
Fig. 5.
Number of components v. number of inputs.
prisingly, the electrostatic versions of the adder and multiplexer circuits require significantly more components due to
the number of wire crossings in these circuits. When graphs
considering circuit complexity are shown, such as these in
Fig. 5, the select bits for the multiplexers are considered input
bits; thus, 2-Mux has three inputs, 4-Mux has six inputs, and
8-Mux has eleven inputs.
V. U NIFORM E RROR R ATES
In order to begin understanding the inherent reliability of
QCA circuits, we first observe circuit reliability when each
component has the same error rate. Recall that the electrostatic
circuits required six components and the magnetic circuits
required seven components. Since no experimental data is
available on the error rate for QCA components, the error
rates tested in this subsection cover the range from 1.0×10−8
to 1.0×10−1. These values are used since they are higher than
the current CMOS transistor failure rates which are on the
order of 1.0×10−11 to 1.0×10−10 [38].
The graphs of Fig. 6 show the estimated circuit reliability
when all components have the same error rate. We show
only the results for error rates of 1.0×10−4 and higher for
clarity. Results for lower error rates will be discussed shortly.
The reliability axis for the parity tree and multiplexer graphs
starts at 0.5 since this value is the RCR (random circuit
reliability) for all of these circuits. For the adder circuits,
the RCR values are 0.25, 0.125, 0.0625, and 0.03125 for
1-Adder, 2-Adder, 3-Adder, and 4-Adder respectively. The
circuit reliability approaches this value for all of the adder
circuits at high error rates.
The graphs in Fig. 6 provide working ranges of expected
circuit reliability when faulty components are present. As
components are initially designed, built, and tested these
results can be used to identify the types of circuits that can
be prototyped and how reliable these prototypes might be. We
also observe that circuit reliabilities tend to plummet as the
error rate increases beyond 0.1% (1.0×10−3), thus this value
could be considered a reasonable lower bound on component
reliability. We also observe that for larger circuits, the circuit
reliabilities quickly approach their RCR values. This trend is
quite pronounced in the electrostatic circuits as the error rate
increases above 1%. Lastly, when considering these graphs as
a whole, it is apparent that magnetic circuits are more reliable
6
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
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than their electrostatic counterparts. This is a direct result of
the wire crossing method necessary for each implementation.
Rather than show data for component error rates below
1.0×10−4, Table I shows the component error rate required
for each circuit to have a reliability of five nines (0.99999)
or better. For each fewer (greater) nine of reliability that is
acceptable, the uniform error rate necessary to achieve that
reliability increases (decreases) by an order of magnitude.
Considering the two input parity tree, four nines of reliability
is observed at a uniform error rate of 1.0×10−5 and three nines
of reliability is observed at a uniform error rate of 1.0×10−4.
VI. C IRCUIT C OMPLEXITY
VERSUS
R ELIABILITY
In this section we consider how circuit reliability changes as
a function of the circuit complexity. Figure 7 plots the circuit
reliabilities as a function of the number of circuit components.
Graphs could be generated by comparing the reliability to the
number of input bits, but they would be nearly identical and
would preclude the inclusion of a reference line.
For these graphs, the component error rate is uniform and is
shown in the legend. Since the lack of wire crossings keeps the
parity trees from suffering significant increases in complexity
they have been placed in the magnetic graph. Additionally,
these graphs display a reference line, labeled Ref. which is
computed as (1 − err)n where err is the uniform error rate
and n is the number of components. These reference lines
fall below those of the circuits since they do not consider the
circuit structure, two wrongs making a right, or any potential
logical masking. In the electrostatic graph, the multiplexers are
more reliable than the adder throughout. In the magnetic graph,
the parity tree and adder reliabilities tend to nearly overlap
(particularly at the lower error rates) and that there is some
flux in which circuit is most reliable when few components
are needed. However, once approximately 50 components are
necessary, the multiplexer has the highest reliability and the
parity tree the lowest. The lack of logical masking is likely
the main cause for the low reliability of the parity tree.
The linear trends shown in both of these graphs suggests
that increasing the circuit size and complexity will not have a
compounding negative affect on circuit reliability. This impact
may enable fewer large logic blocks to be more effective than
a greater number of smaller logic blocks. Another expected
trend would be that circuits with similar complexities would
have similar reliabilities, which generally is not the case here.
This suggests that two factors may be quite influential: 1)
logical masking and 2) the number of outputs of the circuit.
Estimating the impacts of these factors is beyond the scope of
this study and is left for future work.
The results in Sec. V and here provide a good starting
point for identifying the component error rates necessary to
build reliable circuits and how circuit complexity may impact
reliability. However, these results do not consider how circuits
may be impacted by having component error rates that may
differ by several orders of magnitude. Additionally, they do
not provide any insight as to how each component impacts
circuit reliability. In the next section, linear regression is used
to address these concerns.
VII. R EGRESSION A NALYSIS
The final goal of this work is to develop a guide for improving circuit reliability by enhancing device and/or component
reliability. However, to successfully improve circuit reliability,
we much know the following: 1) which component is the most
important and 2) how much enhancement is required.
In our previous work [9], [10], we used two different
methods to determine which component(s) was the most
important. The method in [10] was a regression analysis over
several orders of magnitude for the circuits. In [9], components
were made error-free (perfect) one at a time and the resulting
reliabilities were compared. One limitation of the results in
[10] is that they do not consider how the number of instances
of each component may impact reliability. We introduce a
method of normalizing the regression results to determine if
this limitation is problematic. The direct regression analysis
and normalized regression results are compared by considering
perfect components.
One of the concerns outlined above was that component
error rates that differ by several orders of magnitude were
not considered. In developing our regression analysis, we
remove this concern by computing the circuit reliability for
all combinations of component error rates that vary by several
orders of magnitude. In particular, each component has its
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Parity Tree
2
4
6
8
Inputs
Inputs
Inputs
Inputs
1.0×10−6
2.5×10−7
1.0×10−7
1.0×10−7
1-Adder
2-Adder
3-Adder
4-Adder
7
Adders
Electrostatic
Magnetic
1.0×10−7
5.0×10−8
2.5×10−8
2.5×10−8
5.0×10−7
2.5×10−7
1.0×10−7
1.0×10−7
TABLE I
U NIFORM ERROR RATE CORRESPONDING TO FIVE
Multiplexers
Electrostatic
Magnetic
2-Mux
4-Mux
8-Mux
2.5×10−7
7.5×10−8
2.5×10−8
1.0×10−6
2.5×10−7
1.0×10−7
NINES RELIABILITY
(a) Parity Tree, High Error Rates
(a) Electrostatic Circuits
(b) Multiplexers, High Error Rates
(b) Magnetic Circuits
Fig. 7. Circuit reliability as a function of the number of circuit components.
Lines are for uniform error rates.
(c) Adders, High Error Rates
Fig. 6.
Circuit reliabilities with uniform component error rates.
error rate stepped from 1.0×10−8 to 1.0×10−2 by orders of
magnitude for each of the eighteen circuits examined in this
paper. This results in 76 (7 is the number of component error
rates tested and 6 is the number of components) data points
for each of the electrostatic circuits and 77 data points for each
of the magnetic circuits. Each data point consists of an error
rate for each component and the resulting circuit reliability.
We do not increase the component error rates to 1.0×10−1
since this had a significantly negative impact on the quality
of the regression results. This decrease in quality is a result
of the circuit reliabilities staying near their RCR values rather
than decreasing to zero at high error rates.
For each circuit, these data points are used to form a linear
function of the form a1 x1 + a2 x2 + ... + an xn + c = r using
regression analysis (n = 6, 7 for the electrostatic and magnetic
circuits respectively). Within the linear function, the xi values
are the input variables, in this case the component error rates,
and r is the circuit reliability that results from a set of specific
set of xi values. The regression coefficients, the ai values,
are directly proportional to the impact the variable xi has on
8
the circuit reliability. The constant c is an intercept term that
ensures that the circuit reliability approaches one as the error
rates decrease (i.e. if the component error rates were zero, then
c = r = 1).
The results of this regression analysis, quickly computed
using Matlab, are shown for the smallest and largest circuits
of each type in Table II. The regression coefficients in the
table are negative because increasing the component error rate,
its xi value, decreases the circuit reliability. When examining a row of the table, the magnitude of the coefficient is
what determines the impact of that variable on the circuit’s
reliability. The larger the magnitude of the coefficient, the
greater the impact of that variable’s influence on the circuit’s
reliability. For the two input parity tree, this means that the
majority gate (MAJ) has the greatest impact on reliability,
followed by the straight wire (W), the single bend wire
(SB), the inverter (NOT), and lastly, the T-fanout (TFAN).
Regular fanouts are under the column FAN, while the magnetic
crossover component is under the column XV.
Since the regression analysis only considers the data points
for one circuit at a time, the coefficients of different circuits
are not correlated in any way and comparing them has limited
value. The only conclusion that can be drawn from comparing
the coefficients between circuits is that the small changes in
component reliability have a more significant impact on circuit
reliability as the circuit size increases; i.e. the magnitude of the
regression coefficient increases as the circuit size increases.
The magnitude of the coefficients in Table II is strongly
correlated with the number of instances of each component.
One concern with this result is that less frequently used
components may actually have a larger impact on circuit
reliability than the regression analysis suggests. Accordingly,
we have normalized the regression coefficients by the number
of instances of that component in the circuit as shown in
Table III. If the components were ordered in this manner for
the two-input parity tree, the ordering would have the majority
gate as the most important component followed, in order, by
the inverter, single bend wires, T-fanout, and the straight wires.
For this specific circuit, this ordering places more emphasis on
the inverter and significantly less on the straight wires.
To determine whether the regular or normalized regression
results are best at selecting the most important component,
we will make the most critical component selected by each
method perfect and then compute the circuit reliability when
the other components are faulty. A simple weighted method
has been used to order the components when all of the circuits
are considered. In this weighted method, the components are
scored from 6 (for electrostatic circuits) or 7 (for magnetic
circuits) going down to 1, with the most important component
having the highest score. The component scores are then
averaged for each technology implementation of the circuits.
The component orderings resulting from this weighted method
are shown in Table IV. For the parity tree circuits, the lack of
wire crossings has no impact on these results being included
in the electrostatic orderings. In the magnetic orderings, the
lack of crossover components has no impact for the regression
ordering when the parity tree circuits are not included and in
the normalized ordering the NOT and XV would swap when
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Regression Ordering
Electrostatic
Magnetic
MAJ
W
W
MAJ
SB
SB
FAN
FAN
NOT
XV
TFAN
NOT
TFAN
Normalized Ordering
Electrostatic
Magnetic
NOT
MAJ
MAJ
FAN
FAN
NOT
SB
SB
TFAN
TFAN
W
XV
W
TABLE IV
C OMPONENT IMPORTANCE ORDERINGS ( IN DESCENDING ORDER ).
Fig. 8.
Reliability of electrostatic multiplexers with a single perfect
component as listed in legend. Other components have a uniform error rate.
the parity tree circuits are not considered.
Figure 8 shows the circuit reliabilities for the electrostatic
multiplexer circuits with the majority gate and inverter perfect
to satisfy the regression and normalized orderings respectively.
The symbols marking each line and the legend state which of
the two components was kept perfect as the remainder of the
component error rates were uniform and swept across a range
of values. This graph clearly demonstrates that keeping the
majority gate perfect offers a greater increase in reliability than
keeping the inverter perfect. The graphs for the other circuits
show the same trend. These results lead to the conclusion
that the regression ordering is favored over the normalized
ordering. While no regression analysis was done in [9], each
component was made perfect and the resulting reliabilities
were ordered based on which component offered the best
reliability when perfect. The ordering in [9] closely follows
the regression ordering for the circuits used in this work.
VIII. I MPROVING C IRCUIT R ELIABILITY
To guide research into improving circuit reliability determining which component was most critical needed to be
accomplished. Having done this with linear regression, the
potential reliability improvements by making a single component more robust can be quantified. From the results in
Tables II and IV either the majority gate or wire could be
selected as the most critical component. Selecting the wire
over the majority gate as the most critical component is
advantageous since enhancing its reliability is straightforward
and fewer hours of detailed simulation time will be required.
In Fig. 9, the error rate for the wire is stepped across several
orders of magnitude while the error rate for the remaining
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Circuit Size
Circuit Type
Parity Tree
Electrostatic Adders
Electrostatic Muxes
Magnetic Adders
Magnetic Muxes
2 Inputs
8 Inputs
1-Adder
4-Adder
2-Mux
8-Mux
1-Adder
4-Adder
2-Mux
8-Mux
MAJ
-3.11
-15.68
-14.50
-37.71
-6.52
-23.63
-2.63
-9.51
-2.42
-9.99
NOT
-0.73
-4.09
-3.95
-11.89
-1.46
-8.31
-1.20
-4.41
-0.36
-1.33
9
W
-2.63
-13.54
-15.37
-39.44
-5.10
-21.93
-4.46
-15.82
-1.33
-12.01
Components
SB
-2.40
-12.48
-9.06
-25.48
-4.97
-19.41
-1.92
-6.99
-2.64
-9.71
FAN
TFAN
-0.57
-3.20
-3.68
-11.16
-0.91
-6.55
-0.64
-2.37
-7.06
-10.07
-27.86
-3.45
-18.25
-2.63
-9.48
-0.41
-2.93
-0.52
Constant
XV
0.9998
0.9901
0.9909
0.9412
0.9985
0.9324
0.9996
0.9954
0.9999
0.9941
-1.67
-6.11
-0.49
-6.03
TABLE II
S ELECTED L INEAR R EGRESSION R ESULTS
Circuit Size
Circuit Type
2 Inputs
8 Inputs
1-Adder
4-Adder
2-Mux
8-Mux
1-Adder
4-Adder
2-Mux
8-Mux
Parity Tree
Electrostatic Adders
Electrostatic Muxes
Magnetic Adders
Magnetic Muxes
MAJ
-0.77
-0.56
-0.37
-0.24
-0.43
-0.067
-0.88
-0.79
-0.81
-0.37
NOT
-0.73
-0.58
-0.36
-0.27
-0.37
-0.090
-0.60
-0.55
-0.36
-0.17
W
-0.53
-0.39
-0.24
-0.16
-0.28
-0.046
-0.50
-0.44
-0.44
-0.18
Components
SB
-0.60
-0.45
-0.32
-0.23
-0.33
-0.062
-0.48
-0.44
-0.53
-0.28
FAN
-0.50
-0.36
-0.25
-0.35
-0.071
-0.66
-0.59
-0.41
-0.17
TFAN
-0.57
-0.46
-0.28
-0.21
-0.30
-0.078
-0.64
-0.59
-0.21
XV
-0.56
-0.51
-0.49
-0.22
TABLE III
S ELECTED N ORMALIZED L INEAR R EGRESSION R ESULTS
Fig. 9. Reliability of magnetic multiplexers as the wire component error rate
changes as shown in the legend. Other components have a uniform error rate.
components is uniform and swept over a range of values for
the magnetic multiplexer circuits. This figure clearly shows
that an extremely high error rate for the wire causes the circuits
to be nearly useless. As the error rate for the wire is reduced
by two orders of magnitude, the circuit reliability increases
significantly, particularly for the 8-Mux. Further reductions in
the wire error rate offer continued improvements in circuit
reliability. The other circuits show similar trends.
IX. C ONCLUSIONS
We have estimated the reliability of several electrostatic
and magnetic QCA circuits of varying sizes via analytic
modeling. This work has identified expected reliabilities for
these circuits when component error rates are nearly uniform,
and has demonstrated that for these circuits to be highly
reliable (i.e. 99.999%), components need to have error rates
at or below 1×10−7 for electrostatic QCA and at or below
1×10−6 for magnetic QCA. By using linear regression, a
structured method is available for determining which components, generally the majority gates and straight wires, are most
important and should receive the highest consideration for
reliability enhancement. We have also shown how improving
the reliability of a component across orders of magnitude can
influence the overall circuit reliability.
By using an analytic model such as PTMs, we have been
able to save thousands of hours of computation time to identify
similar results and trends. Physical simulation is still necessary
at the component level; however this work offers guidance as
to which component(s) those computational hours should be
directed towards.
Looking forward to implementations in Teramac-like systems, the circuits considered here are likely to be either contained in or approximately the size of a functional logic block.
By estimating their reliability, we can now start to consider
what a Teramac-like system would look like when implemented in QCA. To successfully build a Teramac-like system,
not only should the functional logic blocks be considered,
but the interconnect both inside and between functional logic
blocks must be considered. This work explicitly demonstrates
this because the choice of implementation technology, and thus
type of interconnect, strongly influences circuit reliability.
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Timothy J. Dysart (S’02) received the B.S. in computer engineering and the M.S. in computer science
and engineering from the University of Notre Dame
in 2002 and 2005 respectively. He is currently a
Ph.D. candidate in computer science and engineering
at the University of Notre Dame.
His current research interests are in nanoelectronic
devices and architectures, defect and fault tolerant
design and modeling in nanoelectronic circuits, and
in CAD/EDA for nanoelectronics.
Peter M. Kogge (SM’86-F ’90) received the B.S. in
electrical engineering from the University of Notre
Dame in 1968, the M.S. in systems and engineering
sciences from Syracuse University in 1970 and the
Ph.D. in electrical engineering from Stanford University in 1973.
He was with IBM, Federal Systems Division, from
1968 until 1994 and was named an IBM Fellow in
1993. In 1977, he was a visiting professor at the
University of Massachusetts, Amherst. From 1977
through 1994, he was also an adjunct professor at
State University of New York in Binghamton. He was named the initial
McCourtney chair in Computer Science and Engineering at the University
of Notre Dame in 1994 and holds this position today. For the 20002001 academic year, he was the interim Schubmehl-Prein department chair.
Additionally, he has been the Associate Dean for Research in the College
of Engineering since August 2001 and a concurrent professor of electrical
engineering since August 2003.
His research interests include massively parallel processing architectures,
advanced VLSI technology and architectures - including nanoelectronics, non
von Neumann models of programming and execution, parallel algorithms and
applications, and their impact on computer architecture.