Injection Locking
EECS 242 Lecture 26
Prof. Ali M. Niknejad
Outline
• Injection Locking
- Adler’s Equation (locking range)
- Extension to large signals
• Examples:
- GSM CMOS PA
- Low Power Transmitter
- Dual Mode Oscillators
- Clock distribution
• Quadrature Locked Oscillators
• Injection locked dividers
Ali M. Niknejad
University of California, Berkeley
Slide:
2
Injection Locking
http://www.youtube.com/watch?v=IBgq-_NJCl0
locking is also known as frequency entrainment or
• Injection
synchronization
• Many natural examples including
clocks on the same wall observed to synchronize
- pendulum
over time
- fireflies put on a good light show
• Injection locking can be deliberate or unwanted
Ali M. Niknejad
University of California, Berkeley
Slide:
3
Injection Locking Video Demonstration
http://www.youtube.com/watch?v=W1TMZASCR-I
metronomes (similar to pendulums) are initially excited
• Several
in random phases. The oscillation frequencies are presumably
•
•
Ali M. Niknejad
very close but vary slightly due to manufacturing imperfections
When placed on a rigid surface, the metronomes oscillate
independently.
When placed on flexible table with “springs” (coke cans), they
couple to one another and injection lock.
University of California, Berkeley
Slide:
4
A Study of Injection Locking and Pulling
Unwanted Injection
Pulling/Locking
in Oscillators
Behzad Razavi, Fellow, IEEE
of the difficulties in designing a
• One
fully integrated transceiver is
•
•
•
Abstract—Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection
pulling in time and frequency domains. An identity obtained from
phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators under injection pulling is also
formulated.
exactly due to pulling / pushing
If the injection signal is strong
Index
Terms—Adler’s
equation,
injection locking, injection
enough,
it
will
lock
the
source.
pulling, oscillator nonlinearity, oscillator pulling, quadrature
oscillators.it will “pull” the source
Otherwise
and produce
unwanted
modulation
NJECTION of a periodic signal into an oscillator leads
to interesting
locking orthe
pullingtransmitter
phenomena. Studied by
In the I
first
example,
Adler [1], Kurokawa [2], and others [3]–[5], these effects have
is locked
a XTAL
whereas
found to
increasingly
greater importance
for theythe
manifest themselvesisin locked
many of today’s
transceivers
and frequency
synthesis
receiver
to
the
data
clock.
techniques.
Unwanted
coupling
This paper
describes new(package,
insights into injection locking and
pulling Vdd/Gnd)
and formulates the behavior
of phase-locked oscillators
substrate,
can
cause
under injection. A graphical interpretation of Adler’s equation
pulling.illustrates pulling in both time and frequency domains while
derived from the phase and envelope equations
A PA isanexpresses
aidentity
classic
source
of trouble
the required
oscillator nonlinearity
across the lock
range.
in a direct-conversion
transmitter
Section II of the paper places this work in context and
Section III deals with injection locking. Sections IV and V
respectively consider injection pulling and the required oscillator nonlinearity. Section VI quantifies the effect of pulling
on phase-locked loops (PLLs) and Section VII summarizes the
experimental results.
Ali M. Niknejad
Fig. 1.
Source: [Razavi]
Oscillator pulling in (a) broadband transceiver and (b) RF transceiver.
Injection locking becomes useful in a number of applications, including frequency division [8], [9], quadrature generation [10], [11], and oscillators with finer phase separations [12].
Injection pulling, on the other hand, typically proves undesirable. For example, in the broadband transceiver of Fig. 1(a),
, is lockedSlide:
to
University of California, Berkeley the transmit voltage-controlled oscillator,
5
I. GENERAL CONSIDERATIONS
Injection Locking is Non-Linear
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• For weak injection, you get a response at both side-bands
• As the injection is increased, it begins to “pull” the oscillator
for large enough injection, the oscillation locks to the
• Eventually,
injection signal
University of California, Berkeley
Slide:
6
Injection Locking in LC Tanks
1416
IE
(a) a free-running
• Consider
oscillator consisting of an ideal
•
positive feedback amplifier and
an LC tank.
Now suppose (b) we insert a
phase shift in the loop. We
know this will cause the
oscillation frequency to (c)
shift since the loop gain has to
have exactly 2π phase shift
(or multiples)
Gm ZT (ω0 ) = gm R = 1
Gm ejφ0 ZT (ω1 ) = 1
Gm ejφ0 |ZT (ω1 )|e−jφ0 = 1
∠ZT (ω1 ) = −φ0
Ali M. Niknejad
Fig
Source:
Fig. 2. (a) Conceptual oscillator. (b)
Frequency[Razavi]
shift due to additional phase
shift. (c) Open-loop characteristics. (d) Frequency shift by injection.
wh
shift), and the ideal inverting buffer follows the tank to create a
total phase shift of 360 around the feedback loop. What hap- if
University of California,
pens if Berkeley
an additional phase shift is inserted in the loop, e.g.,Slide:
as 7
Injection Locking in LC Tanks [cont]
phase shift in the tank will cause the oscillation frequency to
• Achange
in order to compensate for the phase shift through the
•
•
•
tank impedance.
The oscillation frequency is no longer at the resonant
frequency of the tank. Note that the oscillation amplitude
must also change since the loop gain is now different (tank
impedance is lower)
Maximum phase shift that the tank can provide is ± 90°
In a high Q tank, the frequency shift is relatively small since
1.5
1
ω0 dφ
Q=
2 dω
0.5
0
ω0 ∆φ
∆ω ≈
2 Q
-0.5
-1
-1.5
8
9.25 · 10
Ali M. Niknejad
8
9.5 · 10
University of California, Berkeley
8
9.75 · 10
9
1 · 10
9
1.025 · 10
9
1.05 · 10
9
1.075 · 10
9
1.1 · 10
Slide:
8
Phase Shift for Injected Signal
interesting to observe that if a signal is
• It’s
injected into the circuit, then the tank current is
•
•
•
•
Ali M. Niknejad
a sum of the injected and transistor current.
Assume the oscillator “locks” onto the injected
current and oscillates at the same frequency.
Since the locking signal is not in general at the
resonant center frequency, the tank introduces
Source: [Razavi]
a phase shift
Fig. 2. (a) Conceptual oscillator. (b) Frequency shift due to additional phase
shift. (c) Open-loop characteristics. (d) Frequency shift by injection.
In order for the oscillator loop
gain to be equal
to unity with zero phase shift, the sum of the
shift),
andinjected
the ideal inverting buffer follows the tank to create a
current of the transistor and
the
total phase shift of 360 around the feedback loop. What hapcurrents must have the proper
phase shift to
pens if an additional phase shift is inserted in the loop, e.g., as
compensate for the tank phase
shift.
depicted
in Fig. 2(b)? The circuit can no longer oscillate at
because the total
phase shift at this frequency deviates from 360
We see that the oscillator current,
tank
by all. Thus,
as different
illustrated in Fig. 2(c), the oscillation frequency
current, and injected current
have
such that the tank contributes
must change to a new value
phases
enough phase shift to cancel the effect of . Note that, if the
Fig
wh
if
De
be
en
contribute no phase shift, then the drain current m
buffer and
must remain in phase with
under all condi- re
of
tions.
University of California, Berkeley
Slide: 9tan
by adding a sinuNow suppose we attempt to produce
Injection Locked Oscillator Phasors
0
Itank
Vtank = Itank ZT (!1 )
Itank = Iosc + Iinj
Itank
j
Iosc e
Iosc
0
Iinj
6
Iosc = 6 Vtank = 6 Itank + 0
Iinj
that the frequency of the injection signal determines the
• Note
extra phase shift Φ of the tank. This is fixed by the frequency
0
•
•
Ali M. Niknejad
offset.
The current from the transistor is fed by the tank voltage, which by
definition the tank current times the tank impedance, which
introduces Φ0 between the tank current/voltage.
The angle between the injected current and the oscillator current
θ must be such that their sum aligns with the tank current.
University of California, Berkeley
Slide:
10
Injection Geometry
sin φ0 =
B
A
B
Itank
Itank
B
cos(π/2 − θ) = sin(θ) =
Iinj
Iosc
Iinj
sin φ0 =
sin(θ)
Itank
Iinj sin(θ)
Iinj sin(θ)
!
sin φ0 =
=
jθ
|Iosc e + Iinj |
2 + I 2 + 2 cos θI
Iosc
osc Iinj
inj
0
Iinj
geometry of the problem implies the following constraints
• The
on the injected current amplitude relative to the oscillation
•
amplitude.
The maximum value of the rhs occurs at:
−Iinj
cos θ =
Iosc
Ali M. Niknejad
sin θ =
!
2 − I2
Iosc
inj
Iosc
University of California, Berkeley
sin φ0,max
Iinj
=
Iosc
Slide:
11
Locking Range
the edge of the lock range, the injected
• At
current is orthogonal to the tank current.
phase angle between the injected current
• The
and the oscillator is 90° + Φ
lock range can be computed by noting that
• The
the tank phase shift is given by
Itank
0,max
2Q
tan φ0 =
(ω0 − ωinj )
ω0
Iosc
2Q
Iinj
Iinj
tan φ0 =
(ω0 − ωinj ) =
=!
ω0
Itank
2 − I2
Iosc
inj
ω0 Iinj
1
!
(ω0 − ωinj ) =
2Q Iosc
1−
Ali M. Niknejad
2
Iinj
2
Iosc
0
Maximum Locking Range
Iinj
University of California, Berkeley
Slide:
12
Weak Injection Locking Range
first derived these results in a celebrate paper [Adler]
• Adler
under the conditions of a weak injection signal.
results for a large injection signal were first derived by
• The
[Paciorek] and then re-derived (as shown here) by [Razavi]
• Under weak injection: I ! I
inj
osc
Iinj
sin φ0 ≈
sin(θ)
Iosc
Iinj
2Q
sin φ0 =
sin(θ) ≈ tan φ0 =
(ω0 − ωinj )
Itank
ω0
2Q Itank
sin(θ) =
(ω0 − ωinj )
ω0 Iinj
the edge of the locking range, the angle reaches 90°, and the
• At
injected signal is occurring at the peaks of the output, which
cannot produce locking (think back to the Hajimiri phase noise
model)
ω0 Iinj
(ω0 − ωinj ) =
2Q Itank
Ali M. Niknejad
University of California, Berkeley
Slide:
13
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004
Injection Pulling Dynamics
, and
(15)
Source: [Razavi]
ains phase modula- Fig. 6. LC oscillator under injection.
now that the oscillator is under injection
phase shift can Suppose
be
oscillator signal feeding the tank can be written as
antaneous input freEquating this result to
, we obtain
•
so that
VX = Vinj,p cos ωinj t + Vosc,p cos(ωinj t + θ)
VX = (Vinj,p + Vosc,p cos θ) cos ωinj t − Vosc,p sin θ sin ωinj t
(16)
(23)
This We
canalso
benote
written
as athat
cosine with a phase shift
•
from
(19)
slowly-varying ),
ection phenomena. V = Vinj,p + Vosc,p cos θ cos(ω t + ψ)
X
inj
cos ψ
• Which allows us to write! the output as
Vosc,p sin θ
tan ψ =
Vinj,p + Vosc,p cos θ
"
!
#$#
m shown in Fig. 6,
(24)
Vinj,p + Vosc,p cos θ
dψ
−1 2Q
e input. The output
Vout =
cos ωinj t + ψ + tan
ω0 − ωinj −
cos ψ
ω0
dt
having a carrier fre(25)
words, the output is
Ali M. Niknejad
University of California, Berkeley
sibly
time-varying)
Slide:
14
Injection Pulling Dynamics [cont]
have assumed that the phase shift through the tank is given
• We
by the simple expression derived earlier where the
instantaneous frequency is
dψ
ω+
dt
!
"
2Q
dψ
tan α ≈
ω0 − ω −
ω0
dt
• Ifto:the injection signal is weak, then the previous result simplifies
!
Vout = Vosc,p cos ωinj t + ψ + tan
−1
"
2Q
ω0
!
ω0 − ωinj
dψ
−
dt
#$#
must equal to the output voltage, or the phase shifts
• Which
must equal
ψ + tan
−1
Ali M. Niknejad
!
2Q
ω0
"
ω0 − ωinj
dψ
−
dt
University of California, Berkeley
#$
=θ
Slide:
15
Pulling [cont]
• These equations can be manipulated into a form of Adler’s equation:
dθ
ω0 Vinj,p
= ω0 − ωinj −
sin θ
dt
2Q Vosc,p
dθ
= ω0 − ωinj − ωL sin θ
dt
ω0 Vinj,p
ωL !
2Q Vosc,p
equation describes the dynamics of the phase change of the
• This
oscillator under injecting pulling. If we set the derivative to zero,
•
•
we obtain the injection locking conditions (same as before).
Notice that maximum value of the rhs is quite small, which means
that the rate of change of phase is
This equation can be used to study the behavior of locking signals
outside the lock range. Note that this equation agrees with our
graphical analysis:
dθ
=0
dt
Ali M. Niknejad
University of California, Berkeley
Slide:
16
Pull-In Process
θ(t) = 2 tan
−1
!
1
− cot θ0 tanh
sin θ0
θ0 = sin
−1
"
#$
ωL cos θ0
(t − t0 )
2
ω0 − ω1
ωL
the steady-state phase shift between the injected signal
• θand0 isthe
active device signal and t is an integration constant that
0
•
depends on the initial phase shift.
From this equation the lock-in time can be computed (it’s
approximately an exponential process):
!
2
−1 1 − sin θ0 tan
tL =
tanh
ωL cos θ0
cos θ0
Ali M. Niknejad
University of California, Berkeley
"θ #$
L
2
+ t0
Slide:
17
Phase Noise in Injection Locked Systems
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004
input frequency deviates
uction becomes less proeither edge of the lock
g the impedance seen by
o rely on the phase noise
g. Since the lock range is
atural frequency of oscilocess variations and poor
noise due [Razavi]
to injection locking.
he edge of the lock range, Fig. 14. Reduction of phaseSource:
slightly. For example, if
Under
% and the natural
fre- a lock, the phase of the oscillator follows the phase of
the
% with process and
tem-injection signal. If a “clean” signal is used to lock a VCO,
thenat the phase noise would improve up to the locking range.
njection locking occurs
37) and the above obserAt the edge of the lock, the injected signal cannot correct for
e noise falls from infinity
the phase noise since it injects energy at a 90° phase offset,
degradation in the phase
where the signal has a peak amplitude
.
•
•
LOCKED OSCILLATORS
with
pulling in nominally
Ali M. Niknejad
Fig. 15. PLL under injection pulling.
University of California, Berkeley
Slide:
18
Fig. 8. Microstrip balun.
Example: GSM Class E PA
964
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO
Fig. 10. Output power and PAE versus frequency for
Fig. 9. Output power, efficiency, and PAE versus supply voltage.
10 and 5 mil, respectively. A single-ended signal at port 1
can be converted to differential signals at ports 2 and 3 or
vice versa. The edge-coupled microstrip lines and the discrete
tuning capacitors are shown in the enlarged portion of Fig. 8.
and
V.
Fig. 5. Illustration of the mode-locking concept.
B. Mode-Locking Technique
Fig. 11. Amplified GMSK modulated signal (
spectral emission
Modemask.
locking refers to the
) and the GSM
Source: [Tsai]condition in which an
self-oscillating circuit is coupled and forced to
of the same
PAE infrequency
this regionasis an
dueinput
to thesignal,
progressively
morein a
resulting
VI. MEASUREMENT RESULTS
prominent
input power
in driving
the PAE requirement.
definition. At This
2-V is
reduction
in theterm
input
supply, the PAE was measured to be 48%.
Fig. A.
4. Power-Amplifier
Schematic of thePrototype
complete power amplifier.
each stage of the amplifier by a pair of cross-coupl
Fig. 10 shows the output power and PAE at two different
devices,
as
shown
in Fig.
The twowhere
input the
volta
Large single-ended
output stage
is hard
to drive
capacitance).
voltages(large
across
the
range
of 5.
frequencies
A 10-dBm
input device
was converted
to supply
of is
phase,
are the
two output
The isload
mode as
locked
successfully.
Thisvoltages.
locking range
differential signals, using a commercial balun (Murata amplifier
Useequivalent
the and
PAoutput
toapplied
drive
an oscillator,
right?
a
at the
nodes
isYes.
designed
suchGHz.
that
measured
to beoutput
490 MHz,
centering
at about 1.9
LDB20C500A1900),
then
to itself!
the
PA. capacitors
RFThat’s
power and
inductors
and
load, and
larger
verify
its potential
in practical
communication
output ports.
Fig.
9 maximized
shows a
was measured
at the
50- transistors
in phase
to control
the composite
switch.applicaAs far a
switches.
In
fact,injection
the
switch
areto
often
inTo modulation.
Use
locking
inject
phase
Need
“off”
mode-locking
class-Ethe
PAoperation
was tested is
with
a Gaussian
, measured at tions, the
typical plot of the output power versus
circuit
is concerned,
similar
to the si
size to reduce
the
on-resistance
loss.
The
input
capacitance
of
switch
to power
turnincreases
off transmission.
1.98 GHz.
The output
from 49 mW to 1.0 minimum shift keying (GMSK) [21] modulated input signal.
version as shown in Fig. 1, except for two feat
these
is asusually
tuned
out by
inductors.
W transistors
monotonically
the supply
is swept
from
0.6 to 2 VHowever,
and GMSK and its close relative, Gaussian frequency shift keying
thearecurrent
circulating
at each
tuned lo
at gigahertz
frequencies,
beyond
transistor size the
(GFSK),
constantoriginally
envelope modulation
schemes
in which
. The maximum
is approximately
proportional
to a certain
to assist
switching
of the other
circu
is carried
in the
phase variation
of the half
signal,
used in this
caserequired
is determined
by the
peak
drain too
voltage
inductance
values
for tuning
may
become
smallinformation
to utilized
capacitance
input can
now
be significan
makingthe
them
well suitedattoeach
switching
power
amplification.
on chip, which
estimatedthe
to be
slightly
above 5 V capacitance
at 2-VBerkeley
be realizable.
In is
addition,
large
gate-to-drain
Ali M. Niknejad
University of California,
Slide: 19
•
•
•
supply, approaching the drain-gate oxide breakdown limit of
These modulation schemes are used by popular cellular and
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a low-power radio, the overall transmitter efficiency is very
• Inimportant.
The PA output power is modest (~1mW), but since
!
$%&'!('?@!/574/!-50!/%6&80!/%>0>!871=A%6!296&0! !B!9/!9!;,61-%76!7;!-50!C%9/!1,2206-!7;!-50!
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the overall efficiency should be large, the entire transmitter
-5%/!98/7!%61209/0/!-50!.7402!176/,3.-%76!7;!-296/%/-72!E
!96>!E !45%15!>0&29>0/!-50!
should not consume
more than 2-3mW.
!
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By using injection locking one can reduce the power
157/06!-7!C0!N"!EIM!96>!-50!.09=!0;;%1%061K!%/!20>,10>!CK!768K!CK!N?O'!
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consumption of the driver stages and end up with a minimal
-A.%,,18-2!A94472A!42-3!1!C--2!C@1A7!:-%A7!C724-231:.7!1:0!1:!%3C27.%A7!
transmitter architecture.
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-2'!!!!!
Ali M. Niknejad
%#
%F
%!
University of California, Berkeley
%'
Slide:
20
Consider
interconnection
of two
from
the
locked
half
mode
4.8GHz
reference.
the locked
half the
mode
4.8GHz
reference.
A A/0 tanks as
conventional
mode
VCO
fabricated
as
hown
in
Fig.single
1. Each
tank
isisa also
parallel
/0ascircuit,
butFig.1
they
ntional
single
mode
VCO
is also
fabricated
Fig.1
Capacitive-coupledparallel
parallel/0
/0tank
tank
Capacitive-coupled
reference
to show
the power
saving
advantage
of the
nce
to show
the
power
saving
advantage
of the
re
coupled
together
through
a
coupling
capacitor 01. By
structure.
The most important feature for this coupled /0 tank
ure.
Example: Dual Mode VCO
The most important feature for this coupled /0 tank
arying the value of coupling capacitor, differentis dynamic
that
it inherently
has
two
resonantfrequencies.
frequencies.AAsimple
simple
is
that
it
inherently
has
two
resonant
Index
Term
–
Coupled
LC
tank,
dual-mode,
henomenon
be observed.
calculation yields the following expression for the two
ndex
Term – can
Coupled
LC tank, dual-mode,
calculation yields the following expression for the two
resonant frequencies
e-controlled oscillator, injection locking.
resonant frequencies
22 % !
22 " !
I. INTRODUCTION
Eq. 1
2
"
!
2
$
$
#
#
2 % !
2
/
3
I. INTRODUCTION
Eq. 1
$/ #
$3 #
22 3
22 3
22 3
22 3
Generation of a low phase noise spectrally pure tone where
Generation
of a low
phase noise
spectrally pure
tone where
2
has been a major
challenge
for communication
circuits
2
+ 03 03 01 022(
0
3
Eq. 2a
en
a majorinchallenge
for communication
!+#0)) 0" 0
" 0
% ( && % 40 2
fabricated
CMOS technology.
The lack circuits
of a high Q
Eq. 2a
! # )) *3 /"1 3 /"2 1 /%2 2/&&1 '% 4 /31/2
ated
in resonator
CMOS technology.
of consumption
a high Q
stable
necessitates The
high lack
power
in
* /1 0 3/2 0 3/2 01/1 '0 2 /1/2
resonator
highloop
power
consumption
in As
the form ofnecessitates
a phase-locked
frequency
synthesizer.
Eq. 2b
22 #
%
%
%
0
0
0
0
m of
a phase-locked
loop frequency
synthesizer.
As
Eq. 2b
we
move
to higher frequencies,
the problem
is exacerbated
2 2 # 3 /%1 3 /%2 1/%2 2/1
Capacitive-coupled
parallel
/0 tank
ve totohigher
frequencies,
problem is of
exacerbated
due
theFig.1
increasing
powerthe
consumption
the prescalar
Eq. 2c
23 /
#10301/%2 030/22 % 01/01 2
frequency
dividers
in the
frequency synthesizer.
Since
the increasing
power
consumption
of the prescalar
Eq. 2c
2 3 shows
# 0301 the
% 0differential
Fig.2
302 % 0102 dual-mode /0 tank used
digital
logicmost
isinoften
employed synthesizer.
tofeature
perform for
thisSince
task,
ncy
dividers
theimportant
frequency
The
thisthe
coupledinFig.2
/0
tank
this design.
/0 tank coredual-mode
is simply the
shows The
the differential
/0 differential
tank used
power
consumption
increases
as
we
operate
at
a
closer
logic is often employed to perform this task, the
version
of Fig.
values
carefully
in this
design.
The 1.
/0The
tankcomponents
core is simply
theare
differential
sfraction
that
it
inherently
has
two
resonant
frequencies.
A
simple
of
the
process
.
.
Injection
locked
dividers
consumption increasesT as we operate at a closer
calculated
and1.selected
for desired resonant
/1
version
of two
Fig.
The components
values frequencies.
are carefully
alculation
yields
the
following
expression
for
the
consume
less
power,
but
have
narrow
locking
range
and
n of the process .T. Injection locked dividers
and /2 and
areselected
on chipforspiral
inductors.
center tap
calculated
desired
resonant The
frequencies.
/1
require
an
additional
oscillator.
me
less power,
but have narrow locking range and
esonant
frequencies
connection
of
the
two
inductors
is
used
as
the
dc
current
and /2 are on chip spiral inductors. The center tap
While multimode
oscillator have been proposed
e an additional
oscillator.
path which
allows
the
active circuits
presented
at current
the two
connection
of
the
two
inductors
is
used
as
the
dc
(a)
before
[1]
[2],
in
this
paper
we
present
a
coupled
/0
2 2 % ! ports to
2 2 " !have been proposed
While multimode oscillator
share
the
same
dc
current.
By
terminating
each
Eq.allows
1 the active circuits presented at the two
path which
oscillator
with
dual frequency outputs
that
naturally
$
$
#
#
/
3
port with a negative resistance, generated for example by a
[1] [2], in this paper we present a coupled /0
ports
to share the same dc current. By terminating each
22
provides a technique 22
for combining
the
VCO
and
a
3
3
cross-coupled active device, both oscillation modes can be
tor with dual frequency outputs
that naturally
frequency divider in a phase-locked loop. Typically, we port with a negative resistance, generated for example by a
es
technique
for combining
the VCO
andlower
a mode to activated at the same time. This is the basic idea behind the
where
useathe
higher mode
to drive a mixer
and the
cross-coupled
active device, both oscillation modes can be
dual-mode oscillator.
ncy
divider
in
a
phase-locked
loop.
Typically,
we
2
2
drive the PLL dividers.
activatedThe
at the
same /0
time.
This iscan
thealso
basic
idea phase
behindnoise
the
+
(
coupled
network
benefit
0
0
0
0
0
e higher mode to drive
mode
to
3 a mixer
3 and1 the lower
2
3
Eq.oscillator.
2a
dual-mode
! # )) " " % && % 4
performance.
Analytical analysis shows that this higher
he II.
PLL
dividers.
/
/
/
/
/
/
DUAL-MODE
LOCK
The resonant
coupled /0
network
also benefit
phase noise
1 '
1 2
* 1VCO2WITH2 INJECTION
order
network
can can
enhance
the equivalent
tank
performance.
Analytical
shows
that this
higher
DESIGN
quality factor
thereby analysis
improving
the phase
noise.
An
0
0
0
0
3
3
Eq.
2b
1
2
DUAL-MODE
VCO
WITH
I
NJECTION
L
OCK
order
resonant
can enhance
equivalent
tanka
22 #
%
%
%
intuitive
waynetwork
of understanding
thisthe
approach
is that
/ESIGN
/ 2 /of2 Electrical
/1 Engineeringquality
The authors are withDthe
factor
thereby
improving
phase noise.
An (b)
1 Department
“zero”
is designed
at the
vicinity of the
the resonant
frequency,
Fig.
2 roll-off
(a) Differential
dual-mode !" tank (b)
and Computer Science, University of California at Berkeley,intuitive
way
of
understanding
this
approach
is
that
a
shown
in
Fig.
2(b),
so
that
it
increases
the
rate
from
Eq. 2c
2the
0301Email:
% 0of
Berkeley,
CA
94720
USA.
dengzm@eecs.berkeley.edu
impedance over frequency
3 #Department
30
2 % 0102Engineering
thors
are
with
Electrical
the
peak
resulting
in avicinity
sharper of
transition
and a frequency,
narrower
“zero”
is
designed
at the
the resonant
Ali M. Niknejad
University of California,
Berkeley
Slide: 21
voltage-controlled oscillator, injection locking.
coupled tank has two resonant modes.
• AFrom
each port of the oscillator, one mode is
•
•
dominant.
In a fully differential version shown to the
right, the impedance variation with frequency
is shown.
Can we build an oscillator that sustains both
modes?
omputer Science, University of California at Berkeley,
Dual Mode VCO (cont)
Source: [Deng]
cross-coupled pairs are used to sustain each mode by
• Two
providing sufficient negative resistance. The PMOS side is
•
Ali M. Niknejad
running at a lower frequency whereas the NMOS side runs at
the higher frequency.
Transistors M3a/M3b are used for injection locking.
University of California, Berkeley
Slide:
22
Dual Mode VCO Spectrum
•
•
Ali M. Niknejad
•
Without injection locking, each mode runs independently. The
frequencies are not integrally related, so the unlocked spectrum contains
not only the two modes and harmonics, but also every intermodulation
component.
When the modes are locked, the intermodulation components
disappear. The high frequency VCO is divided by two in this
configuration.
More on injection locking dividers to come...
University of California, Berkeley
Slide:
23
ter 2: Overview of Electrical Clock Distribution
14
Clock Distribution
Chapter 2: Overview of Electrical Clock Distribution
16
PLL
Figure 2.7:
igure 2.6:
A buffered H-tree.
A clock grid driven by buffers.
Source: [Mahony]
2.3.1.3
Local
distribution is completely symmetric to simplify the
design
and provide nominally
• source of power consumption. Figures of merit include skew,
The final
level topology
of
distribution
network is the local
which is the portion o
a clock
in acommonly
large
chip
isa clock
a major
challenge
andlevel,
a big
kew (assuming no Delivering
loading variations).
The most
used
is a buff-
the network that follows the clock pin. This network drives the final loads of the clock dis
H-tree [7] which is shown in Figure 2.6. H-trees are an extremely popular choice at
tribution and hence consumes the most power. As a rule of thumb, the power at the loca
jitter, and power.
evel of the clock distribution because they are a simple
pattern that efficiently and
level is about one order of magnitude larger than the power in the global and regional lev
A buffered H-tree or a grid are common approaches. The grid
metrically covers large areas. H-trees minimize the els
distance
fromwith
thethe
PLL
to notable
the fur-exceptions being clock networks that use a
combined,
only
has skew and larger capacitance.
•
low-impedance
grid atthe
theinterconnect
regional level [2].
clock pins (without using diagonal traces) and thereby
minimize
The layout
of the local
is generally included in the design of the macro block and
cy. The number of buffer levels within the global network
− which
alsogrid
determines
is not the responsibility of global and regional clock network designer. Because of its rela
tency − depends on the signal dispersion, loss and on the required power fanout.
Ali M. Niknejad
tively limited span, it is sufficient to use automatic layout for this portion of the clock
University of California, Berkeley
Slide:
24
ould be expected based on the delay between points on the clock network. Despite
vantages, however, an analysis of the relationship between skew and interconnect
Clock Distribution: Distributed
ndicates that wire loss will limit the use of standing-waves in an on-chip, global
distribution. This type of clock distribution also requires
limiting amplifiers to con2.5: Directions in global clock distribution
27
he sinusoidal standing waves to digital levels, which could add additional skew and
2.5: Directions in global clock distribution
l << λ
2
VCO and loop filter
Phase detector
Regional
Clock
Distribution
÷N
Clock load
gure 2.12:
Standing-wave clock distribution [41].
Figure 2.13:
Clock distribution using a coupled array of PLLs [44].System Clk
PD, LPF & CP
Source: [Mahony]
Vc
(to VCOs)
algorithm is used to avoid instability during the phase locking process. There are two main
advantages to this topology. First, the PLLs filter the noise of the global H-tree and
Coupled oscillator arrays
replace it with the noise of the local VCOs, thereby reducing the jitter that accumulates in
wave oscillators tune out the
• Standing
capacitance of the line and form a resonant
VCO
Coupling
wires
the H-tree. The second advantage is that, like in [44], the skew is a function of the error in
he research that has been described to this point generally concentrates on minimiz-
the phase detectors rather than the accumulated skew between branches of the H-tree. This
e skew of a global clock distribution. However, based on the scaling analysis in
means that the scaling of this type of distribution does not depend on the latency of the
Figure 2.15: Clock distribution using a coupled array of VCOs [48].
H-tree but rather on the scaling of the VCO and phase detector. The presence of the global
on 2.4, it appears that jitter may be more difficult to reduce for future high-perfor-
network.
been proposed that have the potential to reduce both jitter and skew by eliminating
A distributed approach locks an array of
amounts of latency from the clock network. Some also reduce skew and jitter by
totheit’s
ying a phase-averaging effectVCO’s
that tends to reduce
impactneighbors.
of uncorrelated static
The neighbors can also be injection locked
to one another to eliminate the phase
detectors.
e microprocessors. Several clock distributions based
on coupled oscillator arrays
H-tree also allows for low-frequency testing by bypassing the PLLs. The only drawbacks
•
•
Ali M. Niknejad
Coupled
distributed oscillators
to this approach are the additional resources necessary for multiple2.5.3.3
PLLs and
the com-
plexity of synchronization. This approach has not yet been prototyped so no measured
The last type of coupled-oscillator clock distributions uses coupled arrays of distrib
data is available.
uted oscillators. The oscillators are distributed in the sense that the coupling wires are pa
2.5.3.2
of the oscillators themselves, so their free-running frequency depends to some degree o
VCO arrays
the geometry of the interconnects. The cooperative ring oscillator (CRO) clock distribu
The global clock distributions described in [47] and [48] are similar to the PLL array
tion described in [49] uses overlapping ring oscillators. The frequency of the oscillato
designs, except that they use a single control loop with multiple VCOs. The clock distribudepends on both the buffer and interconnect delays around the ring. Figure 2.16 shows
tion shown in Figure 2.15 and described in detail here is based on [48], but the same basic
three-phase CRO grid and its electrical equivalent. The oscillators are allowed to run ope
concepts are used in [47]. A control voltage is distributed to all of the VCOs around the
loop, and they phase lock to each other due to mutual coupling between rings, similar
die to set their frequency. A clock signal is fed back from a regional clock tap (driven by a
[47] and [48].
University of California, Berkeley
A similar approach is proposed in [50], which implements coupled arrays
rotar
Slide: of25
of the“keep-out”
PMOS andregions, areas where the signal amplitude is too low to be tapped b
the line, so they are optimized for maximum gd/cd. The relative sizes ered
Thetovoltage
standing-wave pattern for a portion of the grid is shown in Figu
NMOS devices can also be optimized, but a good rule of thumb is tobuffers.
size them
be
Standing Wave Oscillators (SWO)
roughly equal.
Note that the largest magnitude occurs around the square portion of the grid and t
nodes of the standing-wave are pushed onto the stubs.
4.2.3 Design example
Single SWO (folded)
63µm:0.18 µm
Clkinj
Differential interconnect
Cross-coupled pair
Injection-locked
cross-coupled pair
Clock buffer
63µm:0.18 µm
14µm
14µm
Chapter 5: Standing-Wave Clock Distribution Network
3.5mA
3.5µm
4µm
Figure 5.3:
5.1.1 SWO coupling
A resonant
clock grid of coupled SWOs.
Figure 4.8: SWO and transmission line cross-section for design example.
ccp
ccpof theccp
ccp
ccp
This clock grid of coupled oscillators
solves
two
fundamental
problem
negative resistance to sustain
• The
oscillation is distributed along the line.
disadvantage is that the amplitude of
• One
the clock varies along the line.
can be injection locked together
• SWO’s
to form larger clock trees.
accumulation of timing uncertainty and sensitivity to buffer delay. A
A SWO is straightforward to design from (4.11) and (4.2). Table 4.1H-trees:
lists the the
parame-
in spaced
Chapter 2, H-trees accumulate timing uncertainty because the clock si
ters that will be used to design a SWO with five equally sized andcussed
equally
cross-coupled pairs. The transmission-line cross-section (Figure 4.8) is optimized
generatedfor
bymina single source and then regenerated
by
each ccp
buffer along
the tree. I
ccp
ccp
ccp
ccp
the ground
imum loss given a total track width of 32µm and a distance of 3.5µm totrast,
each plane.
SWO in the grid locally generates the clock signal and only uses the
A unit cross-coupled pair (ccp) is defined to have NMOS and PMOS devices that are
18µm wide and 0.18µm long and is optimized for maximum gd/cd with 1.0mA of bias cur-
Figure 5.1: Two coupled SWOs.
Source: [Mahony]
Multiple SWOs can be coupled together by simply connecting their transmission li
Two coupled SWOs are shown in Figure 5.1. Ideally, the two oscillators are matche
frequency and a transient current between the two oscillators brings them into per
phase lock. If the oscillators are detuned, they will still lock if they are within their mu
Ali M. Niknejad
University of California, Berkeley
locking range. A steady-state coupling current will keep them frequencySlide:
locked,26
altho
ROUFOUGARAN et al.: SINGLE-CHIP 900-MHz SPREAD-SPECTRUM WIRELESS TRANSCEIVER IN
Quadrature Locked VCOs (QVCO)
270°
90°
0°
180°
0°
180°
Fig. 20. (a) Q
showing the re
across the reso
Source: [Rofoug]
Fig.
19.VCO’s
Quadrature
oscillator comprises
a pair
of cross-coupled
LC oscil-as
Two
are coupled
together
using
extra transistors
•lators
synchronized
in frequency. are identical, we expect that the
shown.
If the oscillators
amplitude and frequency of oscillation should be identical.
Becausebalanced
of the phase
of the outputs
coupling,
can be shown
that they
recently,
quadrature
areit obtained
from two
lock in quadrature...
•
Ali M. Niknejad
cross-coupled relaxation oscillators [30]. Another oscillator
consists of two LC biquad
inBerkeley
feedback [31]. Four-stage
Universityfilters
of California,
Slide:
27
UM WIRELESS TRANSCEIVER IN 1- m CMOS—PART I
QVCO: Quadrature Lock
525
Source: [Rofoug]
that the tank “A” (a)
is driven by the tank voltage VA plus
(b)
• Note
the tank voltage of “B”.
Fig. 20. (a) Quadrature oscillator redrawn, emphasizing its symmetry and
rightthe
tank,
though,
is driven
by the
voltage
V phases
but voltage
-V .
• The
showing
resonator
currents;
and (b)
relative
of the voltages
across the resonators
required
forand
symmetric
operation.
that the LC
tanks
FETs are
identical, then the
• Assuming
phasor currents flowing into the tanks must have equal
B
pled LC oscil-
magnitude:
A
|vA + vB | = | − vA + VB |
|1 + ejθ | = |1 − ejθ |
d from two
Ali M. Niknejad
cos θ = 0 → θ = ±90◦
University of California, Berkeley
Slide:
28
(a)
(b)
QVCO: Lead/Lag Ambiguity
Fig. 20. (a) Quadrature oscillator redrawn, emphasizing its symmetry and
showing the resonator currents; and (b) the relative phases of the voltages
across the resonators required for symmetric operation.
r of cross-coupled LC oscil-
are obtained from two
30]. Another oscillator
edback [31]. Four-stage
at taps two stages apart
lthough apparently not
ite low phase noise in
ture oscillator. It comSource: [Rofoug]
d above, labeled A and
ted in parallel with the
Oscillator A is direct21. Magnitude
and phase
of a realistic resonator’s impedance,
show- relation, or the
NoteFig.that
the tank
current/voltage
has a 90°
llator B, and the output ing three possible oscillation frequencies. The oscillator selects the highest
of the
impedance
Three frequencies satisfy this
because
the feedback loop is
gain±45°.
is largest here.
Oscillator A (Fig. phase
19). frequency
constraint, but f3 has the highest loop gain.
ctly the same frequency
y the coupling topology. circuit impedance is
andpossible
its phase is solutions:
either 45
It’s
clear
that
there
are
two
lead or lag in
plains how, owing only or 45 (Fig. 20). In an LC resonator with series loss in the
phaseinductor,
between
“A” and “B”.
n quadrature.
these phases appear at three different frequencies, ,
ctively, are the steady, real
and oscillator,
(Fig. 21). However,
amongoscillators
them only
is are
stable,not perfectly
In
any
the
two
with reference polarities because at this frequency the impedance is largest, and thus the
symmetric, and it can be shown that there is only one unique
rrent into the tuned load
the phase
feedback factor in the oscillator is strongest. At
solution
(where
the
loop
gain
is
highest
and the net phase shift
is
into of the resonator’s impedance is 45 , which means that
the differential average
around
0°)
must the
lead loop
by 90is, as
is shown in Fig. 20. Note also that the
ET’s. Arguing purely by oscillation frequency is higher than the resonance of the tuned
Niknejad
University of California, Berkeley
s Ali
inM.the
two circuits are
•
•
•
Slide:
29
performances of the S-QVCO compared to
the P-QVCO.
possible
oscillation The
frequencies
and , both differing f
measurement results for a prototype of thethe
S-QVCO
fabricated
Further, the same LC:
noise also
natural tank
resonance frequency
Fig. 6.show
Fair phase-noise
comparison between
P-QVCO
and S-QVCO. , whic
an oscillation
in a standard 0.35- m CMOS process
which
modulates
YSIS AND DESIGN OF A 1.8-GHz CMOS LC QUADRATURE VCO
frequency of 1.8 GHz, a tuning range of 18%, a phase noise of transconductance
e P-QVCO, in the presence of different values for .
140 dBc/Hz or less at a 3-MHz offset frequency across the we obtain
frequencies
and , both differing f
,
tuning
range,
and an
error ofoscillation
at most 0.25
Linear
model
ofequivalent
QVCO isphasepossible
ption, there
will
be noconsumption
doubt that theofS-QVCO
LC:
the natural
tank resonance
for ashown.
current
mA from
a 2-V power
supply. frequency
The
loop gain 25
is easily
QVCO Loop Gain
•
m the P-QVCO.5
computed and the frequency at
which the loop gain is zero is
II. A SIMPLIFIED QVCO MODEL APPENDIX A
To estimate the effect on th
the oscillation frequency.
These equations can be simplified noting that
appears squared in (17)
duces a linear model for the P-QVCO, where
that the
is offoscillation frequencies to define
InNotice
this appendix,
weoscillation
find the possible
in the expres
the transconductance of the negative-resistance
resonance.
results
lower
for
the
linearized This
QVCO
circuit in
in
Fig.
7. The loop gain is easily
d
the transconductance
of the coupling
pair
phase
noise.
calculated
as
ng to this
figure and
also in the following, we
•
Fig. 7. Linear model for a QVCO.
onverted baseband signals and LO leakage at 1.75 GHz carrier
URE
VCO
1745
ge and
current signals to be fully differential:
56 dB).
Source: [Andreani]
wing into the tank is the difference between the These equations can be simplified noting that
As shown in Appendix A, the oscillation frequency
retwo branches of the differential stage. As a
LC from the and
therefore
possible oscillation frequencies
and , both differing
from displaced
sults
slightly
tank
resonance
. Using
(20), we can approxim
and assuming that (17)
isthe
thenatural
loss resistance
of
one
half-tank.
LC:
tank resonance frequency
by anthe
offset
, whose
magnitude
. This can
to (
inner square
root
in (18) asdepends on . According
According to Barkausen’s criteria, thealso
circuit
oscillates
when
be explained
in thelarger
following,
way. Referring
to
, which
can be neglec
this
term is much
than intuitive
is carrier
satisfied; further,
there
are in
two
thesignals
condition
baseband
and LO leakage at 1.75 GHz
in
Fig. 7,using
the losses
tankare balanced by a current in
Finally,
(19) and
the approximation
B).
matters even further, an additional variable is the value of the phase
, which is provided by
withfor ,
, we arrive at
valid
or widths,
. The results shown in
. The tank is now lossless, and the current from
acts on
d when both P-QVCO and S-QVCO shared the same value
LC-parallel. This second current, , is thus in quadrar,
can be largely reduced for the P-QVCO, in which an ideal (18)
. Using
andwith
assuming
that in turn implies
e decreases by approximately 2 dB in the
region, but
, which
that (20),
andwe can
areapproxim
phase
ture
to (
the inner
in (18)
l decibels in the
region. It should be noted that a lower shifted
. Fig.root
8 shows
the as
phasors of the. According
voltage across
by square
ows the
P-QVCO
to achieve
maximum
oscillation
These
equations
can abehigher
simplified
noting
that
whichTocan
this termand
is of
much
larger than
the currents
entering the, tank.
findbetheneglec
red to the S-QVCO, or, when the oscillation frequency and the the tank,
whichusing
is the same
as the
(2). approximation
Finally,
and
, we consider the loop in Fig.Slide:
7 as
e Ali
same
for both P-QVCO and S-QVCO, the capacitanceUniversity
in
lation
between
M. Niknejad
of California,
Berkeley (19)and
30
both transistors h
Fig. 2.
•
•
•
Ali M. Niknejad
QVCO in the Literature
Schematic view of the quadrature VCO presented in [7].
To see how the
(SSB) upconvers
so that the overal
very difficult to m
into the ratio of th
image band [to b
In the case of the
of 0.1% between
IBR of 70 dB for
and to 49 dB for
Source: [Andreani]
quickly larger wh
is weak
Several
toquadrature
the QVCO
have inbeen
proposed P-QVCO
for
Fig. 3. modifications
Schematic view of the
VCO proposed
this work.
improved performance
easy to check that
In particular, it has been shown that if a weaker coupling isdecreasing . Th
The present
analyzes
alternative
waycircuit
[16] oflocks
cross closer
noise performanc
introduced,
thepaper
phase
noise an
improves
(the
differential VCOs
obtain
a QVCO,
in which quadrature
the error performanc
tocoupling
the tanktworesonance),
but attothe
cost
of imperfect
is placed in series with
, rather P-QVCO present
coupling transistor
generation
in parallel
(Fig. quadrature
3). This choice
is motivated
by the connoise FoM, the h
A than
series
connected
generation
scheme
proposed
in the phase
P-QVCO
is responsible
for a large choosing
that has better
bysideration
[Andreani]
noise
performance.
contribution to the overall phase noise, and connecting
to unity. Slide: 31
University of California, Berkeley
in series with
, in a cascode-like fashion, should greatly
CK out,I
Static Frequency Dividers
/0102&34536$-0'780)$9:(;<=(<$-(8<)&'>
CK out,Q
tD Q
23456738
!"#$%&'
!"#$%&1
(
(
)
*+,
-.
-.
(
)
*+,
)
/0#
)
/0#
Fig. 5.22 (a) Typical static divider, (b) its waveform
#-.
-.
dition. As frequency goes up, the idle time d
/0#
VDD
!
!"#$%&%'()*%+,%-".(/$&$'$0-(1.("20"3$-4(560(275"#%'(
R
R
This is a simple divider structure uses a
• master/slave
8$9%9:(7(*%4$'5%*;($-(-%475$&%()%%/17"3
topology.
!
<75"#%'(=7.(1%($=>2%=%-5%/($-(&7*$0,'(67.'(
Two
latches
are cascaded into a
• negative
7""0*/$-4(50('>%%/?>06%*(*%+,$*%=%-5'
feedback loop (the output will
D
•
therefore toggle).
Since two clock cycles are required to
pass the data from one latch to the
next, it naturally divides by 2.
D in M 1
D
M2
Dout
M3
D in
M4
CKin
CKin
M6
M5
!"#"$%&''())
Ali M. Niknejad
RC
CKin
!*+$,-.
University of California, Berkeley
(a)
Slide:
32
device capacitance of the former can be absorbed as part of the latter. This topology
thus becomes attractive and popular at moderate to high frequencies.
Miller Divider (Regenerative)
! in , 3 ! in
2
x (t )
2
LPF
y (t )
! in
2
output signal of the feedback loop is mixed with the input
• The
signal. The output of the (ideal) mixer has the sum and
Fig. 5.25 Regenerative divider.
components.
Let usdifference
first examine
the division behavior and estimate the operation range. For
the difference
component
(due tounity.
the LPF)
the circuitOnly
to divide
properly, the
loop gain atis!amplified
Redrawing
in /2 must exceed
and
up. with simple RC filter and input amplitude A, we have
the divider
in gained
Fig. 5.26(a)
•
the loop gain is greater! than one
and the loop phase is zero
• Ifdegrees,
!
"A !
! !the input.
the system regenerates
)! ≥ 1,
(5.36)
!H( j
• The output frequency2in steady2 state must therefore satisfy:
in
where " denotes the conversion
gain=
of f
the
It can be further derived that
fout
− fout
inmixer.
"
# 1 $2
2fout = !infin 2
A≥
1+ 2
≥ .
(5.37)
"
2 !c
"
Ali M. Niknejad
University of California, Berkeley
Slide:
33
" xy
L
C
R
! in t
= B cos
M5
2/ "
y (t )
! in
t
M6
M
! in4
M3
Miller Divider Circuit Details
! in
2
2
Vin
2! n
Op. Range
A
B
190
(b)
(a)
VDD
L1
C1
M2
M1
L2
Vout
L
Y
X
C2
(c)
VDD
Vout
L
L
M 6 with bandpass filter; (b) its input sensitivity, (c) typical CMOS
M 5 Regenerative divider
Fig. 5.28 (a)
M3 M4
M4
M3
realization.
Vin
M
M5
A
M6
A
B
5
B
M4
!I
inj
M1
It is interesting
to note
input
M 2that a mixer has two V
M1
M 2 to two posVin
in M 1ports, that leads
sible configurations of Miller dividers. As illustrated in Fig. 5.29, the output could
(c)
(
(a)
8 (a) Regenerative divider with bandpass filter; (b) its input sensitivity, (c) typical CMOS
ion.
Fig. 5.30 (a) Type II regenerative divider, (b) redrawn to shown injecti
LO Port
LO Port
s interesting to note that
ports, that leads
V ina mixer has two input
be posredrawn as that inFilter
Fig. 5.30(b). V
It out
in fact resembles an i
Filter
V outto two
onfigurations of Miller dividers. As illustrated in Fig. 5.29, the output(which
could will be discussed in the next section): M3 and M4 for
RF Port
LO Port
Filter
in
RF Port
Ali M. Niknejad
V out
LO Port
Filter
(a)
and M5 and M6 appear as diode-connected transistors to lo
and
RFincrease
Port the locking range. The differential injection in
lieved to help
V inenlarge the range of operation to some extent
self-resonance frequency of the circuit if (W /L)3,4 > (W /L)
V out
(b)
• Use a double-balanced Gilbert cell mixer to realize divider
Fig. 5.29 Regenerative divider with the output fed back to (a) RF port, (b) LO port.
RF Port
V in
5.8 Injection-Locked Dividers
University of California, Berkeley
Slide:
34
Injection Locked Dividers [IL-Div]
Fig. 2. Model for a free-running LC oscillator.
.
terms with freq
an th-order s
intermodulation
o
equal to
which is the co
written as
injection locked divider is nothing but an injection locked
• An
system where the input frequency is at a harmonic of the freeFig. 3. Model for an injection-locked oscillator.
Using a comp
running frequency
of the oscillator.
Measurements
on a single-ended
ILFD (SILFD) are compared and applying th
Model
the system
a non-linearity
and a bandpass
with
simulations.
The as
simulation
results off(e)
a differential
ILFD be written as
transferare
function
H(ω).
(DILFD)
reported
as well.
•
that the free-running loop has a stable oscillation
• Assume
frequency. The system is injection locked to a super-harmonic
•
Ali M. Niknejad
II. MODEL FOR INJECTION-LOCKED OSCILLATORS
of the
free-running frequency.
An non-linearity
LC oscillator in
can
modeled
a nonlinear
block
The
thebeloop
must as
create
intermodulation
, followed
selective
block
(e.g., an RLC or
products
thatby
falla infrequency
the passband
of the
loop.
, in a positive feedback loop as shown in Fig. 2.
tank)
The nonlinear block models all the nonlinearities in the
oscillator, including any amplitude-limiting mechanism. To
University of California, Berkeley
have a steady-state oscillation,
a loop gain of unity should be
Slide:
35
IL-Div Analysis
the injection signal is a sinusoidal signal which is
• Suppose
added to the oscillator’s signal (at a sub-harmonic of the
injection). The non-linearity acts on both signals and is filtered
by the RLC circuit:
vi (t) = Vi cos(ωi t + φ)
vo (t) = Vo cos(ωo t)
u(t) = f (e(t)) = f (vo (t) + vi (t))
H0
H(ω) =
r
1 + j2Q ω−ω
ωr
can be shown that if the output signal contains various
• Itharmonics
and intermodulation terms which can be written
as:
u(t) =
∞ !
∞
!
Km,n cos(mωi t + mφ) cos(nω0 t)
m=0 n=0
• where K
m,n
Ali M. Niknejad
is the intermodulation component of f(vi+vo)
University of California, Berkeley
Slide:
36
IL-Div Fourier Analysis
• To see this, write the signals in the following form:
vi = Vi cos(β)
vo = Vo cos(α)
f (e) = f (vi + vo )
means that f is periodic in α and β. For every β define a
• which
periodic function g(α) as follows
g(α) = f (vo + Vi cos(α))
• Note that:
g(α + 2π) = g(α)
g(−α) = g(α)
• So that we can write:
g(α) =
∞
!
m=0
Ali M. Niknejad
Lm (β) cos(mα)
!
2π
1
L0 (β) =
f (Vo cos(β) + Vi cos(α))dα
0
! 2π
2π
1
Lm (β) =
f (Vo cos(β) + Vi cos(α)) cos(mα)dα
π 0
University of California, Berkeley
Slide:
37
IL-Div [Fourier Analysis cont.]
• But since L
m
Lm (β) =
is a periodic and even function of β we can write:
∞
!
Km,n cos(nβ)
n=0
• which results in:
f (vi + vo ) =
∞ !
∞
!
!
2π
1
Km,0 =
Lm (β)dβ
2π 0
! 2π
1
Km,n =
Lm (β) cos(nβ)dβ
π 0
Km,n cos(mα) cos(nβ)
m=0 n=0
that the tank filters out all frequencies except the
• Assume
ones around ω . That means that only intermodulation terms
o
that fall at ωo are relevant:
|mωi − nω0 | = ω0
Ali M. Niknejad
University of California, Berkeley
Slide:
38
IL-Div [Fourier cont]
the injection signal is an N’th superharmonic, then only the
• Ifintermodulation
terms
n = Nm ± 1
a frequency equal to 1/N the incident frequency. This
• possess
means that our summation can be written in terms of m as
∞
!
1
uω0 (t) = K0,1 cos(ω0 t) +
Km,N m±1 cos(ωo t + mφ)
2 m=1
complex notation and applying the oscillation condition,
• Using
the output signal can be written as
!
∞
"
jωo t
H
e
1
0
jω0 t
jmφ
vo = Vo e
=
K
+
K
e
0,1
m,N m±1
∆ω
2
1 + j2Q ωr
m=1
#
%
!
"
∞
1 $
∆ω
Vo 1 + j2Q
= H0 K0,1 +
Km,N m±1 ejmφ
ωr
2 m=1
Real Part:
Imag Part:
Ali M. Niknejad
!
∞
"
#
1
Vo = H0 K0,1 +
Km,N m±1 cos(mφ)
2 m=1
∞
∆ω
H0 !
2Vo Q
=
Km,N m±1 sin(mφ)
ωr
2 m=1
University of California, Berkeley
#
Slide:
39
IL-Div Locking Range
two equations can be solved for the unknown oscillation
• The
amplitude and phase for any incident amplitude and incident
frequency, or any offset frequency:
∆ω = (ωi /N ) − ωr
be re-written as:
• The second equation can
!
∆ω = ∆ωA
H0
2Vi
∞
"
#
Km,N m±1 sin(mφ)
m=1
• where Adler’s locking range has been identified:
ω r Vi
∆ωA =
2Q Vo
• Unlike static dividers, the locking range is limited.
Ali M. Niknejad
University of California, Berkeley
Slide:
40
IL Divide by 2 Circuit
equations can be solved analytically for a divide by 2 with
• The
cubic non-linearity
( )=
0+
2
3
+
+
1
2
3
2Q ∆ω
sin(φ) =
H0 a2 Vi ωr
!
! !
!
! ∆ω ! ! H0 a2 Vi !
!<!
!
| sin(φ)| < 1 → !!
ωr ! ! 2Q !
!
"
#
$%
4 1
3
Vo =
1 − H0 a1 + a3 Vi2 + a2 Vi cos(φ)
3 a3 H0
2
range is improved by using a large H0/Q or a larger
• Locking
injection amplitude. For an LC oscillator, this is equivalent to
using a larger inductor:
H0
= ωL
Q
impedance node is a convenient place to inject the signal
• Ato high
limit the injection power.
Ali M. Niknejad
University of California, Berkeley
Slide:
41
Fig. 7. Schematic of the single-ended injection-locked frequency divider.
IL-Div Circuit Details
a first-order differential
(23)
to the output phase (23)
ig. 6, it is clear that an
ion as a first-order PLL.
shaped by the low-pass
unction, and the output
he incident signal within
. However, unlike a
of an ILO is a function
ger for a larger incident
Fig. 8. Schematic of the differential injection-locked frequency divider.
injection signal is applied as a current to the tail of a cross• The
coupled
differential
oscillator.
ity,
the
biasing
circuitry
is not shown in this figure. A Colpitts
nsfer function is a little
oscillator currents
forms the core
of the SILFD.
The
incident signal
is
The
transistor
of
M1/M2
are
a
non-linear
function
of
e ILO itself. Within
the
•
injected
into (feedback)
the gate of M1.
Transistors
M1 and current
M2 are used
output
signal
and
the injected
of M3.
LO is suppressed the
by the
in cascode, mainly to provide more isolation between the input
dent power. Outside
the
Interestingly,
evenTransistor
in the absence
oftoanbeinjection
signal,
node
•
and
output.
M2
is
sized
smaller
than
M1
by
n increases by 20 M3
dB per
is moving at twice ω
phase noise region is
Ali M. Niknejad
o to reduce the parasitic capacitance
almost a factor of three
at the output node
(drain of M2). As a result, a larger
University of California, Berkeley
Slide:
42
little phase synchronization occurs. The lock range in this case
is the mixer conversion gain) at
direc
thebe
zero
crossings
theorinput
at
into
to injection
can
obtained
fromof(6)
(8): fall on the peaks of the output, oscillator.
If node
and is equivalent
switch abruptly
and theofca
little phase synchronization occurs. The lock range in this case nodeis the
conversion
gain) at, and (9) can dir
is mixer
neglected,
then
be
NG IN OSCILLATORS
1417
can be obtained from (6) or (8):
oscillator. If
and
switch abruptly and the c
(9)
, and (9) can b
node is neglected, then
IL-Div Intuitive Picture
(9)
The subtle difference between (6) and (9) plays a critical role in
If referred to the input, this range must be doubled:
quadrature oscillators (as explained below).
The
difference
betweenphase
(6) and
(9) playsacross
a critical
Fig.subtle
4 plots
the input-output
difference
therole
lockin
If referred to the input, this range must be doubled
quadrature
oscillators
(as explainedinjection
below). locking to
range.
In contrast
to phase-locking,
Fig. 4 plots
the input-output
phase
difference
across the lock
mandates
operation
away from
the tank
resonance.
range.
In contrasttotoQuadrature
phase-locking,
injection With
locking
1) Application
Oscillators:
theto
aid of a
mandates
operation
frommodel
the tank
resonance.
feedback
model
[13] or aaway
one-port
[14],
it can be shown Confirmed by simulations, (13) represents the uppe
Application
to Quadrature
Oscillators:
With oscillators
the aid of a
that1)
“antiphase”
(unilateral)
coupling
of two identical
the lock range of injection-locked dividers.
feedback
model
[13]
or
a
one-port
model
[14],
it
can
be
shown
forces them to operate in quadrature. It can also be shown [14]
Confirmed by simulations, (13) represents the up
thatthis
“antiphase”
(unilateral)
coupling
of twoshifts
identical
oscillators the lock range of injection-locked dividers.
that
type ofIntuitively
coupling
(injection
locking)
the
frequency
we canItsee
thatbe the
injection
at the tail III.
of Ithe
MOS
forces
them
to
operate
in
quadrature.
can
also
shown
[14]
NJECTION
PULLING
from resonance so that each tank produces a phase shift of
is mixed
due to the switching action of M1/
that this type cross-coupled
of coupling (injectionpair
locking)
shifts the frequency
the injected signal
out of, but n
M2.
III. frequency
INJECTIONlies
PULLING
Fig. each
5. (a)
Injection-locked
divider.
(b)of
Equivalent If
circuit.
from resonance
so that
tank
produces a phase
shift
from the lock range, the oscillator is “pulled.” We
(10)
If theby
injected
frequency
lies out
of,osci
but
For a strong mixing signal, 2/π component
ofcomputing
thissignal
current
will
behavior
the
output
phase
of an
from
theinjection.
lock range, of
the ω
oscillator
flow into the tank, at
frequency
shift
of by
harmonics
o. In is “pulled.” W
low-level
thealock
range exceeds
(9)
3.3%.
In other
(10)
behavior by computing
output
particular,
aforsignal
at
down-converted
intotheω
o will be
o, phase of an osc
where
denotes
the
current
injected
by 2
oneω
oscillator
into
difference
between
its
input
and
output,
words,
a 90 phase
low-level
injection.
the
tank
has high
impedance.
This
signal
therefore
A.
Phase
Shift
Through
a Tank
is an
theinjection-locked
current
produced
by
the
core
of
each
the other and where
oscillator
need
not
operate
at
the
edge
of
the
. where
Equations
(5)
denotes
the current
injected
by
onefrequency
oscillator
into
oscillator.
Use
of (5) therefore
gives
the
required
shift
experiences
a
large
loop
gain
and
can For
lock
the oscillator.
subsequent
derivations,
we need an express
lock
range.
A.
Phase
Shift
Through
a
Tank
is
the
current
produced
by
the
core
of
each
the
other
and
as
phase shift
introduced
by a tank in the vicinity of re
2) Application
to Dividers:
shows
an injecoscillator. Use of (5) therefore
gives the required
frequencyFig.
shift 5(a)
For subsequent
derivations,
we need
an ,expre
second-order
parallel
tank
consisting
of
,
and
stage
[15].
While
tion-locked oscillator operating as a phase
as
by a tank in the vicinity of
(11) a phase shift
shift introduced
of
nonlinear function
to consisting of , , and
(8) previous work has treated the circuit as asecond-order
parallel tank
derive the lock range [15], it is possible
adoptshift
a time-variant
(11) to
a phase
of
(9) would imply that each oscillator
is pushed
Ali M.Interestingly,
Niknejad
University of California,
Berkeley
Slide: 43
•
•
view to simplify the analysis. Switching at a rate equal to the
Miller Divider / Injection Locked Divider
190
Jri Lee
VDD
VDD
L
Vout
L
L
M4
M3 M4
M5
M6
A
M5
B
Vin M 1
M2
(a)
L
M3
M6
!I
+I
inj
M1
inj
M2
Vin
(b)
Fig. 5.30 (a) Type II regenerative divider, (b) redrawn to shown injection locking.
same circuit topology can be seen to be an injection
• The
locked divider or a Miller divider.
devices M5/M6 are not needed in the normal injection
• The
locked divider, but here they act to lower the Q of the tank,
be redrawn as that in Fig. 5.30(b). It in fact resembles an injection-locked divider
(which will be discussed in the next section): M3 and M4 form a cross-coupled pair,
and M5 and M6 appear as diode-connected transistors to lower the Q of the tank
and increase the locking range. The differential injection in such a manner is believed to help enlarge the range of operation to some extent. It is possible to find a
self-resonance frequency of the circuit if (W /L)3,4 > (W /L)5,6 [22].
•
Ali M. Niknejad
increasing the lock range.
A Miller divider can be designed so that it does not oscillate in
5.8 Injection-Locked
the absence
of an inputDividers
signal.
The operation speed of dividers can be further boosted up if we simplify the structure at the circuit level. Since a cross-coupled VCO provides ultimate simplicity in
generating differential oscillation,
may think
of injecting a periodic signal (apUniversity ofone
California,
Berkeley
Slide:
44
References
[Razavi]
B. Razavi, “A Study of Injection Locking and Pulling in Oscillators,” IEEE J. of Solid-State Circuits, vol. 39, no. 9,
Sept. 2004, pp. 1415-1424.
[Adler]
R. Adler, “A Study Locking Phenomena in Oscillators,” Proc. of the I.R.E. and Waves and Electronics, June 1946, pp.
351-357.
[Paciorek]
[Tsai]
K.-C. Tsai and P. R. Gray, “A 1.9-GHz, 1-W CMOS Class-E Power Amplifier for Wireless Communications,”
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