Microcomputer Block Diagram
A dd re ss Bu s
CPU
Da ta Bus
Co n tro l Bu s
In t e rf a ce Circ uit r y
RAM
ROM
Perip h er a l D e vice s
F1-1
TM-1
CPU Functional Units
CPU
Pro gr am Co u nt er ( PC)
In st r uc t io n Re g ist e r ( IR)
Re g ist e r 0
Inst r u ct io n De co d e
an d C on t r o l U nit
Re g ist e r 1
A r it h m et ic an d
Lo g ic Un it ( A LU )
Reg ist er n - 1
F1-2
TM-2
Opcode Fetch
CPU
A d dr e ss Bu s
N
Pr o g ram
Co u n t e r
D a t a Bu s
Op c od e
RA M
Inst ru ct io n
Re g ist e r
N+2
N+1
Co nt ro l
Bus
Op co d e
Clo ck
N
N-1
Re ad
F1-3
TM-3
Memory Maps
1 Byte
F FFF
7 6 5 4 3 2 1 0
6 5 ,5 3 5
FF FF
4 K ROM
F0 0 0
EFFF
4 4 K Em pt y
De cim a l
A dd re sse s
H exa d ec im al
A d dr esse s
.
.
.
0004
0003
0002
0001
0000
4000
3 FFF
4
3
2
1
1 6 K RA M
0000
0
F1-6/7
TM-4
16-Bit Addresses
Bit 1 5 =
m os t -sig n if ican t b it
15
14
13
12
B it 0 =
lea st -sig n if ica nt bit
11
10
9
8
7
6
5
4
3
2
1
0
1
1
(a )
9
1
0
F
C
0
1
1
1
0
0
1
1
3
1
1
0
0
(b )
F1-8
TM-5
The Development Cycle
Specify
software
Design
software
Edit
Translat e
Preliminary
t est ing
Int egrate
and
verify
Concept
Specify
hardware
Design
hardware
Build
prot otype
Product
Preliminary
t est ing
1-11
TM-6
Steps in
the Development Cycle
List ing
f ile
( .L ST)
Edit o r
Sou rc e
f ile
(. SRC)
A sse m b le r
L ist in g
f ile
( .M A P)
Ob je ct
f ile
(. OBJ)
L in ke r/
lo ca t o r
A b so lut e
o b je ct
f ile
Sim ula t o r
So f t ware
sim u lat io n
Em u lat o r
Ha rdw are
em u lat io n
(For a b solu t e f iles)
OBJHEX
c o nv er sio n
Le g e nd :
Ut ilit y p ro g ram o r
d ev elo p m e nt t o o l
He x
f ile
(. HEX)
Do wn lo ad /
t e rm in al
e m ula t e
RA M
Use r f ile
EPROM
Pro g ram m er
EPROM
Fact o ry
m ask
p ro ce ss
ROM
Ex ec ut io n e nv iro nm e n t
1-13
TM-7
Motorola S-records
S00900006D796E616D656F
S11320003C3C000A327C201661000020534666F4F2
S11320101E3C00E44E4E53636F7474204D61634B59
S10C2020656E7A6965200D0A0061
S113202A1E3C00F81019670000064E4E60F64E7505
S9030000FC
(a)
S1 1 3 2 0 0 0 3 C3 C0 0 0 A 3 2 7 C2 0 1 6 6 1 0 0 0 0 2 0 5 3 4 6 6 6 F4 F2
Che ck sum
Da t a By t es
Lo ad A d d r ess
Byt e Co u n t
Re co r d T y pe
(b)
1-14
TM-8
68000 Programmer's Model
31
16
31
8 7
0
16 15
31
31
15
D0
D1
D2
D3
D4
D5
D6
D7
D at a
Re g is t e rs
A0
A1
A2
A3
A4
A5
A6
A dd re ss
Reg ist ers
0
16 15
0
24 23
A7
U ser St ack Po int e r ( USP)
A7
Su p erv iso r St ac k Po in t e r (SSP)
0
PC Pro g ra m Co un t er
15
8 7
0
123
SR St a t u s Re g ist e r
CCR
F2-1
TM-9
68000 Status Register
U ser By t e
( Co nd it io n Co d e Re gist er )
Syst e m Byt e
15
13
10
9
8
4
3
2
1
0
T
S
I2
I1
I0
X
N
Z
V
C
123
Carry
Ove rf lo w
Ze ro
Ne g at ive
Sig n Ex t e nd
Int er rup t M ask
Sup e rviso r St a t e
Trac e Mo d e
F2-4
TM-10
Condition Code Computation
1 1 1
+
00011001
01110000
10001001
C = Sm D m + Rm D m + Sm Rm
= 0 0 + 0 0 + 0 0
= 0
Z = 0
N = 1
V = Sm Dm Rm + Sm D m Rm
= 0 0 0 + 1 1 1
= 1
X = C = 0
Rm = 1
Dm = 0
Sm = 0
F2-5
TM-11
68000 Memory Map
-- Byte View --
1 By t e
( 8 b it s)
F FFFF F
0 000 04
0 000 03
0 000 02
0 000 01
00 000 0
F2-7
TM-12
68000 Memory Map
-- Word View --
1 W ord ( 1 6 b it s)
FFF FFE
By t e FFF FFE
By t e FFF FFF
N ot e :
Ev e n b y t e s co r re spo n d
t o u p pe r b yt es o n t h e
ex t e rn al d at a b us. Od d
b yt es c o r r esp o n d t o lo w e r
b yt es o n t h e e xt er n al
d at a b us.
By t e 5
By t e 4
By t e 2
By t e 0
Byt e 3
By te 1
0 000 04
0 000 02
00 000 0
F2-8
TM-13
68000 Memory Map
-- Longword View --
1 L o ng w or d ( 3 2 b it s )
W or d a dd re ss: n + 4
B yt e n + 4
L o ng w o rd s
ca n b e at a ny
e ve n a dd re ss
et c.
n + 8
n + 4
n
B yt e n
1
2
B yt e n + 1
3
Wo rd ad d ress: n
B y te n + 2
1
2
B y te n + 3
3
W o rd ad dr ess: n + 2
F2-9
TM-14
68000 Addressing Modes
Assembler
Syntax
Effective Address
Generation
Data Register Direct
Dn
EA = Dn
Address Register Direct
An
EA = An
Absolute Short
xxx.W or <xxx
EA = (next word)
Absolute Long
xxx.L or >xxx
EA = (next two words)
Register Indirect
(An)
EA = (An)
Postincrement Register Indirect
(An)+
EA = (An), An ` An + N
Predecrement Register Indirect
-(An)
An ` An - N, EA = (An)
d16(An)
EA = (An) + d16
d8(An,Xn)
EA = (An) + (Xn) + d8
d16(PC)
EA = (PC) + d16
d8(PC,Xn)
EA = (PC) + (Xn) + d8
#data
DATA = next word(s)
CCR, SR, USP,
SSP, PC
EA = CCR, SR, USP, SSP, PC
Mode
Register Indirect with Offset
Register Indirect with Index & Offset
PC Relative with Offset
PC Relative with Index and Offset
Immediate
Implied Register
Notes:
EA = effective address
An = address register
Dn = data register
Xn = address or data register used as index register
CCR = condition code register
SR = status register
USP = user stack pointer
SSP = supervisor stack pointer
PC = program counter
( ) = contents of
d8 = 8-bit offset (displacement)
d16 = 16-bit offset (displacement)
N = 1 for byte, 2 for word, 4 for longword. (If An is the
stack pointer and the operand size is byte, N = 2 to
keep the stack pointer on a word boundary.)
` = is replaced by
T2-1
TM-15
Data Register Direct
Instruction: MOVE.B D0,D3
Register Contents
Before:....D0.....10204FFF
...........D3.....1034F88A
After:.....D0.....10204FFF
...........D3.....1034F8FF
On ly b it s 0 -7
af f ec t e d
F2-10
TM-16
Address Register Direct
Instruction:
Before:
After:
MOVEA.L A3,A0
Register Contents
A0.....00200000
A3.....0004F88A
A0.....0004F88A
A3.....0004F88A
Mo ve t o
a d dr e ss r e g ist e r
3 2 bit s are
m ov e d
F2-11
TM-17
Absolute Short
Instruction:
Before:
After:
MOVE.L #$1E,$800
**** MEMORY ****
Address Contents
000800
12
000801
34
000802
56
000803
78
000800
000801
000802
000803
00
00
00
1E
So urc e a dd re ssin g
m o d e is im m e d ia t e
De st in at io n a dd re ssin g
m o d e is ab so lu t e sho rt
3 2 -b it o p e ran d siz e
m o v es d at a t o f o u r
c on se cu t iv e b y t e
lo ca t io n s
F2-13
TM-18
Absolute Long
Instruction: MOVE.B #$1E,$8F000
Before:
After:
**** MEMORY ****
Address Contents
08F000
FF
08F000
1E
D est ina t io n ad d ressin g
m od e is a b so lut e lo n g
Op era n d siz e
is b yt e
F2-14
TM-19
Register Indirect
Instruction:
Before:
After:
MOVE.L D0,(A0)
**** MEMORY ****
Address Contents
001000
55
001001
02
001002
3F
001003
00
001000
001001
001002
001003
10
43
83
4F
A0 co nt ain s t h e
a d dr ess o f t h e
d e st in at ion
Registers
A0 00001000
D0 1043834F
A0 do e s no t
ch an g e
A0 00001000
D0 1043834F
A lo n g w o r d is w r it t e n t o
ad d r e ss $ 0 0 1 0 0 0
F2-17
TM-20
Postincrement Address
Register Indirect
Instruction:
Before:
After:
MOVE.W (A5)+,D0
**** MEMORY ****
Address Contents
001000
45
001001
67
001002
89
001003
AB
001000
001001
001002
001003
45
67
89
AB
Registers
A5 00001000
D0 0000FFFF
A dd re ss re gist e r
in cr em e n t e d b y
nu m b e r o f b y t e s
m ov e d, 2
A5 00001002
D0 00004567
F2-18
TM-21
Predecrement Address
Register Indirect
Instruction:
MOVE.W D0,-(A7)
**** MEMORY ****
Address Contents
Before: 001000
10
001001
12
001002
83
001003
47
After:
001000
001001
001002
001003
01
43
83
47
Registers
A7 00001002
D0 00000143
A dd re ss re gist e r
d e cre m en t ed b y
nu m b e r o f b y t e s
m ov e d, 2
A7 00001000
D0 00000143
F2-19
TM-22
Register Indirect
With Offset
Instruction: MOVE.W 6(A0),D0
**** MEMORY ****
Address Contents
Before: 001026
07
001027
BF
After:
001026
001027
07
BF
Ef f e ct ive a d dr ess is
6 p lu s va lu e in A 0
Registers
A0 00001020
D0 00000000
A d dre ss r e g is t e r
do e s no t ch an g e
A0 00001020
D0 000007BF
F2-20
TM-23
Register Indirect
With Index and Offset
A d dr ess r e g ist e r
Ind e x r eg ist er , 3 2 b it s
Instruction: MOVEA $10(A0,D0.L),A1
Before:
After:
**** MEMORY ****
Address Contents
00101C
EF
00101D
10
00101C
00101D
EF
10
Registers
A0 0000100A
A1 00000000
D0 00000002
A0 0000100A
A1 FFFFEF10
D0 00000002
W o r d v alu e is
sig n-e xt en d ed
b e ca use d est ina t io n
is a n a dd r e ss r e gist e r
No t e:
EA = $ 1 0 + $ 1 0 0 A + $ 2 = $ 1 0 1 C
F2-22
TM-24
PC-Relative
With Offset
Instruction:
MOVE.W $1020(PC),D5
**** MEMORY ****
Address Contents
Before: 001020
AB
001021
CD
After:
001020
001021
AB
CD
Registers
PC 00001000
D5 12345678
In st r uc t io n is t w o
w o rd s lo ng , s o PC is
in cr em e n t e d b y f o ur
PC 00001004
D5 1234ABCD
F2-23
TM-25
PC-Relative
With Index and Offset
Instruction:
Before:
After:
MOVE.W $1020(PC,D0.W),D5
**** MEMORY ****
Address Contents
001026
FE
001027
DC
001026
001027
FE
DC
Registers
PC 00001000
D0 ABCD0006
D5 12345678
On ly lo w - o rd er
1 6 b it s o f D 0 use d
a s ind e x
PC 00001004
D0 ABCD0006
D5 1234FEDC
F2-26
TM-26
Immediate
Instruction:
Before:
After:
MOVE.L #$1FFFF,D0
Register Contents
D0
12345678
D0
0001FFFF
Im m e dia t e d at a
f ollo w
Base :
$ = he xa d ecim al
@ = oc tal
% = b in a ry
& ( o r n o t h in g ) = d ec im al
' A B' = A SCII ch ara ct er s
F2-28
TM-27
68000 Signals
Vc c (2 )
A d dr ess Bu s
GND (2 )
A1 -A 2 3
68000
D at a Bu s
D0 -D1 5
CL K
AS
R/ W
Pro ce ssor
St a t u s
MC 6 8 0 0
Perip h era l
Co n t ro l
Sy st e m
Co n t r ol
FC0
UDS
FC1
L DS
FC2
D TA CK
E
BR
V MA
BG
VPA
BGAC K
B ERR
IPL0
RESET
IPL1
HA L T
IPL2
A syn ch ro n o us
Bu s
Co n t ro l
Bu s
A rb it ra t io n
Co n t ro l
In t e rrup t
Co n t ro l
F2-33
TM-28
Upper Data Strobe and
Lower Data Strobe
Int er n a l
Sig n als
A2 3
A1
Bu s
Sig n als
A2 3
A1
A0
UD S
( ev en b yt e)
WORD / BYT E
LD S
WORD / BYT E
A0
U DS
L DS
1
X
0
0
0
0
0
1
0
1
1
0
( o dd b yt e )
( a)
(b )
F2-34
TM-29
Decoding with
-UDS and -LDS
68 0 00
A 1 -A2 3
A d d r e ss B us
D 8 -D 1 5
D a t a B us ( u pp e r b y t e)
D 0 -D7
D a t a B us ( l ow er b y t e )
A d dre ss
De co d ing
UD S
Up p er
RA M
CS
Lo wer
RAM
CS
L DS
F2-36
TM-30
Generation of -DTACK
A d dre ss Bu s
6 80 0 0
A dd re ss
De co d ing
74 07
RA M
CS
Ad d re s s
D e co d ing
740 7
RA M
CS
+5 V
10 K
Fro m o t h e r RA Ms ,
ROM s, I/ O De v ic es , et c.
DT A CK
F2-36
TM-31
Function Code Outputs
Function Code
FC2
FC1
FC0
Address Space Type
0
0
0
(Undefined, reserved)
0
0
1
User Data
0
1
0
User Program
0
1
1
(Undefined, reserved)
1
0
0
(Undefined, reserved)
1
0
1
Supervisor Data
1
1
0
Supervisor Program
1
1
1
CPU Space (Interrupt Acknowledge)
T2-3
TM-32
Read Cycle Timing
D at a lat ch e d in t o
CPU at be g in nin g
o f S7
DT AC K m u st b e
asse rt ed b ef o r e t h e e n d
o f S4 , ot h erw ise w ait
st at es ar e in sert ed
S0
S1
S2
S3
S4
S5
S6
S7
CLK
FC0 -FC2
A1 -A2 3
AS
UDS
L DS
R/ W
DT A CK
D8 - D1 5
D0 - D7
F2-39
TM-33
Write Cycle Timing
S0
S1
S2
S3
S4
S5
S6
S7
CL K
FC0 -FC2
A1 -A2 3
AS
UDS
L DS
R/ W
DT A CK
D8 - D1 5
D0 - D7
F2-40
TM-34
Data Movement Instructions
Instruction
Operation
EXG
Exchange registers
LEA
Load effective address
LINK
Link and allocate stack
MOVE
Move source to destination
MOVEA
Move source to address register
MOVEM
Move multiple registers
MOVEP
Move to peripheral
MOVEQ
Move short data to destination
PEA
Push effective address
UNLK
Unlink stack
T3-3
TM-35
Integer Arithmetic Instructions
Instruction
Operation
ADD
Add source to destination
ADDA
Add source to address register
ADDI
Add immediate data to destination
ADDQ
Add short data to destination
ADDX
Add with extend bit to destination
CLR
Clear operand
CMP
Compare source to destination
CMPA
Compare source to address register
CMPM
Compare memory
DIVS
Signed divide
DIVU
Unsigned divide
EXT
Sign extend
EXTB
Sign extend byte
MULS
Signed multiply
MULU
Unsigned multiply
NEG
Negate
NEGX
Negate with extend
SUB
Subtract source from destination
SUBA
Subtract source from address register
SUBI
Subtract immediate from destination
SUBQ
Subtract short from destination
SUBX
Subtract with extend bit from destination
T3-4
TM-36
CMP Example
Instruction:
CMP.B #'z',D7
Register Contents
Before:
D7
FFFFFF7A
SR
001F
After:
Notes:
D7
SR
FFFFFF7A
0014
A SCII co d e f o r
'z ' is $ 7 A
D 7 also co n t a in s
ASCII co d e f or ' z'
D7 d o e s n o t
ch an g e
01111010
- 01111010
00000000
12 3
Z= 1
N = 0
V = 0 ( sig n b it d oe s n ot ch an g e)
C = 0 ( b o rro w no t re q u ir ed )
X = 1 (n o ch an g e)
F3-5
TM-37
DIVS Example
Instruction:
DIVS #-3,D7
Register Contents
Before:
D7
0000000E
SR
001F
After:
D7
SR
0002FFFC
0018
Div is or , - 3
D ivid en d , 1 4
Qu o t ie n t , -4
Re m ain d er , 2
Notes: 14 / -3 = -4 with a remainder of 2
F3-8
TM-38
Boolean Instructions
Instruction
Operation
AND
AND source to destination
ANDI
AND immediate data to destination
EOR
Exclusive OR source to destination
EORI
Exclusive OR immediate data to destination
NOT
Complement destination
OR
OR source to destination
ORI
OR immediate data to destination
Scc
Test condition codes and set operand
TST
Test operand and set condition codes
T3-5
TM-39
EOR Example
Instruction: EOR.L D6,(A4)+
**** MEMORY ****
Address Contents
Before: 003100
AB
003101
CD
003102
EF
003103
10
After:
003100
003101
003102
003103
Notes:
ABCDEF10
+ 12345678
B9F9B968
1 2 3
B9
F9
B9
68
Z=
N =
V =
X =
Registers
A4 00003100
D6 12345678
SR
0000
So ur ce o p e ran d
De st ina t io n o p e ran d
A4 00003104
D0 12345678
SR
0008
A 4 in cre m en t ed
by four
0
1
C = 0 ( alw a ys)
n ot af f e ct e d ( assu m e 0 )
F3-10
TM-40
Shift and Rotate Instructions
Instruction
Operation
ASL
Arithmetic shift left
Bit Movement
C
Op era n d
0
X
ASR
Op er a nd
Arithmetic shift right
C
X
LSL
C
Logical shift left
Ope ra nd
0
Op e ran d
C
X
LSR
0
Logical shift right
X
ROL
Rotate left
C
ROR
Rotate right
ROXL
Rotate left with extend bit
ROXR
Rotate right with extend bit
SWAP
Swap words of a longword
Op e ran d
C
X
Op er an d
C
Op e ran d
X
Op era nd
1 6 b it s
C
1 6 b it s
T3-6
TM-41
ASR Example
Instruction:
Before:
After:
Notes:
A rit hm e t ic shif t
righ t : sig n b it
d o es n o t ch an g e !
ASR.B D3,D2
Register Contents
D3
00000002
D2
00000068
SR
001F
D3
D2
SR
Sh if t c o un t in D3
Sh if t d at a in D 2
00000002
0000001A
0000
01101000
00110100
00011010
1 2 3
0
C =
Z=
N =
V =
X = 0
0
0
0 ( alw ay s)
F3-11
TM-42
Bit Manipulation Instructions
Instruction
Operation
BCHG
Change bit
BCLR
Clear bit
BSET
Set bit
BTST
Test bit
T3-7
TM-43
BTST Example
Instruction:
Before:
After:
BTST #7,D5
Register Contents
D5
FFFFFF7F
SR
0000
D5
SR
FFFFFF7F
0004
T e st b it 7 o f D 5
Bit 7 = 0
Z = 1
F3-12
TM-44
Binary-Coded Decimal Instructions
Instruction
Operation
ABCD
Add source to destination
NBCD
Negate destination
SBCD
Subtract source from destination
T3-8
TM-45
ABCD Example
Instruction: ABCD -(A3),-(A4)
Before:
After:
**** MEMORY ****
Address Contents
00200E
98
00210E
54
00200E
00210E
O p e r an d siz e
alw a ys b y t e
Registers
A3 0000200F
A4 0000210F
SR
001F
98
53
A3 0000200E
A4 0000210E
SR
0011
10011000
01010100
1
+
1 1
11101101
+ 00000110
11 1
11110011
+ 01100000
01010011
1
2 3
Bot h a d dr ess r e g ist e r s
d e cr e m en t ed b y o n e
---XNZVC
00010001
1
Notes:
X= 1
(X = 1 )
98 + 54 + 1 = 15 3
( t h e h u nd r e d s d ig it
is st o r e d in C & X)
( ad d 0 6 )
( ad d 6 0 )
Z= 0
C = X = 1
N = V = u nd e f ine d ( a ssum e 0 )
F3-13
TM-46
Program Flow Instructions
Instruction
Operation
Bcc
Branch conditionally
BRA
Branch always
BSR
Branch to subroutine
DBcc
Test, decrement, and branch
JMP
Jump to address
JSR
Jump to subroutine
NOP
No operation
RTE+
Return and deallocate stack
RTR
Return and restore condition codes
RTS
Return from subroutine
+privileged instruction
T3-9
TM-47
BRA Example
Instruction:
Before:
BRA $20A0
Br a n ch d e st in at io n
**** MEMORY ****
Address Contents
002050
60
002051
4E
Registers
PC 00002050
In st r uc t io n w o r d
After:
002050
002051
60
4E
PC 000020A0
Notes:
Displacement = X
2052 + X = 20A0
X = 20A0 - 2052
= 4E
Bra n ch o f f s et , 8 b it s
F3-15
TM-48
BSR/RTS Example
BSR $ 4 0 F2
BEFO RE
A FT ER
RE GIS T ERS:
RE GIS T ERS:
PC
A7
PC
A7
0 0 5 0 16
0 000 305 0
MEMO RY:
0 0 4 0 F2
0 000 304 C
MEMO RY:
00 501 A
0 0 5 0 1 8 F0 DA
00 501 6 6 1 0 0
0 0 4 0 F A 4 E7 5
MA IN
PROGRA M
00 50 1A
0 0 5 0 1 8 F0 DA
00 50 16 6 1 00
BSR $ 4 0 F2
0 0 4 0 F A 4 E7 5
RTS
MA IN
PROGRA M
BSR $ 4 0 F2
RTS
SU BROU TIN E
SU BROU TIN E
0 0 4 0 F2
0 0 4 0 F2
00 3 05 0 1 234
00 3 04 E 5 678
0 0 3 0 4 C 9 A BC
A7
00 3 05 0 1 234
00 3 04 E 5 01A
00 3 04 C 0 000
STA CK
STA CK
A7
a dd re ss o f
ins t ru ct ion
f o llo w in g BSR
RT S
BEFORE
A FT ER
REGIST ERS:
REGIST E RS:
PC
A7
PC
A7
0 0 4 0 FA
0 00 0 3 04 C
MEMORY:
00 5 01 A
0 0 5 0 1 8 F0 DA
00 5 01 6 61 00
0 0 4 0 FA 4 E7 5
0 05 01A
0 00 0 30 5 0
ret u r n t o
in st r u ct io n
f o llo w in g BSR
MEMORY:
MA IN
PROGRA M
00 5 01 A
0 0 5 0 1 8 F0 DA
00 5 01 6 61 00
BSR $ 4 0 F2
0 0 4 0 FA 4 E7 5
RT S
MA IN
PROGRA M
BSR $ 4 0 F2
RT S
SU BROU TINE
SU BROU TINE
0 0 4 0 F2
003 050 1 2 34
003 04E 5 0 1A
003 04C 0 0 00
0 0 4 0 F2
003 050 1 23 4
003 04E 5 01 A
003 04C 0 00 0
ST A CK
A7
A7
ST A CK
F3-16
TM-49
System Control Instructions
Instruction
Operation
ANDI++
AND immediate to status register/condition code register
CHK
Trap on upper out-of-bounds operand
EORI++
Exclusive OR immediate to status register/condition code
register
ILLEGAL
Illegal instruction trap
MOVE++
Move to/from status register/condition code register
ORI++
OR immediate to status register/condition code register
RESET+
Assert RESET line
STOP+
Stop processor
TAS
Test and set operand
TRAP
Trap unconditionally
TRAPV
Trap on overflow
+privileged instruction
++privileged instruction if SR specified
T3-10
TM-50
TRAP Example
Instruction: TRAP #5
Before:
V ec t o r
ad d r e ss
f o r t ra p 5
After:
Notes:
**** MEMORY ****
Address Contents
002FFA
12
002FFB
34
002FFC
56
002FFD
78
002FFE
9A
002FFF
BC
000094
00
000095
01
000096
80
000097
F0
002FFA
002FFB
002FFC
002FFD
002FFE
002FFF
000094
000095
000096
000097
Registers
PC 00002000
A7' 00003000
SR
001F
V ec t o r f o r
t rap 5
00
1F
00
00
20
02
00
01
80
F0
PC 000180F0
A7' 00002FFA
SR
201F
SR sa ve d o n
syst em st ac k
Sy st e m
St a ck Po int er
Exc ep t ion p ro ce ssing
b e gin s at ad d r ess
$ 0 1 8 0 F0
Sy st e m
St a ck Po int er
d e cr e m e nt ed
by 6
Su p er viso r St a t e
b it = 1
PC sav ed o n
sy st e m st a ck
Vector read from address $80 + (5 x 4) = $94
F3-18
TM-51
68000 Instruction Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Operation Word
(1st word specifies operation and addressing modes)
Immediate Operand
(if any, one or two words)
Source Effective Address Extension
(if any, one or two words)
Destination Effective Address Extension
(if any, one or two words)
F3-19
TM-52
Effective Address Encoding
Addressing Mode
Mode Bits
Register Bits
Data Register Direct
000
register number
Address Register Direct
001
register number
Address Register Indirect
010
register number
Address Register Indirect with
Postincrement
011
register number
Address Register Indirect with
Predecrement
100
register number
Address Register Indirect with
Displacement†
101
register number
Address Register Indirect with Index*
110
register number
Absolute Short†
111
000
Absolute Long††
111
001
Program Counter with Displacement†
111
010
Program Counter with Index*
111
011
Immediate or Status Register†††
111
100
†
One extension word required
††
Two extension words required
†††
For Immediate addressing, one or two extension words required
depending on the size of the operation
*
One extension word required; see Table C-4 for the encoding
T3-11
TM-53
68000 Condition Code Encoding
Mnemonic
T†
Condition
true
Encoding
0000
Test
1
F†
HI
LS
CC(HS)
CS(LO)
NE
EQ
VC††
false
0001
high
low or same
carry clear
carry set
not equal
equal
overflow clear
0010
0011
0100
0101
0110
0111
1000
0
C •Z
C+Z
overflow set
1001
V
plus
minus
greater or equal
1010
1011
1100
N
N• V + N • V
VS††
PL
MI
GE††
C
C
Z
Z
V
N
LT††
GT††
less than
1101
N• V + N •V
greater than
1110
N• V •Z +N • V • Z
LE††
less or equal
1111
Z + N• V + N •V
† Not available for Bcc instruction
†† Twos complement arithmetic
• = Boolean AND
+ = Boolean OR
T3-12
TM-54
Opcode Map
Bits
15 through 12
Operation
0000
Bit Manipulation/MOVEP/Immediate
0001
Move Byte
0010
Move Long
0011
Move Word
0100
Miscellaneous
0101
ADDQ/SUBQ/Scc/DBcc
0110
Bcc/BSR
0111
MOVEQ
1000
OR/DIV/SBCD
1001
SUB/SUBX
1010
(Unassigned)
1011
CMP/EOR
1100
AND/MUL/ABCD/EXG
1101
ADD/ADDX
1110
Shift/Rotate
1111
(Unassigned)
T3-13
TM-55
Assembler Operation
PROG.OBJ
L eg e nd :
Ut ilit y p ro g ram
PRO G.SRC
A68 K
Use r f ile
PROG.L ST
( a)
C o m m an d
( b)
Inp u t
f ile
Lis t ing
o ut ut f ile
O b je ct co d e
o ut p ut f ile
A ssem ble r
op t ion s
A 6 8 K PROG.SRC, PRO G.L ST , PROG.OBJ, X S
F4-1
TM-56
Assembler Files
La b el
f ield
PROG
LOOP
Mn e m o nic
f ie ld
Op er an d
f ie ld
C om m en t
f ield (e m p t y )
ORG.....$1000
LEA.....$800,A0
MOVE.B..#50,D0
CLR.W...D7
ADD.W...(A0)+,D7
SUBQ.B..#1,D0
BRA.....*
END
Sou r ce
f ile
( a)
L ine nu m b e r
A d d re ss
1
2
3
4
5
6
7
8
Co n t e n t s
So u rce f ile
00001000.................ORG.....$1000
00001000.41F80800.PROG...LEA.....$800,A0
00001004.103C0032........MOVE.B..#50,D0
00001008.4247............CLR.W...D7
0000100A.DE58.....LOOP...ADD.W...(A0)+,D7
0000100C.5300............SUBQ.B..#1,D0
0000100E.60FE............BRA.....*
00001010.................END
L ist in g
f ile
(b )
F4-2
TM-57
Listing Examples
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
00001000
00001000
00001002
00001004
00001008
00000064
0000100A
0000100E
00001012
00001016
0000101A
0000101E
00001022
00001026
0000102A
0000F000
0000102C
00001030
00001032
00001034
00001036
00001038
6006
60FE
6000FFFE
181B
3A3C0064
3A3C0064
3A3C0064
3A3C0064
3A3C0064
3E3CFFFB
3E3CFFFB
3A390000
F000
3A390000
F000
4E71
4E71
67FA
ORG
BRA
BRA
HERE BRA
MOVE.B
COUNT EQU
MOVE.W
MOVE.W
MOVE.W
MOVE.W
MOVE.W
MOVE.W
MOVE.W
MOVE
$1000
*+8
*
HERE
(A3)+,D4
100
#COUNT,D5
#100,D5
#$64,D5
#144Q,D5
#%01100100,D5
#-5,D7
#$FFFB,D7
$F000,D5
;"*" location counter
;branch to itself
;branch to itself
;indirect addressing
;equate symbol to value
;symbol as immed. data
;decimal
;hexadecimal
;octal (A68K format)
;binary
;negative number, decimal
;negative number, decimal
;data address
PORT
EQU
MOVE
$F000
PORT,D5
;equate symbol as address
;data address (symbol)
BACK
NOP
NOP
BEQ
END
;code address (NOP =
;
no operation)
BACK
F4-4
TM-58
Assemble-Time Operators
Operator†
.NOT.
.LOW.
.HIGH.
.LWRD.
.HWRD.
*
/
+
.MOD.
.SHR.
.SHL.
.AND.
.OR.
.XOR.
.EQ.
Function
Precedence
Type
Unary minus
Logical NOT
Low byte
High byte
Low word
High word
Multiplication
Division
Addition
Subtraction
Modulo
Logical shift right
Logical shift left
Logical AND
Logical OR
Logical XOR
Equal††
1
1
1
1
1
1
3
3
4
4
3
3
3
5
6
6
7
Unary
Unary
Unary
Unary
Unary
Unary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
.NE.
Not Equal††
7
Binary
.GE.
Greater or equal††
Less or equal††
7
Binary
7
Binary
Greater than††
Less than††
7
Binary
7
Binary
Unsigned greater than††
Unsigned less than††
7
Binary
7
Binary
.LE.
.GT.
.LT.
.UGT.
.ULT.
†Operators apply to A68K. Different assemblers may support different
operators.
††Relational operators return 1s (true) or 0s (false).
T4-1
TM-59
Examples of
Assemble-Time Operators
1
2
3
4
5
6
7
8
9
10
11
00000064
00002000
00002000
00002004
00002008
0000200C
00002010
00002014
00002018
0000201C
00002020
COUNT
3A3CFFFF
3A3C0009
3A3C0001
3A3C0400
3A3C0040
3A3C0041
3A3CFFFF
3A3C0032
EQU
ORG
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
END
100
$2000
#-1,D5
#4+50/10,D5
#25.mod.6,D5
#$8000.shr.5,D5
#$45&$F0,D5
#.high.'AB',D5
#5.gt.4,D5
#COUNT/2,D5
F4-5
TM-60
Assembler Directives
Directive
Operation
ORG
set program origin
EQU
Syntax
ORG
value
equate value to symbol
symbol EQU
value
END
end of source program
END
label
DC
define data constant
[label]
DC
number[,number][...]
DS
define RAM storage
[label]
DS
count
RSEG
begin relocatable segment
RSEG
name
EXTERN
define external symbol
EXTERN symbol[,symbol][...]
PUBLIC
define public symbol
PUBLIC symbol[,symbol][...]
T4-2
TM-61
Listing Examples
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Address
00001000
00001000
00000064
00002000
00002000
0000000D
00003000
00003000
00003004
00003006
0000300A
00004001
00004002
00005000
00005000
00000050
00006000
00006000
00006050
00007000
00007000
00007002
00007006
0000700A
0000700C
00000000
00000000
00000004
Contents
1A3C0064
1A3C0064
0005FFFF
05FF
4A4F484E
0D00
000F
6100
7250
327C6000
12FC0000
5301
66F8
1A3C002C
***************
ORG
START MOVE.B
COUNT EQU
ORG
HERE
MOVE.B
CR
EQU
ORG
NUM
DC
MORE
DC.B
NAME
DC.B
DC.B
ORG
VALUE DC
ORG
DC.W
LENGTH EQU
ORG
BUFFER DS.B
TEMP
DS.B
ORG
MOVE.L
MOVEA
LOOP
MOVE.B
SUBQ.B
BNE
RSEG
BEGIN MOVE.B
END
CH4-6.SRC *********************
$1000
#100,D5
100
$2000
#COUNT,D5
$0D
define a symbol
$3000
set origin
5,-1
word size default
5,-1
byte size constants
'JOHN'
ASCII string
CR,0
CR is a symbol
$4001
15
decimal constant
$5000
'a'
80
$6000
LENGTH
1
$7000
#LENGTH,D1 use R1 as counter
#BUFFER,A1 A1 points to buff
#0,(A1)+
clear location
#1,D1
done?
LOOP
no: clear again
EPROM
#44,D5
F4-8
TM-62
Linker Operation
P ROG .H EX
Le g en d :
F ILE 1 . OB J
FIL E 2 .O BJ
Ut i lit y pr o g r a m
X LIN K
F ILE 3 . OB J
Us er f ile
F ILE 4 . O BJ
PRO G. MA P
( a)
O pt i o ns
f o llo w
Co m m an d
CPU
In p ut
f ile s
A bso l u t e
o u t p u t f i le
f o r m at t e d
in S- r ec o r d s
L ist in g
f ile
XL IN K 6 8 K F IL E1 .OBJ FIL E2 .O BJ FIL E3 .O BJ FIL E4 .OB J / O= PROG.H EX M= PRO G.M A P
( b)
F4-10
TM-63
User Mode vs. Supervisor Mode
Feature
User Mode
Supervisor Mode
Clearing S-bit in SR
Exception processing
0
1
Active stack pointer
USP
SSP
Other stacks using
A0 - A6
USP, A0-A6
Entire SR
CCR bits only
Entire SR
Entire SR
Entered by
FC2 =
SR access
Read:
Write:
Instructions available
All except
All
AND #data,SR
EOR #data,SR
MOVE <ea>,SR
MOVE USP,An
MOVE An,USP
OR #data,SR
RESET
RTE
STOP
T6-1
TM-64
Changing Between
User Mode and Supervisor Mode
T ra ns it io n m a y o cc ur o n ly
d ur in g ex ce pt io n p r o ce ssing
U ser
M o de
Su pe rv isor
Mo d e
T ran sit io n m ay o ccu r
t h r o u gh f o u r in st r uc t io n s:
MOV E t o SR
A N DI t o SR
EOR t o SR
RT E
F6-1
TM-65
Exception Tree
Exc ep t ion
Ext e r n al
Int e r na l
In t er r u p t
Use r
V e ct o r
A ut o
V e ct o r
Exec ut io n
Er r o r
In st r uc t io n
Bu s
Er r o r
Re s e t
T RA P
T RA PV
CH K
T r a ce
D iv id eb y - ze r o
Pr iv ileg e
V io la t io n
A - lin e o r
F- line
Em ula t io n
A d dr ess
Er r o r
Ille g al
In s t r uc t io n
F6-2
TM-66
Exception Processing Sequence
St art e xc ep t ion
Ma ke in t ern al
c op y of SR
S = 1, T = 0
Int err up t
?
y es
Up d at e in t e rru p t
m a sk lev el
no
Ob t a in v ec t o r
n um be r
V ec t o r a dd re ss =
ve ct or n u m b er x 4
Pus h PC an d c o pie d
SR o n t o st ac k
( V ec t o r ad d re ss)
-----> PC
C on t in u e e xe cu t io n
F6-3
TM-67
Stack Frame for Exceptions
(except bus error and address error)
Hig h -Me m o r y
15
0
n+6
SP ( old )
n+4
Pro g r am Co u nt e r ( lo w )
n+2
Pr o g ra m C o un t e r (h ig h )
n
St at u s Re g ist e r
SP ( n ew )
Lo w -Mem or y
F6-4
TM-68
Exception Vector Address
A3 1
A 10
all ze r o s
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
V7
V6
V5
V4
V3
V2
V1
V0
0
0
4
4
1
4
4
4
2
4
3
V e ct o r n u m b er
F6-5
TM-69
Reset and Exception
Vector Assignments
Vector
Number
0
Hexadecimal
Address
000
Assignment
–
004
Reset PC†
Reset SSP†
2
008
Bus Error
3
00C
Address Error
4
010
Illegal instruction
5
014
Divide-by-zero
6
018
CHK instruction
7
01C
TRAPV instruction
8
020
Privilege violation
9
024
Trace
10
028
Line 1010 emulator
11
02C
Line 1111 emulator
12
030
(reserved)
13
034
(reserved)
14
038
Format error (68010)
15
03C
Uninitialized interrupt vector
16-23
040-05C
(reserved)
24
060
Spurious interrupt††
25
064
Level 1 interrupt autovector
26
068
Level 2 interrupt autovector
27
06C
Level 3 interrupt autovector
28
070
Level 4 interrupt autovector
29
074
Level 5 interrupt autovector
30
078
Level 6 interrupt autovector
31
07C
Level 7 interrupt autovector
32-47
080-0BC
TRAP instruction vectors†††
48-63
0C0-0FC
(reserved)
64-255
100-3FC
User interrupt vectors
† The reset vector is four words and resides in the supervisor program (SP)
space. All other vectors reside in the supervisor data (SD) space.
†† The spurious interrupt vector is taken when there is a bus error during an
interrupt acknowledge cycle.
††† Trap #n uses vector number 32 + n. See Table 6-5.
T6-2
TM-70
Exception Grouping and Priority
Group
Exception
Processing
0
Reset
Address Error
Bus Error
Exception processing begins
within two CPU cycles
1
Trace
Interrupt
Illegal Instruction
Privilege Violation
Exception processing begins
before the next instruction
2
TRAP, TRAPV
CHK
Zero Divide
Exception processing begins by
normal instruction execution
T6-3
TM-71
Traps vs. Subroutines
Features
Traps
Subroutines
Initiated from
user mode or
supervisor mode
user mode or
supervisor mode
Routine executes in
supervisor mode
user mode or
supervisor mode
PC and SR
PC
system stack
user stack or
system stack
RTE
RTS
user mode or
supervisor mode
user mode or
supervisor mode
Registers saved
Registers saved on
Routine ends with
Privilege state after is
T6-4
TM-72
Vector Assignments for
TRAP Instructions
Instruction
Vector
Number
Vector
Address
TRAP #0
32
$000080
TRAP #1
33
$000084
TRAP #2
34
$000088
TRAP #3
35
$00008C
TRAP #4
36
$000090
TRAP #5
37
$000094
TRAP #6
38
$000098
TRAP #7
39
$00009C
TRAP #8
40
$0000A0
TRAP #9
41
$0000A4
TRAP #10
42
$0000A8
TRAP #11
43
$0000AC
TRAP #12
44
$0000B0
TRAP #13
45
$0000B4
TRAP #14
46
$0000B8
TRAP #15
47
$0000BC
T6-5
TM-73
Stack Frame for
Bus Error and Address Error
Hig h - Me m o ry
15
0
n+1 4
SP (o ld )
n+1 2
Prog r a m Co u nt er ( lo w )
n+1 0
Pr o g ram Co u n t e r ( h ig h)
n+ 8
St at us Re g ist e r
n+ 6
In st ruc t io n Re g is t e r
n+ 4
Ac ce s s ad d r es s ( lo w )
n+ 2
A c c ess a dd re ss (h ig h )
n
SP ( ne w )
A cc es s t yp e
Lo w -M em o ry
( a)
15
5
u n de f in ed
4
3
2
1
0
R/ W I/ N FC 2 FC1 FC 0
142 4 3
Fu nc t io n C o de
I/ N
0 = in s t r uc t io n
1 = n o t a n in st r u ct io n
R/ W
0 = w r it e c yc le
1 = re ad cy cle
( b)
TM-74
F6-6
TM-75
Power-on Reset Timing
...
CL K
+5V
Vcc
0V
> 100 ms
RESET
H A LT
< 4 c lo c ks
1
B u s Cyc les
SS P H
SSP L
PC H
PC L
14 42 44 3 1 44 24 43
In it ializ e SSP
In it ializ e P C
144244
E xec ut e 1 st
in st ru c t io n
L eg e nd :
1
Int er na l st art -u p t im e
A ll c o nt r o l sig n als in ac t ive .
D at a b us in r ea d m o d e
Bus s t at e u n kn ow n
Bu s c y cle ( m e m o ry r e ad o r m em o r y w r it e )
F6-7
TM-76
A Switch as an Input Device and an
LED as an Output Device
+5 V
Re sist o r
22 0 Ω
LED
Sw it c h
W ir e
Sw it c h
OPEN
CL OSED
L ED
OF F
ON
Sw it c h
OPEN
CL OSED
L ED
?
?
( a)
+5 V
L ED
Sw it c h
Re sis t o r
22 0 Ω
Co m p u t e r
( b)
F7-1
TM-77
Interface to Switches and LEDs
(conceptual)
D at a Bu s
Ad d re ss Bus
6 800 0
0
0
C
0
0
0
L ED # 7
D15
D1 5
D14
D1 4
D13
D1 3
A23
A22
D12
A21
A20
D11
A19
A18
A17
D10
A16
A15
D8
A14
A13
A12
A11
A10
D9
0
C
REA D SWIT C HES
0
A9
A8
A7
A6
A5
A4
A3
A2
0
0
0
+5 V
A1
UD S
AS
R/ W
A2 3
A2 2
D1 2
A2 1
A2 0
D1 1
A1 9
A1 8
A1 7
D1 0
A1 6
A1 5
D8
A1 4
A1 3
A1 2
D9
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
L ED # 0
WRIT E LED S
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
U DS
AS
R/ W
D T A CK
Co n t ro l Bu s
F7-2
TM-78
+5 V
Timing for MOVE.B $00C000,D0
CPU clo ck :
Op co d e
f et ch
Hig h- w o rd o f
a d dr ess
( $0 000 )
Lo w - w o rd o f
ad d re ss
( $ C0 0 0 )
Me m o ry
lo ca t io n
$ 0 0 C0 0 0
Mem or y
r e ad
M em o ry
r e ad
Me m o r y
r ea d
M em or y
r e ad
123
One clo ck
p er io d
t im e
t hre e - st a t e
b uf f ers e na b led
S0
S1
S2
S3
S4
S5
S6
CL K
S7
D a t a f r o m sw it ch e s
lat ch ed int o r eg ist er
D 0 , b it s 0 -7 , a t
t h e st ar t of S7
F C0 -FC2
A1 - A 2 3
$ 0 0 C0 0 0
AS
UDS
LD S
R/ W
DT A CK
D 8 -D1 5
sw it c h d at a
D 0 -D7
F7-3
TM-79
Example of Partial Decoding
0
0
C
A 23
A 22
A 21
A 20
A 19
A 18
A 17
A 16
A 15
A 14
A 13
A 12
UDS
AS
R/ W
A 23
A 22
A 21
A 20
A 19
A 18
A 17
A 16
A 15
A 14
A 13
A 12
UDS
AS
R/ W
0
0
REA D SW IT CH ES
C
W RIT E L ED S
( a)
A d dr e ss:
A23
0
A19
0
0
0
0
0
A15
0
0
0
0
1
A1 1
1
0
0
X
C
A7
X
X
X
X
X
A3
X
X
X
X
X
A0
X
X
0
XXX0
(b )
F7-5
TM-80
Flowcharts for
Program-Conditional I/O
In pu t F lo w c h ar t :
NO
O ut p ut Flo w c h a r t :
E nt er
En t e r
Rea d D e v ic e
S t a t u s Flag
Re ad D ev ice
S t at us F la g
D e vic e
Re ad y
?
NO
De v ic e
Rea d y
?
Y ES
YE S
In p ut
Ou t p u t
D at a
Da t a
Clea r Flag
Cle ar Fla g
Ex it
Exit
( a)
(b )
F7-7
TM-81
Keyboard Interface
D a ta Bu s
D8
Ke yb o ard
KBD
D A TA
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D1 5
D1 4
D1 3
D1 2
D1 1
D1 0
D9
D8
F L AG
K EYH IT
S
Q
R
REA D K BD D A T A
REA D KBD ST A T U S
( a)
Da t a ar e st o re d
in lat ch an d
f la g is se t
A k ey is
pr ess e d
KBD DA T A
V alid D at a
K EYH IT
( b)
F7-6
TM-82
Interface Using a
Peripheral Interface IC
Da t a B us
CPU
A d dr ess Bu s
Co nt ro l Bus
Pe r ip h e r al In t er f a ce IC
A1
A0
R/ W
A d d r e ss
D ec o din g
CS
Re ad
W rit e
St at us
C o nt ro l
e t c.
etc .
e t c.
etc .
In p u t
Ou t p u t
Pe ri p h er a l Dev ic e
F7-9
TM-83
Program Execution
Without Interrupts or
With Interrupts
t im e
M ain P r o g r am
( a)
Int er r up t - le v el
ISR
exe c u t io n
*
Base - lev el
exe c u t io n
M ain
ISR
**
*
ISR
**
Ma in
*
**
M ain
*
**
Ma in
Int er r up t
Ret ur n f r o m int e r r up t in s t r uc t io n
( b)
F7-11
TM-84
Interrupt Priority Conditions on IPL2, -IPL1, and -IPL0
Signal
IP2
IP1
IP 0
Interrupt
Condition
Maskable
Priority
1
1
1
0
No interrupt
-
-
1
1
0
1
Interrupt
Yes
Lowest
1
0
1
2
Interrupt
Yes
(etc.)
1
0
0
3
Interrupt
Yes
(etc.)
0
1
1
4
Interrupt
Yes
(etc.)
0
1
0
5
Interrupt
Yes
(etc.)
0
0
1
6
Interrupt
Yes
(etc.)
0
0
0
7
Interrupt
No
Highest
T7-3
TM-85
Autovectors for
Automatic IACK Cycles
Interrupt
Vector Address
(Autovector)
0
-
1
$000064
2
$000068
3
$00006C
4
$000070
5
$000074
6
$000078
7
$00007C
T7-4
TM-86
Vector Addresses for
User IACK Cycles
Vector Number
Vector Address
0
$000000
1
$000004
2
$000008
etc.
etc.
255
$0003FC
T7-5
TM-87
Interrupt Circuitry
+5 V
74 07
1 0K
V PA
680 00
7 4 HC 1 3 8
A3
A2
A1
N o n - Mas k ab le
In t er r u p t ( NM I)
C
B
A
+5 V
+5 V
IN T 7
IN T 6
7 4 H C1 4 8
7
6
5
4
3
2
IN T 5
IN T 4
IN T 3
IN T 2
IN T 1
+5 V
E1
E2
E3
A2
A1
IPL 2
IPL 1
A0
IPL 0
7
6
5
4
3
2
1
0
IA C K 7
IA C K 6
IA C K 5
IA C K 4
IA C K 3
IA C K 2
IA C K 1
7 4 H C1 3 8
FC 2
FC 1
FC 0
C
B
A
7
6
5
4
3
IA ( In t e rr up t Ac k n o w led g e )
S P ( Sup e r v is o r P r og r a m )
S D ( Su p e r v is o r Da t a )
E1
E2
E3
2
1
0
UP ( Us er P ro g ram )
UD ( Us er D at a)
+5 V
1
0
AS
E1
F7-12
TM-88
Bus Connections for DMA Interface
Da t a Bu s
CPU
A dd re ss Bu s
C o nt ro l Bu s
Me m o r y
DMA
Co n t r o lle r
Dev ic e
F7-13
TM-89
Device-to-Memory
Transfer Using DMA
D at a Bu s
A dd re ss Bu s
Co n t r o l Bus
Me m o r y
DMA
Co n t ro l le r
Dev ic e
F7-14
TM-90
68000 Bus Arbitration
Control Signals
68 000
CPU
D MA
Co nt ro lle r
BR
BR
BG
BG
BGA CK
BGA CK
F7-15
TM-91
Bus Arbitration
6 8 0 0 0 CPU
DMA Co n t r ol le r
Re qu e st t he Bus
1 . A ssert b us r e q ue st
( BR = 0 )
Gr an t t he Bus
1 . A sse r t b u s g ran t ( BG = 0 )
A ckn o w le dg e Bus M ast er sh ip
1 . A ssert b us g r a nt
a ck no w le d ge (B GA CK = 0 )
2 . Ne g at e b u s req u e st
( BR = 1 )
Ter m ina t e Bus A rb it r a t io n
1 . Ne g at e b u s gr an t ( BG = 1 )
a nd w a it f o r BGA CK t o be
n e ga t e d
Op er a t e as Bu s Mast e r
1 . Pe r f o r m d at a t r an sf e rs
acc o r d in g t o sam e r u les
t h e CPU u se s
t im e
Rele ase Bu s M ast ersh ip
1 . Ne g at e b u s g ran t
ack no w le d g e ( BGA CK = 1 )
Resu m e N o rm a l Pr o ce ssing
F7-16
TM-92
Timing for Bus Arbitration
t im e
BR
BG
BGA CK
1 2 3
CPU
cy cles
1
4
4
2
4
DM A
cy cles
4
3
1 2 3
C PU
cy cle s
F7-17
TM-93
Block Diagram of the 68KMB
T e rm ina l/
H o st Co m p u t e r
68 000
CPU
Sy st e m
Cloc k
6 8 6 8 1 DUA RT
Re s e t
Cir c uit
Int e r rup t
Circ u it
M isce lla n eo u s
In pu t / Ou t p u t
De vic es
Sy st e m Bu ses
A dd r e ss
D ec od e
Cir c uit
Mo nit o r
EPRO Ms
(1 6 K)
U ser
EPRO Ms
( 1 6 K)
RAM s
( 1 6 K)
Ext e rn al
Int err u p t s
F8-3
TM-94
68000 CPU
14, 49
+5 V
16, 53
15
V cc
G ND
68000
CPU
C LK
+5 V
20
19
21
13
11
12
6
9
7
Co n t r o l
Bu s
8
10
28
27
26
25
24
23
22
18
17
E
V MA
V PA
BR
BG
B G A CK
AS
R/ W
U DS
L DS
D T A CK
F CO
F C1
F C2
IPL 0
IPL 1
IPL 2
B ERR
RESET
H A LT
7 X
1 0 KΩ
A2 3
A2 2
A2 1
A2 0
A1 9
A1 8
A1 7
A1 6
A1 5
A1 4
A1 3
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
52
D1 5
D1 4
D1 3
D1 2
D1 1
D1 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
54
51
50
48
47
46
45
44
43
42
41
40
39
A d d r es s
Bu s
38
37
36
35
34
33
32
31
30
29
55
56
57
58
59
60
61
62
63
D at a
Bu s
64
1
2
3
4
5
F8-4
TM-95
68KMB Clock Circuit
7 4 HC 1 4
1
0 . 0 1 µF
2
1K
10
pF
47 Ω
3
4
5
6
C LK
to
680 00
BA U D CL K
to
686 81
1K
3.68 64
MHz
13
12
F8-6
TM-96
68KMB Reset Circuit
+5 V
1N
9 14
+5 V
1 0K
7 4 HC1 4
9
100 Ω
+
8
11
7 407
10
3
1
2 2 µF
4
2
RESET
to
68 000
H A LT
RESET
F8-7
TM-97
68KMB Interrupt Circuit
M ON IT OR
+
2 2 µF
+5V
7 x
10K
7 4 HC1 4 8
4
IN T 7
Ext er na l
In t e r ru pt s
3
IN T 6
IN T 5
IN T 4
2
1
13
IN T 3
IN T 2
IN T 1
12
11
+5 V
X1 6
10
5
7
6
5
4
3
2
1
0
A2
A1
A0
6
IPL 2
IPL 1
IPL 0
7
9
to
68 000
740 7
E0
GS
13
15
12
14
E1
11
10
5
6
V PA
7 4 H C1 3 8
3
A3
A2
A1
2
1
C
B
A
+5V
7 4 H C1 3 8
f ro m
680 00
3
FC 2
FC 1
FC 0
2
1
C
B
A
+5 V
6
AS
4
5
E1
E2
E3
7
6
5
4
3
2
1
0
6
7
9
10
11
IA
4
SP
SD
5
E1
E2
E3
7
6
5
4
3
2
1
0
7
9
10
11
12
13
IA CK7
IA CK6
IA CK5
IA CK4
IA CK3
IA CK 2
14
15
to
686 81
IA CK1
12
13
14
UP
UD
15
F8-8
TM-98
68KMB Address Decoding
f ro m
68 000
1
A20
A19
A18
A17
A16
A15
A14
UD S
LDS
AS
2
3
4
5
6
7
8
9
11
20
+5 V
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
1 6 L8
O8
O7
O6
O5
O4
O3
O2
O1
19
EPROM 0 U
EPROM 0 L
EPROM 1 U
EPROM 1 L
RA M0 U
RA M0 L
D UA RT
18
17
16
15
14
13
12
9
Vc c
t o EPRO M,
RA M , & D UA RT
c hip se le ct inp u t s
8
D T A CK
t o 6 800 0
7 407
10
GN D
F8-9
TM-99
68KMB Memory Map
FFFFFE
Re f le ct ed
7 M w o rd s
Ex pa ns io n
9 9 2 K w o rd s
200000
1FFFFE
010000
8 M w o rd s
( 1 6 M b y t e s)
00FFFE
D UA RT
00C000
8 K w or d s
( I/ O)
00BFFE
RA M0 U
RA M 0 L
008000
8 K w or d s
( syst e m / u ser )
1 M w o rd s
( 2 M b y t e s)
007FFE
EPROM1 U
EPROM1 L
8 K w or d s
( u ser )
EPROM0 U
EPROM0 L
8 K w o rd s
( MON 6 8 K)
004000
003FFE
000000
F8-10
TM-100
Monitor EPROMs
f r om
68 000
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
2
23
21
24
25
3
4
5
6
7
8
9
10
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
2764A
EPROM
( m o nit or )
D7
D6
D5
D4
D3
D2
D1
D0
f ro m
680 00
EPROM0 U
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
20
2
23
V cc
Vpp
PGM
21
24
25
3
4
5
6
7
8
9
10
CS
GN D
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
2764A
EPROM
( m o nit or )
D7
D6
D5
D4
D3
D2
D1
D0
EPROM0 L
20
17
16
15
13
12
11
CS
28
1
27
t o / f ro m
680 00
22
14
19
18
17
16
15
13
12
11
D7
D6
D5
D4
D3
D2
D1
D0
+ 5V
V cc
Vpp
PGM
OE
f ro m A dd r e ss
De co d e C ir cu it
D15
D14
D13
D12
D11
D10
D9
D8
18
+ 5V
OE
f ro m A d dr ess
D ec od e Cir cu it
19
GN D
28
1
27
22
14
F8-12
TM-101
User EPROMs
f ro m
6 800 0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
2
23
21
24
25
3
4
5
6
7
8
9
10
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
2764A
EPROM
(u se r )
D7
D6
D5
D4
D3
D2
D1
D0
f ro m
680 00
EPROM 1 U
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
20
2
23
Vc c
Vp p
PGM
21
24
25
3
4
5
6
7
8
9
10
CS
GND
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
2764A
EPROM
( use r )
D7
D6
D5
D4
D3
D2
D1
D0
EPROM1 L
20
17
16
15
13
12
11
5
4
3
2
1
0
CS
28
1
27
t o/ f ro m
68 000
22
14
19
18
17
16
15
13
12
11
D7
D6
D5
D4
D3
D2
D1
D0
+5 V
Vc c
Vp p
PGM
OE
f ro m A d dr ess
D ec od e Cir cu it
D1
D1
D1
D1
D1
D1
D9
D8
18
+5 V
OE
f ro m A d d r ess
D ec o de Cir cu it
19
GND
28
1
27
22
14
F8-13
TM-102
System/User RAM
f ro m
6 800 0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
R/ W
f r o m A d dr ess
D ec od e Cir cu it
f ro m
6 800 0
RA M0 U
A1 3
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
R/ W
f ro m A d dr e ss
D ec od e Cir cu it
RA M0 L
2
23
21
24
25
3
4
5
6
7
8
9
10
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
27
W
20
CS
2
23
21
24
25
3
4
5
6
7
8
9
10
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
27
W
20
CS
6264
RA M
D7
D6
D5
D4
D3
D2
D1
D0
19
18
17
16
15
13
12
11
D1
D1
D1
D1
D1
D1
D9
D8
5
4
3
2
1
0
+5V
Vcc
28
26
OE
GND
6264
RA M
D7
D6
D5
D4
D3
D2
D1
D0
t o / f ro m
68 000
22
14
19
D7
D6
D5
D4
D3
D2
D1
D0
18
17
16
15
13
12
11
+5V
Vcc
28
26
OE
GND
22
14
F8-14
TM-103
68681 DUART
J3
D B2 5 S
30
25
t o / f ro m
68 000
D7
D6
D5
D4
D3
D2
D1
D0
f r om A d d r e ss
D e co d e Cir c uit
24
17
23
18
22
19
D7
D6
D5
D4
D3
D2
D1
D0
IN T 2
IA CK 2
8
9
6
5
3
1
21
37
RESET
R/ W
D T A CK
31
T1 I
T1 O
R1 0
R1 I
12
Rx DA
2
3
14
2
T e r m ina l/
H os t Co m p u t e r
7
68681
DUA RT
MA X
232
11
10
10
9
TxD B
Rx DB
RS4
RS3
RS2
RS1
T2 I
T2 O
R2 0
R2 I
J8
D B2 5 S
7
3
8
2
+5V
1
+
4 X
1 0 µF
+
IRQ
IA CK
C1 +
Vcc
C1 -
V+
7
C2 +
V-
+
2
6
4
5
+
15
C2 -
CS
G ND
J1
32
f r o m Clo ck
Cir cu it
BA UD
CL K
C LK/ X1
33
X2
40
+ 5V
V cc
20
O p t io n al
Ser ia l
Por t
16
3
35
D UA RT
11
TxD A
34
RESET
R/ W
D T AC K
A4
A3
A2
A1
t o / f ro m
In t e r r u pt Cir cu it
16
O P7
O P6
O P5
O P4
O P3
O P2
O P1
O P0
G ND
IP5
IP4
IP3
IP2
IP1
IP0
15
8
26
7
14
9
27
3
13
17
28
4
12
11
29
5
38
14
39
15
2
16
36
12
4
13
7
Mis c ellan e ou s
Inp u t / Ou t pu t
D ev ic e s
6
+5V
20
10
F8-15
TM-104
Expansion to 6800 Peripherals
J2
1
D7
D6
D5
D4
D3
D2
D1
D0
t o / f ro m
680 00
2
3
4
5
6
7
8
11
A 16
14
A3
A2
A1
15
13
RESET
V PA
E
R/ W
t o / f ro m
In t e r ru pt
Circu it
Exp an sion t o
6 8 0 0 Pe rip he r a ls
16
18
17
19
12
IN T3
SD
9
+5V
20
10
2 0 - pin
h ea de r
F8-16
TM-105
68681 Interface to
LEDs and Switches
(I/O Board #1)
686 81
DU ART
J1
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
8 ×
220 Ω
7 4 LS2 4 4
15
8
17
3
26
7
15
5
14
9
13
7
27
3
11
9
13
17
8
12
28
4
6
14
12
11
4
16
29
5
2
18
+5 V
1, 19
20
+5V
10
+5 V
IP5
IP4
38
14
39
15
2
16
36
12
4
13
7
6
IP3
IP2
IP1
IP0
6 ×
1 0 kΩ
F9-3
TM-106
Interface to Switches and
7-Segment LED
(I/O Board #2)
686 81
DU ART
J1
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
+5 V
7 4 LS2 4 4
7 ×
22 0 Ω
15
8
17
3
26
7
15
5
1
14
9
13
7
13
27
3
11
9
10
13
17
8
12
8
28
4
6
14
7
12
11
4
16
2
29
5
2
18
11
20
14, 3
a
a
b
c
f
e
f
b
g
d
c
e
d
g
MA N 7 2 A
7 -s eg m e nt
co m m o n
an od e LED
1, 19
+5V
10
+5 V
IP3
IP2
IP1
IP0
2
16
36
12
4
13
7
6
4 ×
1 0 kΩ
F9-4
TM-107
4-Digit 7-Segment Display
(I/O Board #3)
+5 V
6 86 8 1
J1
18
V cc
O P2
O P1
O P0
28
5
4
12
11
13
29
5
12
20
8 ×
47 Ω
DA TA
CL OCK
a
ENA BL E
b
c
MC1 4 4 9 9
+5 V
d
10
e
6
0 .0 1 5
µF
f
O SC
g
9
GN D
D4
7
h (d p )
D3
8
D2
10
4 × MA N 4 7 4 0 A
4
14
3
13
2
8
1
7
17
6
16
1
15
2
14
4
aa
a
bb
cc
f
f
b
f
f
b
d
dp
dp
dp
4,12
4 ,1 2
4 ,1 2
4 ×
2 N3 9 0 4
11
F9-6
TM-108
c
e
d
dp
b
g
c
e
d
dp
a
g
c
e
d
g
a
g
c
e
ff
4 ,1 2
D1
b
g
dd
ee
a
MC14499 Timing
t im e
ENA BL E ( OP0 )
CL OCK ( OP1 )
D AT A ( OP2 )
d1
d2
d3
d4
d1 9
d20
F9-7
TM-109
MC14499 Digit and Bit Sequence
t im e
Bit N o .
1
2
3
4
5
6
7
8
9
10
11
12
13 14
15
16
17 18
19
20
1 4 2 4 3 1 42 4 3 1 4 2 4 3 1 4 2 4 3 1 4 2 4 3
De cim a l
Poin t s
Dig it
1
D ig it
2
D igit
3
Dig it
4
F9-8
TM-110
8-Digit 7-Segment Display
(I/O Board #4)
D IGIT
SEG
MC1 4 4 9 9
DA TA
CL OCK
EN ABL E
D IGIT
SEG
MC1 4 4 9 9
h
D A TA
C LO CK
EN AB LE
h
et c.
F9-9
TM-111
68681 Input Expansion
Using 74LS165s
Ex t e r n al Inp u t s
J1
L SB
6 868 1
D UA RT
MSB
20
+ 5V
10
6
IP0
7
6
9
4
5
H
G
3
F
D AT A
O UT
G ND
8, 1 5
O P0
12
11
29
5
13
D
12
C
11
B
Vcc
16
DA T A 1 0
IN
L O AD
7
6
A
7 4 L S1 6 5
+ 5V
O P1
14
E
1
nc
CL K
2
5
H
9
4
G
3
F
D AT A
O UT
G ND
8, 1 5
14
E
13
D
12
C
11
B
A
DA T A
IN
7 4 L S1 6 5
Vc c
16
+5V
L O AD
7
1
10
CL K
2
etc .
nc
F9-10
TM-112
6821 Interface to the 68000
(I/O Boards #5 & #6)
J2
1
26
2
27
D7
D6
3
28
4
29
5
30
PIA
CA 2
CA 1
D3
D4
PA 7
D3
PA 6
D2
PA 5
D1
PA 4
D0
PA 3
31
6
D2
7
32
8
33
PA 2
23
9
SD
A16
CS2
24
11
CS1
1
7 4 HC 0 0
2
RESET
R/ W
E
18
PA 0
PB 7
3
PB 6
6
5
13
34
19
21
17
25
12
38
14
37
PB 5
RESET
R/ W
E
IRQA
A3
A1
PA 1
9
8
7
6
5
4
3
2
CS0
INT 3
A2
40
22
+5 V
4
VPA
39
D5
D4
D0
D7
D6
D5
D1
6 821
nc
IRQB
15
35
16
36
PB 4
PB 3
PB 2
PB 1
PB 0
17
16
15
14
13
12
11
10
RS1
RS0
20
+5V
+5 V
10
20
1
V cc
CB2
CB1
19
18
GN D
F9-11
TM-113
Keypad Interface to the 6821
(I/O Board #5)
68 21
PIA
2
PA 0
3
PA 1
4
PA 2
PA 3
5
J
6
H
G
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
N
PA 4
7
M
PA 5
8
L
PA 6
9
K
PA 7
Gra yh ill PN 8 8 BA 2
F9-12
TM-114
Output to a MC1408L8 DAC
(I/O Board #6, 1 of 4)
M C1 4 0 8 L 8
68 21
9
5
8
6
7
7
6
8
PA 7
PA 6
PA 5
D7
V r ef +
D6
5
9
4
10
3
11
2
12
PA 3
PA 2
PA 1
PA 0
10 0 Ω
15
+5 V
16
D3
1
D2
4 .7 k Ω
nc
D1
+ 1 2 V -1 2 V
D0
7
IO
V CC
4
2
6
VO
3
COMP
8
L M3 0 1
1
2
1 5 pF
1 kΩ
V r ef -
4
13
1 50 Ω
14
D5
D4
PA 4
+5V
1 kΩ
GND
V EE
3
3 3 pF
-1 2 V
F9-13
TM-115
Low-Pass Filter and Audio Output
(I/O Board #6, 2 of 4)
0 .0 4 4 µ F
VO
( f ilt er ed )
2 .4 k Ω
+12V -12V
+ 1 2 V -1 2 V
7
1 .2 k Ω
7
4
2
1 .2 k Ω
6
1
L M3 0 1
( lo w - pa ss
f ilt e r )
5 kΩ
33 pF
2 5 µF
+
3
8
0 .0 2 2 µ F
4
2
6
3
VO
A ux ilia r y
Jack
8
1
LM 3 0 1
( vo lt ag e
f o llo w e r )
Sp ea k e r
3 3 pF
F9-15
TM-116
Interface to ADC0804
Analog-to-Digital Converter
(I/O Board #6, 3 of 4)
AD C0 8 0 4
682 1
C B2
C B1
V cc
19
18
3
5
1
2
WR
Vin ( + )
IN TR
17
11
16
12
15
13
14
14
13
15
12
16
11
17
10
18
+5V
6
Di f f e re nt ial In p ut s
V in( - )
10 k Ω
t r im p o t
( t r an sd uc er)
7
CS
RD
Vr ef
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
20
D7
D6
D5
D4
D3
D2
D1
D0
C LK R
9
nc
19
1 5 kΩ
CL K IN
4
1 5 0 pF
D GN D
A GN D
10
8
F9-16
TM-117
Timing for ADC0804 Conversions
Clea r
INT R
St a r t o f
Co n ve rsio n
En d o f
Co nv er sion
C le ar
IN TR
St ar t Ne xt
Co nv er sio n
WR
≈ 1 0 0 µs
IN T R
F9-17
TM-118
Microphone Input to the ADC0804
(I/O Board #6, 4 of 4)
1 kΩ
1%
VA
100 k Ω
1%
VB
1 kΩ
1 0 kΩ
+
1 0 µF
+ 1 2 V -1 2 V
47 Ω
7
1 kΩ
1%
Mic rop h o ne
200 Ω
6
8
4
2
6
2 2 kΩ
3
1
47 Ω
7
4
2
1 0 0 kΩ
1%
+ 1 2 V -1 2 V
3
+5V
LM 3 0 1
( p r e -am p )
LM 3 0 1
(a m p )
8
1
2 2 kΩ
33 pF
33 pF
+5 V
1N914
1 .2 k Ω
0 .0 4 4 µF
L F3 9 8
( sa m p le an d h o ld )
2 .4 k Ω
+12V
1 .2 k Ω
-1 2 V
18 k Ω
+ 1 2 V -1 2 V
V
7
5 . 6 kΩ
C
8
3
5
3
0 .0 2 2 µ F
1
+5 V
4
6
8
20
V cc
1
4
2
A DC0 8 0 4
L M3 0 1
( lo w -p a ss f ilt e r )
V
D
6
7
0 .0 0 1 µ F
6
V in (+ )
7
33 pF
V in (- )
1
CS
RD
2
6 821
CB2
CB1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
19
3
18
5
WR
IN T R
17
11
16
12
15
13
14
14
13
12
15
11
17
10
18
16
TM-119
V re f
CL K R
D7
D6
D5
D4
D3
D2
D1
D0
9
nc
19
15 k Ω
CL K IN
4
1 50 pF
D GND
A GND
10
8
F9-19
TM-120
Sample-and-Hold Waveforms
1 0 0 µ s m in im un
Sign a l a t V C
Sig n al at V D
V o lt a ge
T im e
F9-20
TM-121
68000-Family Features
48-pin
68008
52-pin
68008
68000
68010
68020
68030
68040
8
8
16
16
32
32
32
Address Bus (bits)
20
22
24
24
32
32
32
Data Cache (bytes)
–
–
–
–
–
256
4096
Instruction Cache
(bytes)
–
–
–
–
256
256
4096
On-Chip Memory
Management
No
No
No
No
No
Yes
Yes
On-Chip FloatingPoint Unit
No
No
No
No
No
No
Yes
Data Bus (bits)
T10-1
TM-122
Comparison of Five Recent
Microprocessors
†
68040
Company Motorola
80486
PowerPC
Pentium
Alpha
21064
Intel
IBM/Motorola
Intel
DEC
Introduced
1989
6/91
4/93
3/93
2/92
Architecture
CISC
CISC
RISC
CISC
RISC
Width (bits)
32
32
32
32
64
Registers
(general/FP)
16/8
8/8
32/32
8/8
32/32
No
No
Yes
Yes
Yes
10.8 x
11.7
not
available
11 x 11
17.2 x
17.2
15.3 x 12.7
Transistors
(millions)
1.2
1.2
2.8
3.1
1.68
Clock (MHz)
25
50
80
66
200
SPECint 92††
21
27.9
85
67.4
130
SPECfp 92††
15
13.1
105
63.6
184
Peak Power
(Watts)
6
5
9.1
16
30
$233
$432
$557
$898
$505
Multiprocessing
Support?
Device Size (mm)
Price ($US/1000
units)
† Source: IEEE Spectrum, December 1993, p. 21
†† Integer and floating-point performance benchmarks
T10-10
TM-123