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CIGRÉ Canada
Conference on Power Systems
Halifax, September 6- 8, 2011
Control and Performance of
a Modular Multilevel Converter System
Wei LI, Luc-Andre GREGOIRE, Jean BÉLANGER
OPAL-RT Technologies (CAN)
SUMMARY
The Modular Multilevel Converter (MMC) system has many advantages over conventional
voltage source converters and therefore can be used in dc power transmission, micro grid, or
renewable energy applications. While MMC’s distinctive topology offers many new features,
it also necessitates a sophisticated controller to deal with extra control requirements. This
paper presents a control scheme with multiple control objectives required by MMC, i.e. active
and reactive power control, dc voltage control, sub-module capacitor voltage control and
balancing, circulating current eliminating, and zero-sequence current eliminating. The system
is modeled in an electromagnetic transients program, RT-LAB, and its dynamic performance
is evaluated by time-domain studies using a real-time simulator, eMEGAsim. The results
show the multiple control objectives are fulfilled and the system has fast response to control
command and system dynamics.
KEYWORDS
High-voltage dc (HVDC), Modular Multilevel Converter (MMC), real time simulation,
voltage source converter (VSC).
wei.li@opal-rt.com
1. INTRODUCTION
The modular multilevel converter (MMC) is a new type of voltage source converter (VSC) for
medium or high-voltage dc power transmission and other applications such as connecting renewable
resources to main grids, Figure 1. Compared to conventional 2-level VSC system, the topology of
MMC offers some advantages and unique features:
1. Its AC voltage has low harmonic contents due to harmonic cancellation among multiple submodules (SM), and therefore the need for a filter is eliminated.
2. The currents in MMC arm and DC link are continuous, and the DC link capacitor can be omitted;
3. The PWM carrier frequency is low, and therefore losses in power electronic switches are reduced.
4. In a DC link short circuit fault, only some of SM capacitors are discharged and the discharging
current is limited by the protection choke in the arms. Therefore, the system recovers fast.
5. The system can remain operating for a certain period even when a few SM are out of order.
Nevertheless, MMC unique topology has some further control requirements in addition to those of
conventional VSC and therefore requires a more sophisticated controller. For example, the MMC
controller needs to balance SM capacitor voltages and eliminate circulating current. MMC systems are
discussed in literature [1-5]. However, little literature provides comprehensive analyses of the system
and control schemes adequately fulfilling the extra requirements of the MMC topology.
This paper presents an MMC control scheme with multiple control objectives, and its performances
are validated when the system is operating in the steady state, transients and faults. Modeled in an
electromagnetic transients program, RT-LAB, the MMC system is evaluated by time-domain studies
using the eMEGAsim real time simulator by OPAL-RT Technologies.
(a) PWM Reference signal n (solid) and interleaved carriers (dotted)
1
0
-1
0.02
0.03
0.04
(b) 1st gating signal N1 (solid) and its dc & fundamental components (dotted)
1
0.5
0
0.02
0.03
0.04
(c) sum of gating signals ΣNi (solid) and its dc & fundamental components (dotted)
1
0.5
0
0.02
Figure 1 MMC topology
time(s) 0.04
0.03
Figure 2. Phase-shifted multicarrier PWM method
2. MMC SYSTEM ANALYSES
A SM Voltage and multicarrier PWM Strategy
In MMC, each SM is a two-terminal device which consists of a half IGBT bridge and a capacitor,
Figure 1. Depending on its gating signals, the SM terminal voltage is either equal to its capacitor
voltage or zero, and can be expressed as (1), where Vsm-i, Ni, and Vcap-i are terminal voltage, gating
signal of upper-gate, and capacitor voltage of i-th SM respectively. Ni takes the value of either 1 or 0.
The gating signal of lower-gate is the complimentary of Ni. To simplify the analyses, conducting
voltage drop on IGBT and diode, and dead-time between ON gating-signals on the upper and lower
gates are ignored here.
Vsm-i = Ni*Vcap-i
(1)
In one arm of MMC, to synthesize a multi-level voltage with the fundamental component equal to a
sinusoidal reference, the SM gating signals are achieved by pulse width modulation (PWM), i.e.
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comparison of the reference to multiple carrier signals. There are two main categories of multicarrier
PWM techniques, namely the carrier disposition method where the carrier signals are shifted in
magnitude, and the sub-harmonic method where the carrier signals are shifted in phase. There are
several implementations in either category. A discussion of the characteristics and advantages of each
implementation is provided in [6].
Generally, the sub-harmonic method has the advantage of lower harmonic in AC voltage and current.
Therefore, in this paper, the phase-shifted multicarrier technique is used to generate SM gating signals,
Figure 2. For an MMC with k number of SM in each arm, the triangle carrier signals are evenly
interleaved, i.e. a 2π/k phase shift between every two consecutive carriers. Usually in steady states, the
PWM reference signal, ni, contains mainly a fundamental sinusoidal and a dc component. In frequency
domain, the outcome gating signals Ni have components as in (2), where the first harmonic band is
around the carrier frequency.
Ni = 0.5 + ni /2 + harmonics
(2)
When in one arm the reference signals, ni, are all same, the sum of total PWM signals has equal DC
and fundamental components as each single signal in pu, while majority harmonics are cancelled by
each other. The frequency of the first harmonic band is pushed to k times the carrier frequency.
Since harmonic effect is negligible over one cycle, (2) is reduced to (3). In the rest of this paper, Ni is
no longer a Boolean variable but takes a real value between 0 and 1. Then (1) gives the DC and
fundamental components of the SM terminal voltage.
Ni = 0.5 + ni /2
(3)
B MMC Currents
One distinctive characteristic of MMC is that its arm currents are continuous. Therefore, a DC
capacitor becomes unnecessary. However, there are circulating paths that currents could circulate
within the three phases of an MMC. The circulating current will not affect AC or DC side of the
converter. However, if not controlled, it could increase the current magnitude flowing through SM and
raise a risk of damaging the power electronic switches in SM.
The phase current, arm current, and DC link current in an MMC can be broken up into several
components, given in (4), (5), and (6), respectively, Figure 3. In the equations, iupac-u and ilowac-u are
AC components of phase-u currents contributed from upper and lower arms respectively, iup0-u and
ilow0-u are zero-sequence components, idc-u is DC-link current which carries DC power and passes
through phase-u, and icirc-u is circulating current which passes through phase-u, where u=a, b, or c.
iu = iupac-u+iup0-u+ilowac-u+ilow0-u, where u=a, b, or c;
(4)
iup-u = iupac-u+iup0-u+idc-u+icirc-u, ilow-u = −ilowac-u−ilow0-u+idc-u +icirc-u, where u=a, b, or c;
(5)
I dc+ =
∑ (i
u =a ,b ,c
dc −u
+ iup 0−u ) , I dc− =
∑ (i
u = a ,b ,c
dc−u
− iup 0−u ) .
(6)
A good control scheme will have to achieve (i) equal phase current contribution from upper and lower
arms, i.e. iupac-u = ilowac-u; (ii) minimizing zero-sequence current, i.e. iup0-u= ilow0-u = 0; (iii) equal dc
link current contribution from the three phases, i.e. idc-a=idc-b=idc-c=Idc/3; and (iv) minimizing
circulating current, i.e. icirc-u =0. Therefore, (4), (5), and (6) are reduced to (7), (8), and (9)
respectively.
iu = 2*iupac-u=2*ilowac-u, where u=a, b, or c;
(7)
iup-u = iupac-u+idc-u=iu/2+ Idc/3, ilow-u = −ilowac-u +idc-u =−iu/2+ idc/3, where u=a, b, or c;
(8)
I dc + = I dc − =
∑ (i
u =a ,b ,c
dc −u
).
(9)
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Figure 4 dq control of active and reactive powers
Figure 3 current break-up components in MMC
Figure 5 DC link voltage control
C Differential Equations in MMC
The arm current in an MMC is determined by the voltage difference across the arm inductor, Ls, as in
(10). Here Vdc+/- is the positive and negative dc link voltage, Vt-u is the phase-u voltage, The SM
capacitor voltage is governed by (11), where Ccap is capacitance of the SM capacitor.
iup-u = 1/Ls*∫(Vdc+−Σ(Ni*Vcap-i) −Vt-u), where u=a, b, or c;
(10)
Vcap-i=1/Ccap*∫(iup/low-u*Ni),
(11)
The MMC controller uses SM gating signals, Ni, to regulate arm current and SM capacitor voltage. A
positive variation on Ni will result in a negative variation on arm current if capacitor voltages are
invariable as in (10), and a positive variation on SM capacitor voltage if arm current is invariable as in
(11). However, coupling of the arm current and SM capacitor voltage in both equations makes the
control become parameters sensitive. For example, a positive variation applied to Ni by the controller
and a consequently negative variation on arm current could have conflict effects on the SM capacitor
voltage variation. Which effect prevails, or in other words whether the capacitor voltage increases or
decreases, depends on the MMC and control parameters, as well as the system operating point.
3. MMC CONTROL SCHEME
The multiple control objectives are listed below and achieved by different control loops which are
discussed in following subsections.
Basic VSC control: (1) Active power, and (2) Reactive power or ac voltage;
Dc link voltage control;
SM capacitor voltage control: (1) Overall control (average value = 1 pu) and (2) Balancing (among
every SM);
Current control: (1) Circulating current eliminating, and (2) Zero sequence current eliminating.
A Active and Reactive Power Control
The MMC basic control loop for power control is similar to a conventional VSC dq control where the
VSC ac voltage is controlled to a calculated reference value to guarantee that the actual active and
reactive powers track their set-points [7]. The control loop details can be found in literature and are
not given in this paper. In an MMC, the phase reactor Ls is in upper and lower arms, therefore, if the
voltage Vup-u and Vlow-u (u=a, b, or c) in Figure 1 are controlled to the same reference calculated by
the control loop, the upper and lower arms contribute equally to the phase currents, Figure 4.
B DC Link Voltage Control
In a conventional SVC, the dc voltage is determined by the dc link capacitor voltage and therefore it is
regulated through the active power control loop. In an MMC, the dc link capacitor is omitted and
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therefore the MMC has a direct and fast control of the dc link voltage. For example, the positive dc
link voltage is determined by SM terminal voltages as in (12), Figure 1.
Vdc+ =Σ(Ni*Vcap-i)+Vup-u , Vdc- = − Σ(Ni*Vcap-i)+Vlow-u ,
(12)
To regulate Vdc at 1 pu, the SM gating signal, N1i, can be calculated as in Figure 5 when capacitor
voltage Vcap is balanced. V*up/low-a,b,c is the outcome of the PQ control in Figure 4. The PWM reference
signals, n1i, are calculated according to (3).
C Arm Current Regulating
From (5), when upper and lower arms contribute equal phase current (iupac-u = ilowac-u) and the zerosequence component is eliminated (iup0-u = ilow0-u =0), the dc-link current in each phase can be
calculated as in (13). In order to have equal dc component of arm currents among the three phases as
in (9) and to eliminate the circulating current, the arm currents should respect (14).
idc-u = (iupac-u + ilowac-u )/2−icirc-u, where u=a, b, or c;
(13)
(iupac-u + ilowac-u )/2= idc-u/3,
(14)
where u=a, b, or c;
The arm current control loop is given in Figure 6. According to (10), when the dc component in an
arm is higher than its reference, a positive deviation on the PWM reference, n2i, is applied to reduce
the arm current, and vice versa.
D Zero-sequence Current Eliminating
For an MMC ac-dc-ac system, when either MMC is connected to a Y- or ∆-connection transformer,
the zero sequence current is 0 due to infinite zero sequence impedance. Otherwise if both terminals are
either transformerless or Yg- connection, there will exist a zero-sequence current circulating path. The
zero-sequence current is calculated as in (15), where the positive direction is defined as in Figure 1.
I0 = (Ia + Ib + Ic ) = (Idc+ − Idc-),
(15)
Therefore, eliminating zero-sequence current is equivalent to controlling the currents in positive and
negative dc links being equal. Based on (10), the control loop is given in Figure 7. For example,
when there is a positive zero-sequence current, i.e. the positive dc link current is larger than the
negative dc link current, a positive deviation is added to the PWM references of all SM in the three
upper arms and an opposite deviation is added to all in the three lower arms, to decrease Idc+ and
increase Idc- and consequently to suppress the zero sequence current.
E Overall SM Capacitor Voltage Control
The average SM capacitor voltage is controlled by regulating the overall energy stored in all
capacitors. For example, if the average voltage is higher than the reference, the control loop as in
Figure 8 gives a positive ∆Pref , which is added to Pref in PQ control in Figure 4. Consequently, more
power is injected into the ac gird meanwhile the power (current) flowing into the dc link remains the
same. Therefore, the energy and thus the voltage of the capacitors are reduced.
F SM Capacitor Voltage Balancing
Three actions are carried out to balance capacitor voltage of SM in difference locations.
1. To balance Vcap within each arm, the PWM reference of an SM with lower Vcap will be up-shifted to
have more charging time when the corresponding arm current is positive, and down-shifted for less
discharging time when current is negative. For SM with higher Vcap, the opposite operation is
applied to reduce its voltage.
2. To balance Vcap among phases, a positive dc offset is added to the reference of the current control
loop to increase charging current for the arms with lower average Vcap; and a negative dc offset for
the arms with higher average Vcap.
3. To balance Vcap between the three upper arms and the three lower arms, an opposite small phase
angle shift is applied to the voltage references of Vup-u and Vlow-u in Figure 4. With the small angle
difference in the voltage phase, the power flows into upper arms are slightly different to that into lower
arms and consequently equalize average capacitor energy and voltage in upper and lower arms.
The global view of the proposed controller is shown as in Figure 9.
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Figure 6 Arm current control loop
Figure 7 zero-sequence current eliminating loop
Figure 9 Global view of MMC control
Figure 8 Overall control of SM capacitor voltage
4. STUDY SYSTEM AND SIMULATION RESULTS
The study system is a back-to-back MMC system connecting two power systems through voltage stepup transformers. The two power systems (50 Hz and 60 Hz) are simplified as 230 kV infinite buses in
series with equivalent impedance. The voltage rating at the MMC ac side is 100 kV, and the dc side is
±100 kV. The power base is 200 MW. The MMC has 30 SM in each arm (60 per phase). The SM
capacitor is 5 mF. The arm inductor is 34 mH. The dc link has an inductance of 100 mH.
System steady state performance is given in Figure 10 where the active and reactive power references
are 0.4 pu and 0.05 pu respectively. The following is observed:
1. The ac voltage and current has low harmonics due to the harmonic cancellation among multiple SM
even without passive filters installed in the system;
2. Active and reactive powers are regulated at their set points;
3. DC voltage is closely regulated to 1 p.u. (deviation is below ±0.3%);
4. The SM capacitor voltages are controlled to 1 p.u. and well balanced;
5. The dc components of arm currents ({iupac-u+ilowac-u}/2) equally contribute to the dc link current and
the circulating currents are eliminated to minimum (the dc component of arm current in each phase
in Figure 10(h) is one third of dc link current Figure 10(g));
6. Zero sequence current is eliminated (the positive and negative dc link currents are equal in
magnitude)
Figure 11 gives the system response to a step change of power reference, where active power
reference is changed from 0 to 0.4 pu at time of 5 seconds. The following is observed:
1. The MMC has fast response, where the active power reaches its new set point within two cycles.
The ramp of the power change is actually limited by the controller so that the current will have a
smooth change to reduce harmonics during the transient.
2. The dc voltage deviation is limited to a small scale during the transient (less than ±2%);
3. During the transient, the SM capacitor voltages keep on being balanced, Figure 11(f), and the
deviation of their average value is limited to a small scale (less than ±2%), Figure 11(e);
4. the dc components of arm currents equally contribute to the dc link current;
5. No zero sequence current is induced during the transient.
Therefore, the MMC has fast response, and meanwhile fulfills the multiple control objectives at the
transient of controller command change.
To study the MMC performances at system fault conditions, two worst case scenarios, i.e. three-phaseground short circuit fault at transformer primary side and positive and negative dc link short circuit
fault, are investigated and the results are given in Figure 12 and Figure 13 respectively. In both cases,
the faults are applied at 6 seconds and cleared at 6.04 seconds. The MMC system survives both ac and
dc faults. It is observed that the voltage and current at ac and dc sides recover within a few hundreds
of milliseconds to a few seconds, while the SM capacitor voltages are balanced in a longer time frame,
i.e. a few tens of seconds. As long as the extent of capacitor voltage unbalancing is within a certain
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range, the MMC control is able to regulate the system voltages and currents on both ac and dc sides as
in normal operation.
Figure 10 MMC at steady states (a) ac voltages, (b) ac currents, (c) ac active and reactive powers (d) dc link
voltages, (e) upper and lower envelopes and mean value of SM capacitor voltages, (f) capacitor voltage mean
value in each arm (g) dc link current, (h) dc component of arm current, and (i) arm current.
Figure 11 MMC response to a power reference step change, (a) ac voltages, (b) ac currents, (c) ac active and reactive
powers (d) dc link voltages, (e) upper and lower envelopes and mean value of SM capacitor voltages, (f) capacitor
voltage mean value in each arm (g) dc link current, (h) dc component of arm current, and (i) arm current.
Figure 12 MMC response to a short circuit fault at transformer primary side, (a) ac voltages, (b) ac currents, (c) ac
active and reactive powers (d) dc link voltages, (e) upper and lower envelopes and mean value of SM capacitor voltages,
(f) capacitor voltage mean value in each arm (g) dc link current, (h) dc component of arm current, and (i) arm current.
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Figure 13 MMC response to dc link short circuit fault, (a) ac voltages, (b) ac currents, (c) ac active and reactive
powers (d) dc link voltages, (e) upper and lower envelopes and mean value of SM capacitor voltages, (f) capacitor
voltage mean value in each arm (g) dc link current, (h) dc component of arm current, and (i) arm current.
Note that in this study, the controller is not optimized for fault conditions and it operates without fault
detection and protection circuits. With a comprehensive fault study, the MMC controller can have
enhanced performances in fault conditions if equipped with protections.
5. CONCLUSIONS
The paper provided a comprehensive analysis of the MMC system, and presented a control scheme
with multiple control objectives to fulfill the requirements raised by the MMC distinctive topology.
The system is modeled in an electromagnetic transients program, RT-LAB, and simulated using the
eMEGAsim real-time simulator from OPAL-RT Technologies. The results show that the MMC has a
good dynamic response to control command and system transients, and the multiple control objectives
are fulfilled, especially the circulating currents in the MMC arms are eliminated and the SM capacitor
voltage are balanced. It also demonstrates the ability of RT-LAB to simulate complex power systems
with a very large number of power electronic switches in real time.
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