In review…!
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures
Lecture 16
State Elements & Intro to Combinational Logic
•  ISA is very important abstraction layer!
•  Contract between HW and SW!
•  Clocks control pulse of our circuits!
•  Voltages are analog, quantized to 0/1!
2010-07-19!
•  Circuit delays are fact of life!
•  Two types of circuits:!
!
!Instructor Paul Pearce!
•  Stateless Combinational Logic (&,|,~)!
•  State circuits (e.g., registers)!
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of DNSSEC. This is also a political issue! What is DNSSEC and why
does the root need to be signed? Read on.!
http://tinyurl.com/27nrtrf
http://en.wikipedia.org/wiki/Domain_Name_System_Security_Extensions
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (1)!
Maximum Clock Frequency!
•  State elements are used to:!
•  Build memories!
•  Control the flow of information between other state
elements and combinational logic!
•  D-flip-flops used to build registers!
•  Clocks tell us when D-flip-flops change!
•  Setup and Hold times important!
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (2)!
Maximum Clock Frequency!
Max Delay"
How does the clock period
relate to the Max Delay?"
Max Delay"
If the clock period is shorter
than the maximum circuit
delay, the circuit will not
function correctly!"
!Hint…!
Frequency = 1/Period!
Max Delay"
• What is the maximum frequency of
this circuit?!
Max Delay = !Setup Time + CLK-to-Q Delay!
!
!
!
!
! + !CL Delay!
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (3)!
Pipelining to improve performance (1/2)!
Here the clock period is
longer than the max delay.
This is wasteful, as the clock
period can be shortened."
Max Delay"
Now the clock period is
minimized. Minimum period
means maximum frequency!"
CS61C L16 State Elements II and Intro to Combinational Logic (4)!
Pipelining to improve performance (2/2)!
•  Insertion of register allows higher clock
frequency."
Extra Register are often added to help
speed up the clock rate."
•  More outputs per second."
Timing…!
Note: delay of 1 clock cycle from input to output."
Clock period limited by propagation delay of adder/shifter."
CS61C L16 State Elements II and Intro to Combinational Logic (5)!
Pearce, Summer 2010 © UCB!
Pearce, Summer 2010 © UCB!
Timing…!
Tradeoff: It now takes
2 clock cycles to
produce a result!"
CS61C L16 State Elements II and Intro to Combinational Logic (6)!
Pearce, Summer 2010 © UCB!
Recap of Timing Terms!
Finite State Machines (FSM) Introduction!
•  Clock (CLK) - steady square wave that
synchronizes system!
•  Setup Time - when the input must be stable before
the rising edge of the CLK!
•  Hold Time - when the input must be stable after the
rising edge of the CLK!
•  “CLK-to-Q” Delay - how long it takes the output to
change, measured from the rising edge!
•  Flip-flop - one bit of state that samples every rising
edge of the CLK!
•  Register - several bits of state that samples on
rising edge of CLK or on LOAD!
CS61C L16 State Elements II and Intro to Combinational Logic (7)!
Pearce, Summer 2010 © UCB!
Finite State Machine Example: 3 ones…!
FSM to detect the occurrence of 3 consecutive 1ʼs in the input."
• You have seen FSMs
in other classes. (Have
you?)"
• Same basic idea."
• We represent the
functionality of a FSM
with a “state transition
diagram”."
• With combinational
logic and registers, any
FSM can be
implemented in
hardware."
Hardware Implementation of FSM!
… Therefore a register is needed to hold the a representation of which
state the machine is in. Use a unique bit pattern for each state."
+!
Draw the FSM…!
Assume state transitions are controlled by the clock:"
on each clock cycle the machine checks the inputs and moves
to a new state and produces a new output…"
CS61C L16 State Elements II and Intro to Combinational Logic (9)!
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (8)!
Pearce, Summer 2010 © UCB!
Hardware for FSM: Combinational Logic!
Combinational logic circuit is
used to implement a function
maps from present state and
input to next state and output.!
=!
?!
CS61C L16 State Elements II and Intro to Combinational Logic (10)!
Pearce, Summer 2010 © UCB!
General Model for Synchronous Systems!
In the reference slides we discuss the detailed implementation, but
for now can look at its functional specification, truth table form."
Truth table…!
PS" Input" NS" Output"
00"
0"
00"
0"
00"
1"
01"
0"
01"
0"
00"
0"
01"
1"
10"
0"
10"
0"
00"
0"
10"
1"
00"
1"
CS61C L16 State Elements II and Intro to Combinational Logic (11)!
Pearce, Summer 2010 © UCB!
•  Collection of CL blocks separated by registers."
•  Registers may be back-to-back and CL blocks may be back-toback."
•  Feedback is optional."
•  Clock signal(s) connects only to clock input of registers."
CS61C L16 State Elements II and Intro to Combinational Logic (12)!
Pearce, Summer 2010 © UCB!
Peer Instruction!
Combinational Logic!
• FSMs had states and transitions!
• How to we get from one state to the
next?!
• Answer: Combinational Logic!
A.  The period of a usable
synchronous circuit is greater than
the CLK-to-Q delay!
B.  You can build a FSM to signal when
an equal number of 0s and 1s has
appeared in the input. !
A:
B:
C:
D:
AB
FF
FT
TF
TT
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (13)!
Truth Tables!
TT Example #1: 1 iff one (not both) a,b=1!
a!
0!
0!
1!
1!
0
CS61C L16 State Elements II and Intro to Combinational Logic (17)!
Pearce, Summer 2010 © UCB!
TT Example #2: 2-bit adder!
b!
0!
1!
0!
1!
CS61C L16 State Elements II and Intro to Combinational Logic (18)!
y!
0!
1!
1!
0!
Pearce, Summer 2010 © UCB!
TT Example #3: 32-bit unsigned adder!
How
Many
Rows?!
CS61C L16 State Elements II and Intro to Combinational Logic (19)!
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (16)!
Pearce, Summer 2010 © UCB!
How
Many
Rows?!
CS61C L16 State Elements II and Intro to Combinational Logic (20)!
Pearce, Summer 2010 © UCB!
Logic Gates (1/2)!
And vs. Or review – Danʼs mnemonic!
AND Gate!
Symbol
A!
D
B! AN
CS61C L16 State Elements II and Intro to Combinational Logic (21)!
Pearce, Summer 2010 © UCB!
Logic Gates (2/2)!
Definition
C!
CS61C L16 State Elements II and Intro to Combinational Logic (22)!
Pearce, Summer 2010 © UCB!
2-input gates extend to n-inputs!
• N-input XOR is the
only one which isnʼt
so obvious!
• Itʼs simple: XOR is a
1 iff the # of 1s at its
input is odd ⇒
CS61C L16 State Elements II and Intro to Combinational Logic (23)!
Pearce, Summer 2010 © UCB!
Truth Table ⇒ Gates (e.g., majority circ.)!
CS61C L16 State Elements II and Intro to Combinational Logic (24)!
Pearce, Summer 2010 © UCB!
Boolean Algebra!
• George Boole, 19th Century
mathematician!
• Developed a mathematical system (algebra) involving logic!
• later known as “Boolean Algebra”!
• Primitive functions: AND, OR and NOT!
• The power of BA is thereʼs a one-to-one
correspondence between circuits made
up of AND, OR and NOT gates and
equations in BA!
+ means OR,• means AND, x means NOT!
CS61C L16 State Elements II and Intro to Combinational Logic (25)!
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (26)!
Pearce, Summer 2010 © UCB!
Boolean Algebra (e.g., for majority fun.)!
BA: Circuit & Algebraic Simplification!
BA also great for circuit verification
Circ X = Circ Y?
use BA to prove!!
y=! (a • b)! + (b • c)! +!(a • c)!
y = a • b + b • c + a • c
y = ab + bc + ac!
CS61C L16 State Elements II and Intro to Combinational Logic (27)!
Pearce, Summer 2010 © UCB!
Laws of Boolean Algebra!
CS61C L16 State Elements II and Intro to Combinational Logic (29)!
CS61C L16 State Elements II and Intro to Combinational Logic (28)!
Pearce, Summer 2010 © UCB!
Boolean Algebraic Simplification Example!
Pearce, Summer 2010 © UCB!
Canonical forms (1/2)!
CS61C L16 State Elements II and Intro to Combinational Logic (30)!
Pearce, Summer 2010 © UCB!
Canonical forms (2/2)!
Sum-of-products!
(ORs of ANDs)!
CS61C L16 State Elements II and Intro to Combinational Logic (31)!
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (32)!
Pearce, Summer 2010 © UCB!
Peer Instruction!
“And In conclusion…”!
•  Max clock frequency is calculated based on max circuit delay!
•  We pipeline long-delay CL for faster clock!
•  Finite State Machines extremely useful!
•  Youʼll see them again 150,152, 164, 172…!
•  Boolean algebra!
•  Sum-of-products!
1.  (a+b)• (a+b) = b!
2.  You can use NOR(s) with clever
wiring to simulate AND, OR, & NOT!
A:
B:
C:
D:
12
FF
FT
TF
TT
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (33)!
Reference slides!
•  Use this table and techniques we learned to transform from 1
to another!
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (35)!
TT Example #4: 3-input majority circuit!
You ARE responsible for the
material on these slides (theyʼre
just taken from the reading
anyway) ; weʼve moved them to
the end and off-stage to give
more breathing room to lecture!!
CS61C L16 State Elements II and Intro to Combinational Logic (37)!
Pearce, Summer 2010 © UCB!
Truth Table ⇒ Gates (e.g., FSM circ.)!
PS! Input! NS! Output!
00!
0!
00!
0!
00!
1!
01!
0!
01!
0!
00!
0!
01!
1!
10!
0!
10!
0!
00!
0!
10!
1!
00!
1!
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (38)!
Boolean Algebra (e.g., for FSM)!
PS! Input! NS! Output!
00!
0!
00!
0!
00!
1!
01!
0!
01!
0!
00!
0!
01!
1!
10!
0!
10!
0!
00!
0!
10!
1!
00!
1!
or equivalently…!
or equivalently…!
y = PS1 • PS0 • INPUT!
CS61C L16 State Elements II and Intro to Combinational Logic (39)!
Pearce, Summer 2010 © UCB!
CS61C L16 State Elements II and Intro to Combinational Logic (40)!
Pearce, Summer 2010 © UCB!