Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
FEATURES
BSH105
SYMBOL
• Very low threshold voltage
• Fast switching
• Logic level compatible
• Subminiature surface mount
package
QUICK REFERENCE DATA
VDS = 20 V
d
ID = 1.05 A
RDS(ON) ≤ 250 mΩ (VGS = 2.5 V)
g
VGS(TO) ≥ 0.4 V
s
GENERAL DESCRIPTION
N-channel, enhancement mode,
logic level, field-effect power
transistor. This device has very low
threshold voltage and extremely
fast switching making it ideal for
battery powered applications and
high speed digital interfacing.
PINNING
SOT23
PIN
DESCRIPTION
1
gate
2
source
3
drain
3
Top view
The BSH105 is supplied in the
SOT23
subminiature
surface
mounting package.
1
2
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
VDS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
RGS = 20 kΩ
IDM
Ptot
Drain current (pulse peak value)
Total power dissipation
Tstg, Tj
Storage & operating temperature
Ta = 25 ˚C
Ta = 100 ˚C
Ta = 25 ˚C
Ta = 25 ˚C
Ta = 100 ˚C
MIN.
MAX.
UNIT
- 55
20
20
±8
1.05
0.67
4.2
0.417
0.17
150
V
V
V
A
A
A
W
W
˚C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-a
Thermal resistance junction to
ambient
FR4 board, minimum
footprint
300
-
K/W
August 1998
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
BSH105
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
CONDITIONS
MIN.
VGS = 0 V; ID = 10 µA
VDS = VGS; ID = 1 mA
Tj = 150˚C
RDS(ON)
gfs
IGSS
IDSS
Drain-source on-state
resistance
VGS = 4.5 V; ID = 0.6 A
VGS = 2.5 V; ID = 0.6 A
VGS = 1.8 V; ID = 0.3 A
VGS = 2.5 V; ID = 0.6 A; Tj = 150˚C
Forward transconductance
VDS = 16 V; ID = 0.6 A
Gate source leakage current VGS = ±8 V; VDS = 0 V
Zero gate voltage drain
VDS = 16 V; VGS = 0 V;
current
Tj = 150˚C
TYP. MAX. UNIT
20
-
-
V
0.4
0.1
0.5
-
0.57
140
180
240
270
1.6
10
50
1.3
200
250
300
375
100
100
10
V
V
mΩ
mΩ
mΩ
mΩ
S
nA
nA
µA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 1 A; VDD = 20 V; VGS = 4.5 V
-
3.9
0.4
1.4
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 20 V; ID = 1 A;
VGS = 8 V; RG = 6 Ω
Resistive load
-
2
4.5
45
20
-
ns
ns
ns
ns
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 16 V; f = 1 MHz
-
152
71
33
-
pF
pF
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
IDR
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
August 1998
MIN.
TYP.
MAX.
UNIT
Ta = 25 ˚C
-
-
1.05
A
IF = 0.5 A; VGS = 0 V
-
0.74
4.2
1
A
V
IF = 0.5 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 16 V
-
27
19
-
ns
nC
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
BSH105
Normalised Power Dissipation, PD (%)
BSH105
Peak Pulsed Drain Current, IDM (A)
120
1000
100
D = 0.5
100
0.2
80
0.1
60
0.05
10
0.02
40
P
D
D = tp/T
tp
single pulse
1
20
T
0
0
25
50
75
100
125
0.1
1E-06
150
1E-05
1E-04
Ambient Temperature, Ta (C)
1E-03
1E-02
1E-01
1E+00 1E+01
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Ta)
Fig.4. Transient thermal impedance.
Zth j-a = f(t); parameter D = tp/T
Normalised Drain Current, ID (%)
Drain Current, ID (A)
5
120
4.5V
4.5
100
2.5V
4
80
3.5
60
2.5
BSH105
Tj = 25 C
2.1 V
3
VGS = 1.9 V
2
40
1.7 V
1.5
20
1.5 V
1
1.3 V
0.5
0
0
25
50
75
100
125
1.1 V
0
150
0
Ambient Temperature, Ta (C)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Ta); conditions: VGS ≥ 4.5 V
0.5
1
1.5
Drain-Source Voltage, VDS (V)
2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
BSH105
Drain-Source On Resistance, RDS(on) (Ohms)
100
Peak Pulsed Drain Current, IDM (A)
0.5
BSH105
1.5 V
0.45
1.7 V
1.9 V
2.1 V
0.4
RDS(on) = VDS/ ID
10
0.35
tp = 100 us
0.3
1
0.1
2.5 V
0.25
1 ms
10 ms
0.2
100 ms
0.15
d.c.
VGS = 4.5 V
0.1
0.05
0.01
Tj = 25 C
0
0.1
1
10
Drain-Source Voltage, VDS (V)
100
0
Fig.3. Safe operating area. Ta = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
August 1998
0.5
1
1.5
2
2.5
3
Drain Current, ID (A)
3.5
4
4.5
5
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
Drain Current, ID (A)
BSH105
BSH105
Threshold Voltage, VGS(to), (V)
3
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDS > ID X RDS(on)
2.5
2
1.5
1
150 C
Tj = 25 C
0.5
0
typical
minimum
0
0
0.5
1
1.5
2
Gate-Source Voltage, VGS (V)
2.5
25
50
3
75
100
125
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
BSH105
Drain Current, ID (A)
Transconductance, gfs (S)
150
Junction Temperature, Tj (C)
1E+00
BSH105
VDS = 5 V
Tj = 25 C
4
1E-01
3.5
3
1E-02
2.5
1E-03
2
1E-04
1.5
1
1E-05
0.5
1E-06
0
0
0.5
1
1.5
2
2.5
1E-07
3
0
Drain Current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
0.4
0.6
0.8
Gate-Source Voltage, VGS (V)
1
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C
BSH105
Capacitances, Ciss, Coss, Crss (pF)
Normalised Drain-Source On Resistance
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.2
1000
RDS(ON) @ Tj
RDS(ON) @ 25C
2.5 V
Ciss
VGS = 4.5 V
100
1.8 V
Coss
Crss
0
25
50
75
100
125
10
150
0.1
Junction Temperature, Tj (C)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
August 1998
1
10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
BSH105
BSH105
Gate-source voltage, VGS (V)
10
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
VDD = 20 V
RD = 20 Ohms
Tj = 25 C
9
8
7
6
5
4
3
2
1
0
0
2
4
Gate charge, QG (nC)
6
Tj = 25 C
-0.2
-0.4
-0.6
-0.8
-1
-1.2
Drain-Source Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
August 1998
150 C
0
8
BSH105
Source-Drain Diode Current, IF (A)
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
BSH105
MECHANICAL DATA
Plastic surface mounted package; 3 leads
SOT23
D
E
B
A
X
HE
v M A
3
Q
A
A1
1
2
e1
bp
c
w M B
Lp
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
mm
1.1
0.9
OUTLINE
VERSION
A1
max.
bp
c
D
E
0.1
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
e
1.9
e1
HE
Lp
Q
v
w
0.95
2.5
2.1
0.45
0.15
0.55
0.45
0.2
0.1
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
SOT23
Fig.15. SOT23 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
August 1998
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
BSH105
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1998
7
Rev 1.000