Bridgeless Power Factor Correction Circuits with
Voltage-Doubler Configuration
Dylan Dah-Chuan Lu and Wenfei Wang
Power Engineering Laboratory
School of Electrical and Information Engineering
The University of Sydney, NSW 2006, Australia
dylan.lu@sydney.edu.au, wenfei.wang@sydney.edu.au
Abstract—This paper presents a generalized approach to
deriving single-phase power factor correction (PFC) circuits with
bridgeless and voltage-doubler structures. The approach requires
two dc/dc converters connected in a parallel-input series-output
manner. Compared to conventional full-bridge diode rectified
PFC circuit, which has two diodes along the input current
path, the PFC circuits derived by this approach have one diode
only, hence reducing the converter losses. Through the proposed
approach, some recently reported bridgeless PFC circuits have
been identified and new possible combinations can be generated.
A design example of dual buck dc/dc converters operating
in discontinuous-input-voltage mode (DIVM) is presented to
demonstrate the usefulness of the proposed approach.
I. I NTRODUCTION
Full-bridge diode rectifier has long been used in ac/dc
conversion due to its simple and robust circuit. A single
dc/dc converter, which is connected after the rectifier, is then
able to perform power factor correction (PFC) and output
voltage regulation. However as the output power increases,
the forward voltage drop across these standard Si diodes will
cause significant conduction loss. Bridgeless PFC rectifiers
have been introduced to reduce or eliminate the full-bridge
rectifier hence its losses [1]. There are a number of approaches
to produce bridgeless PFC circuits. One approach is to replace
all or partly the full-bridge rectifier by MOSFET which has
lower conduction loss if the on-state resistance is small enough
[2]. The other approach is to use a pair of MOSFETs to form
a bi-directional switch for bi-directional current flow during
the positive and negative ac line cycles [3].
For ac/dc conversion, voltage-doubler is usually used in
conjuction with a range switch so that the voltage at the
doubler is within a narrow voltage range for universal input
voltage application. It has also been used in improving power
factor in passive ac/dc circuits [4]-[5] and active ac/dc circuits
[6]. In [6] it is shown that, as compared to conventional
full-bridge rectifier, the rectifier which has a voltage doubler
reduces the capacitor voltage by half. This reduces the cost as
c
Copyright 2011
IEEE. Published in the Proceedings of the 2011 IEEE
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higher voltage electrolytic capacitors (e.g. 400V) are generally
more expensive than lower voltage ones (e.g. 250V).
Recently there are a number of ac/dc PFC circuits introduced which combined bridgeless and voltage-doubler structures to improve conversion efficiency. Not only the number
of semiconductors for input current path is reduced, the
voltage stress on the power transistors is also reduced. So
far, the bridgeless PFC circuits with voltage-doubler reported
are mainly on boost [7]-[9], buck [10] and SEPIC [11]
converter topologies. This paper hence explores the possibility
of deriving new topologies based on a general bridgeless PFC
converter with voltage-doubler structure, and discusses some
design considerations of these PFC circuits. A buck topology
with discontinuous-input-voltage mode (DIVM) operation is
designed and experimented to prove the feasibility of the
proposed approach.
II. D ERIVING B RIDGELESS PFC C IRCUITS
VOLTAGE - DOUBLER
WITH
A. Basic requirement
Fig. 1 shows the general structure of bridgeless PFC circuit
with a voltage-doubler. Two dc/dc converters are required
and are connected in a parallel-input series-output manner.
Therefore the output voltage, Vo , can be expressed as
Vo = VC1 + VC2
(1)
The two dc/dc converters can be of the same type or of
different types. But the PFC control must ensure the input
current waveshape and average input current of positive half
line cycle and that of the negative half cycle are equal.
Otherwise, even current harmonics will be generated. During
any half-cycle, only one dc/dc converter is in operation and
the other is idle.
B. Formation of PFC circuits
Fig. 2(a) shows two boost dc/dc converters forming a
bridgeless PFC circuit with voltage doubler structure. Note
that a common path must be available for both converters to
arrange their output voltages in series. Diodes Da and Db are
used to force unidirectional current flow and prevent charging
up of both inductors at the same time. This is in particular
valid for MOSFET switch. As shown in Fig. 2(a), suppose
during the positive line cycle S1 is operating and S2 is idle. If
Da and Db are absent, inductor L2 will still be charged up by
Vac due to the conduction of body diode even though it is not
supposed to be charged during this positive half line period.
The common path requirement also applies to other dc/dc
converters. Fig. 2(b) shows the PFC circuit formed by two
buck dc/dc converters. It has the same structure as that
proposed in [10]. Figs. 2(c), 2(d) and 2(e) are the bridgeless
PFC circuits with voltage-doubler formed by dual buckboost
converters, dual flyback converters and dual SEPIC converters
[11] respectively. In fact, based on this general structure, any
dc/dc converter can be used to form a bridgeless PFC converter
with voltage-doubler.
III. D ESIGN E XAMPLE , A NALYSIS
R ESULTS
AND
Da
L1
D1
C1
S1
+
VC1
−
+
Vo
Vac
−
Db
Common path
E XPERIMENTAL
L2
D2
-
C2
S2
−
VC2
+
(a) Dual boost converters [7]
A. Discontinuous input voltage mode (DIVM) buck converter
In order to show the usefulness of the proposed PFC converter structure, two buck converters working in discontinuous
input voltage mode (DIVM) are put into the structure, as
shown in Fig. 3, and studied. The DIVM buck converter
provides continuous input current and inherent PFC properties
by adding an inductor-capacitor filter [12], [13]. The capacitance (Ca and Cb ) of the filter is small enough to allow
discontinuous voltage operation for every switching cycle, i.e.,
its voltage drops to zero before the switch is turned off.
Da
S1
L1
C1
D1
+
VC1
−
Vac
+
Vo
−
Db
L2
S2
C2
D2
−
VC2
+
B. Circuit Operation
The operation of the DIVM buck converters within a
switching cycle has five stages and is explained, with the aid
of Figs. 4 and 5, as follows. Suppose the input ac voltage is at
its positive half cycle and the upper DIVM buck converter,
as shown in Fig. 3, is operating and the lower one is on
idle mode. Prior to t0 , the input capacitor Ca is charging
by input voltage and L1 operates in continuous conduction
mode. Since the switching frequency is much higher than the
AC line frequency, the input voltage v ac (t) is considered as
a constant within a switching period. The output load RL
with C1 and C2 form their own current loop which does not
connect to the main current loops of the two buck converters.
The DIVM buck converter behaves the same way as a normal
(b) Dual buck converters [10]
Da
S1
D1
C1
L1
−
VC1
+
−
Vo
Vac
+
Db
S2
D2
L2
C2
+
VC2
−
(c) Dual buck-boost converters
dc/dc
Converter 1
C1
+
VC1
−
+
Vo
Vac
dc/dc
Converter 2
Fig. 1.
Fig. 2.
Different converter topologies for the proposed bridgeless PFC
voltage-doubler structure.
C2
+
VC2
−
−
General structure of bridgeless PFC circuit with voltage doubler.
buck converter in which the input current will flow into the
circuit when the input voltage is higher than the output voltage.
Therefore the converter will introduce dead angles of input
current when Vo > vac (t). The following explanation assumes
vac (t) ≥ Vo :
Stage 1 (t0 ≤ t < t1 ) [Fig. 4(a)]: At t = t0 , S1 is turned
on. Capacitor Ca discharges through the switch and charges
Da
T1
D1
C1
S1
+
VC1
−
Vac
+
Vo
Db
T2
D2
−
C2
S2
+
VC2
−
(d) Dual flyback converters
Da
CB1
D1
C1
S1
+
VC1
−
+
Vo
−
Vac
Db
CB2
D2
C2
S2
−
VC2
+
(e) Dual SEPIC converters
Fig. 2.
Different converter topologies for the proposed bridgeless PFC
voltage-doubler structure.
Da
La
Ca
S1
D1
L1
C1
+
VC1
−
RL
Vac
to discharge and vCa drops below VC1 , L1 begins to discharge
as the voltage across it would become (vCa − VC1 ) < 0.
Stage 3 (t2 ≤ t < t3 ) [Fig. 4(b)]: At t = t2 , Ca is
completely discharged and D1 is turned on. vCa is clamped
by D1 . La continues to charge and the voltage across it equals
(vac − Vo ). Therefore output inductor current iL1 is the sum
of two currents, i.e. iLa + iD1 .
Stage 4 (t3 ≤ t < t4 ) [Fig. 4(c)]: At t = t3 , S1 is turned
off. Both La and Ca are charged by input voltage. The rate of
change of voltage on La slows down during this interval as its
voltage equals (vac − vCa ) and is decreasing as vCa increases
linearly. During this stage, iD1 only carries iL1 .
Stage 5 (t4 ≤ t < t5 ) [Fig. 4(c)]: At t = t4 , vCa ≤ vac and
thus La begins to discharge but Ca keeps charging as iLa > 0.
The period repeats when S1 turns on again at t = t5 . The
circuit operation of the upper buck converter can be applied
to the lower one, which takes place at the negative half line
cycle, as they are identical.
C. PFC Capability
Suppose the inductance of La is large enough such that the
input current ripple is small, the peak voltage of VCa is given
by
iin (Ts ) × [1 − d(t)]Ts
(2)
VCa,peak =
Ca
where iin (Ts ) denotes the average input current per switching
period Ts . The average input voltage during one switching
period is equal to the average voltage on Ca , which is given
by
VCa,peak
[1 − d(t) + ds (t)]
(3)
v ac (t) =
2
By combining (2) and (3), and considering the voltage-doubler
structure, the voltage conversion ratio of the PFC circuit is
expressed as
2ds (t)
Vo
=
v ac (t)
1 − d(t) + ds (t)
+
Vo
From (4), ds (t) can be expressed as
−
Db
Lb
Cb
S2
D2
L2
C2
−
VC2
+
ds (t) =
PFC circuit by dual DIVM buck converters.
Ts [1 − d(t)][1 − d(t) + ds (t)]
v ac (t)
=
2Ca
iin (t)
(5)
(6)
If ds (t) << (1 − d(t)), (6) can be approximately written as
Ts [1 − d(t)]2
(7)
2C
where C = Ca = Cb . It can be observed from (7) that if
duty cycle d(t) is made constant and with fixed switching
frequency, the converter can emulate a pure resistor which
implies unity power factor. Also, the output inductor L1 is
not a factor for (7) and hence L1 (and L2 ) can work in any
mode and its operation will not affect the PFC capability at
the input side.
Rin ≈
up L1 . Meanwhile, since vCa is higher than vac during this
interval, La is discharging with a voltage (vac − vCa ) across
it. The output load RL is sustained by C1 and C2 but C1
recovers some charges through iL1 .
Stage 2 (t1 ≤ t < t2 ) [Fig. 4(a)]: At t = t1 , S1
remains closed. Ca discharges such that vCa ≤ vac . As
(vac − vCa ) ≥ 0, La begins to charge up. While Ca continues
Vo [1 − d(t)]
2v ac (t) − Vo
Hence the input resistance of the converter, Rin , is calculated
from (2) and (3) and is given by
Rin =
Fig. 3.
(4)
Fig. 5.
Key waveforms of the DIVM buck converter.
D. Switch Voltage Stress and Input Current Ripple
As seen from Fig. 5, the power switch enjoys soft turnoff feature due to the presence of the small input capacitor,
Ca . However the switch turns on with a high drain-to-source
voltage as Ca charges up during turn-off period of the switch
and its peak value is governed by VCa . This voltage is
calculated by considering both the average voltages across La
and L1 . From the voltage-second balance of L1 , the following
relationship is found:
VCa,peak
(8)
2
Combine (3) and (8) would yield the maximum voltage stress
on the power switch, VDS,max , which happens when diode D1
is on and VCa is at its peak value, i.e.,
VC1 = ds (t)
VDS,max = VCa,peak =
2[vac (t) − VC1 ]
1 − d(t)
v ac (t) − VC1
[d(t) − ds (t)]Ts +
L
Z ta4
v ac (t) − vCa (x)
dx
La
t3
Value
Input voltage vin
110-220Vrms
Output voltage Vo
50V
Maximum output power Po
100W
Input capacitors Ca and Cb
208nF/450V
Input inductors La and Lb
2mH
Output inductors L1 and L2
60µH
Output capacitors C1 and C2
1000µF/200V
MOSFETs S1 and S2
IRFP450
Diodes D1 and D2
MUR460
Micro-controller
PIC18F4431
TABLE I
E XPERIMENTAL C ONDITIONS AND C IRCUIT PARAMETERS
(9)
From Fig. 5 and the analysis in Sec. III, it can be observed
that the input current iLa is continuous when v ac (t) ≥ Vo .
The input current ripple can be approximated by inspecting
the current rise during interval between t2 and t4 :
∆iLa (t) =
Parameters
(10)
E. Experimental Results
To verify the PFC analysis and proposed converter structure,
a laboratory prototype has been built and tested. The experimental conditions and circuit parameters are listed in Table
I.
Fig. 6 shows the gate-to-source signals for both switches
S1 an S2 . When one switch is in operation the other is idle.
Note that it is possible to have both switches in operation at
all times without disturbing the overall power conversion. It is
because, for instance during the positive half cycle, diode Db
is always reverse-biased and no current flows into the lower
converter, as shown in Fig.3. This ensures only one converter
operates at a time. However, having two switches operate at
all times increases switching loss and power consumption.
Fig. 7 shows the drain-to-source voltage of S1 . Thanks to
the small input capacitance, the MOSFET enjoys zero-voltage
turn-off operation. Fig. 8 displays the measured input current,
showing sinusoidal waveshape during the conduction period.
The harmonic contents of the input current is shown in
Fig. 9 which experimentally proven that the converter can
meet stringent Class D limits of the IEC 61000-3-2 standard.
Finally, Fig. 10 depicts the measured efficiency at different line
and load conditions. The efficiency is around 90% for both
line conditions at 20% load and above. The peak efficiency
iLa
-
iS1
-
iL1
-
Io
La
Ca
S1
D1
L1
C1
+
VC1
−
RL
Da
6
-
Vac
+
Vo
−
Io
Io
(a) Stage 1 (t0 ≤ t < t1 ) and Stage 2 (t1 ≤ t < t2 )
iLa
-
iS1
-
iL1
-
Io
La
Ca
S1
D1
L1
C1
+
VC1
−
RL
Da
6
iD1
-
Vac
Fig. 6.
Gate signals for S1 and S2 .
+
Vo
−
Io
Io
(b) Stage 3 (t2 ≤ t < t3 )
-
Da
iLa
La
Ca
S1
D1
?
iL1
-
Io
L1
C1
+
VC1
−
RL
6
iD1
-
Vac
+
Vo
−
Io
Io
Fig. 7.
Measured drain-to-source voltage of S1 .
(c) Stage 4 (t3 ≤ t < t4 ) and Stage 5 (t4 ≤ t < t5 )
Fig. 4. Operating stages of the proposed DIVM buck converter within a
switching period.
of the converter is 92% at 220V input. This is expected as at
high line condition the input current is smaller and hence the
conducion loss of the power semiconductors is reduced.
IV. C ONCLUSION
This paper introduced a generalized approach to deriving
single-phase bridgeless voltage-doubler PFC circuits by combining two dc/dc converters in a parallel-input series-output
manner. A number of recent published topologies are identified
as being derived from the proposed structure. To demonstrate
the usefulness of the proposed approach, a bridgeless voltage-
Fig. 8. Measured input voltage (200V/div) and current (1A/div) waveforms.
Time base: 10ms.
Fig. 9. Measured current harmonic contents of the input current at rated
condition.
Fig. 10. Measured conversion efficiencies of the converter at 110V and 220V.
doubler PFC converter using two buck converters operating in
discontinuous input voltage mode (DIVM) is presented. Experimental results have shown that the PFC converter constructed
by the proposed approach achieves high power factor and high
efficiency.
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