Metal Oxide Semiconductor
Field Effect Transistor (MOSFET)
Structure:
G
S
metal
n
D
oxide
n
semiconductor
p+
1
MOSFET operation
If VG=0
Assuming VD=high, VS=0
G
S
n
D
No current
nn
p+
2
MOSFET operation
If VG=high
Now if VD=high, there is a current
flow between D and S
G
S
D
++
n
++
Gate voltage attracts
electrons and pushes
holes away
nn
An n type channel
is formed
p+
3
MOSFET structures and circuit symbols
Gate
Depl et i on r egi on
Sour ce
Dr ai n
+
n
n+
Si O2
Dr ai n
Dr ai n
Dr ai n
Gate
Bul k
p- t ype subst r at e
Sour ce
Channel
Sour ce
Sour ce
(c)
(d)
Subst r ate
(a)
(b)
(a) Schematic structure of n-channel MOSFET (NMOS) and
circuit symbols for (b) MOSFET, (c) n-channel MOSFET, and (d)
n-channel MOSFET when the bulk (substrate) potential has to
be specified in a circuit.
4
Complementary MOSFET pairs
Gat e
Sour c e
+
n
Si O2
Dr ai n
n- channel
p- channel
Si O2
+
p
Dr ai n
Dr ai n
Gat e
p- t yp e subst r at e
Bul k
n- t y p e wel l
Subst r at e
Sour ce
Sour c e
Schematic structure of Complementary MOSFET (CMOS) and
circuit symbols for p-channel MOSFET (PMOS). Minuses and
pluses show the depletion regions.
5
Sub-threshold mode of MOSFET operation
• VG = 0; the MOSFET conducting channel
V =0
is not formed
higher V
G
Energy
Channel
Source
Ec
ΦB
G
²E F1
²E F2
Drain
EF
Distance
In the subthreshold regime, the MOSFET current is a small reverse current
through the source – substrate and drain – substrate p-n junctions;
Only a small number of electrons can pass over the potential barrier
separating the drain and the source.
nST ≈ nSource × e − ( Φ B / kT )
6
Sub-threshold mode of MOSFET operation
10 2
VG1
10
VG2
10
10
VG3
Source
0
0.05 V
It
-2
-4
10 -6
Drain
VG1<VG2<VG3
V ds = 3.0 V
10
10
-8
-10
-0.2
0.2
0.6
1.0
1.4
1.8
Gate-source voltage (V)
In the sub-threshold regime, the channel current is very low and increases
exponentially with the gate bias.
nST ≈ nSource × e − ( Φ B / kT )
7
MOSFET threshold voltage
10 2
VG1<VG2<VG3
VG1
10
10
VG2
10
VG3
Source
0
0.05 V
It
-2
-4
10 -6
Drain
VT
V ds = 3.0 V
10
10
-8
-10
-0.2
0.2
0.6
1.0
1.4
1.8
Gate-source voltage (V)
At certain gate bias called the threshold voltage, the conductivity type under
the gate inverts and the barrier between the Source and the Drain
disappears.
Electrons can enter the region under the gate to form a
conducting n-channel.
At the gate voltages above the threshold, the gate and the channel form a
Metal-Insulator-Semiconductor (MIS) capacitor.
8
MOSFET above the threshold voltage
The free electron charge in the MOSFET channel (per unit area):
Q1 = CGATE × (VG – VT)
(assuming that at VG = VT the free electron concentration is zero)
In MOSFETs, the gate and channel form a MIS-capacitor,
hence the capacitance per unit gate area
ci = ε i / d i = ε ir ε 0 / d i
εi = εir ε0
is the total dielectric permittivity of the gate dielectric
(usually, SiO2), εir is the relative dielectric permittivity of the gate dielectric.
Total gate capacitance CG = ci ×A, where A is the gate area
The sheet electron concentration above the threshold, nS is given by:
qns = ci (VGS − VT ) = ci VGT
9
MOSFET above the threshold voltage
10 2
10
10
10
V ds = 3.0 V
0
0.05 V
It
-2
-4
10 -6
10
10
qns = ci (VGS − VT ) = ci VGT
-8
-10
-0.2
0.2
0.6
1.0
1.4
1.8
Gate-source voltage (V)
Above the threshold, the sheet electron concentration and hence
the channel current increase linearly with the gate bias VG.
10
MOSFET Threshold Voltage
G
S
metal
n
D
oxide
n
semiconductor
p+
Source
Drain
11
Band Diagram at the MOS interfaces
Before Contact
Vacuum level
oxide
q χox
EC
n
q χs
qφm
qφs
EC
EFm
Ei
Eg
p+
metal
EFs
EV
n
EV
METAL
OXIDE
SEMICONDUCTOR
12
After Contact
Metal and semiconductor Fermi levels align by
electron transfer. Bending is the result of the
presence of transferred electron
E
ECC
EC
n
Ei
EFm
EC
EFs
EVEi
EFs
EV
p+
n
EV
METAL
OXIDE
SEMICONDUCTOR
13
n
Flat band Voltage
VG
Gate voltage making the band flat
p
+
VFB= φm-φs
n
EC
EC
EC
EC
EC
Ei
EFs
EV
VG
EC
EFm
EFm
Ei
EFs
EV
VG
VG
Ei
EFs
EV
EFm
EV
EV
VG>0
EV
VG=VFB
VG<VFB
14
Conductivity conversion in MOSFET
n
n
Less holes at the
interface, more
bending
VG
VG
p
+
p
+
n
n
Less p type
p type
EC
EC
Ei
Ei
EFs
EFs
EV
EV
VG=0
VG ↑
More depletion
15
n
n
VG
VG
p
+
p
+
n
Less p type
n
p type
Less p type
p type
EC
EC
Onset of
Channel
Ei
creation
EFs
Channel
Ei
created
EFs
EV
EV
VG ↑ ↑
n type
Inversion
VG ↑ ↑ ↑
n type
Strong Inversion
16
Inversion condition in MOSFET
Equilibrium hole concentration in the bulk of semiconductor
p = ni
qφb
e kT
EC
qφb is the Fermi level offset from
the mid-gap in the bulk material
qVs
Ei
EFs
qφb
EV
Surface potential Vs
is controlled by the gate voltage
Accumulation
Depletion
Onset of inversion
Inversion
Vs<0
Vs<φb
Vs=φb
Vs>φb
Strong Inversion
Vs>2φb
When Vs = 2φb, n-concentration at the surface
is the same as p-concentration in the bulk
17
Surface potential required to reach
the MOSFET threshold
n = ni
qφb
e kT
p = ni
qφb
e kT
EC
VsT=2φb
φb
φb
Ei
EFs
EV
When Vs = 2φb, n-concentration at the surface
is the same as p-concentration in the bulk
18
Surface potential and gate voltage
• VG is the gate voltage, as source is grounded,
VG=VGS
Vi
EC
EC
• Vi is the voltage drop across the oxide/insulator
• Vs is the surface potential
Ei
EFs
EV
Vs
VG
EFm
VGS = VFB + Vs + Vi
EV
19
Voltage drop across the oxide layer
VGS = VFB + Vs + Vi
Vi
EC
EC
Vi is the voltage drop across the oxide/insulator
Gate electrode and semiconductor form the
plates of the MOS capacitor.
Ei
EFs
EV
Vs
VG
EFm
Voltage drop across the capacitor:
Q
Vi = d
Ci
EV
where Qd is the capacitor charge and Ci is the capacitance.
Since the charges on the metal and semiconductor plates are the same,
Qd can be calculated as the charge in semiconductor.
The semiconductor charge is formed by the charge of the depletion region
20
Voltage drop across the oxide layer
The relation between the depletion region width W and
the applied voltage Vs:
q Na W 2
Vs =
2εs
Form this,
Vi
EC
EC
Ei
EFs
EV
Vs
VG
2εVs
W=
qN a
EFm
EV
The depletion region charge (per unit area):
Qd = qN a W = qN a
2εVs
qN a
→ Qd = 2ε s qN aVs
21
Voltage drop across the oxide layer
Q
Vi = d
Vi
EC
ci
EC
where, Qd = 2εs qN a Vs
Ei
EFs
EV
Vs
VG
is the depletion region charge per unit area,
EFm
ci is the MOS-capacitor capacitance per unit area:
ci =
εi
di
EV
di is the thickness of the oxide film under the gate
22
MOSFET threshold voltage (cont.)
The MOSFET threshold voltage is defined as the Gate
voltage leading to the strong inversion, i.e. Vs = 2φb
VGS = VFB + Vs +
2ε s qN aVs
ci
At the onset of strong inversion:
VT = VFB + ( 2φb ) +
2ε s qN a ( 2φb )
ci
Finally, the threshold voltage,
VT = VFB + 2ϕb + γ
2ϕb
N
where the body effect constant,
γ N = 2ε s qN a / ci
23
Effect of Body Bias
VS
VG
VD
n
n
p+
VBS ≠0
the Threshold voltage,
VT = VFB + 2ϕb + γ N
(2ϕb − VBS )
24
Effect of Surface States
VS
VG
VD
n
During the oxide growth on Si, dangling
bonds are created that contributes to
wanted trapped charges at the interface
n
++++++++++
p+
VBS ≠0
the Threshold voltage,
VT = VFB +
Q ss
Ci
+ 2ϕ b + γ N
(2ϕb − VBS )
Qss : surface state charges per unit area
25