Turkish Journal of Electrical Engineering & Computer Sciences
http://journals.tubitak.gov.tr/elektrik/
Research Article
Turk J Elec Eng & Comp Sci
(2015) 23: 2182 – 2196
c TÜBİTAK
⃝
doi:10.3906/elk-1306-111
Analysis and design of an interleaved current-fed high step-up quasi-resonant
DC-DC converter for fuel cell applications
Sina SALEHI, Behrooz VAHIDI∗, Jafar MILI MONFARED, Meghdad TAHERI, Hadi MORADI
Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran
Received: 12.06.2013
•
Accepted/Published Online: 25.08.2013
•
Printed: 31.12.2015
Abstract: This paper proposes a current-fed quasi-resonant converter with soft switching method. Input current ripple
is reduced by employing two boost circuits at the input, which makes this converter appropriate for fuel cell application.
Current stress on switches is reduced because of the resonance in switches, and also, as a result of zero voltage switching
in switches, switching losses will be reduced in this proposed converter. In the output, the reverse recovery problem
of diodes is alleviated by zero current switching, so there is no need for fast diodes anymore. The reduction of losses
improves the efficiency, and in a wide range of load, efficiency is high. Experimental results on a 1-kW prototype are
provided to validate the proposed concept.
Key words: Current-fed, fuel cells, isolated boost converter, quasi-resonant DC-DC converter, zero-voltage switching
1. Introduction
These days a variety of topologies of DC-DC converters have been proposed, and they are more applicable.
Different demands are considered depending on application of DC-DC converters, like high efficiency [1–3],
high voltage gain [4], low voltage and/or current stress on switches [5,6], smaller size of magnetics [7], etc. A
resonant converter is one kind of converter satisfying these needs [6,8–16]. These converters can operate at high
frequencies [17]. Because of this, they have light weight and small size. Since the size and weight of converters is
highly restricted in some applications, resonant converters are more capable. Analysis complexity is one major
disadvantage of resonant converters [7,18,19].
Pulse width modulation (PWM) converters have high electromagnetic interference (EMI) and switching
losses at high frequencies [20], while switching losses and EMI at high frequencies for resonant converters are
low [21]. Quasi-resonant converters are a kind of resonant converters employing soft switching at zero voltage
(ZVS) and/or zero current (ZCS) to reduce losses and to improve efficiency [5,6,22].
This proposed converter (Figure 1) operates in discontinuous conduction mode (DCM) to achieve minimum current stress in the turn-off switching state. Further controllability of the converter becomes easier, so
this proposed converter can be controlled with a PWM method in contrast to conventional resonant converters.
Consequently, the converter works at a constant frequency, reducing the EMI effect [23]. Since this converter is
controlled by the PWM method, control complexity is eliminated.
Fuel cells produce unregulated and low-level voltage, and they also have low dynamics, so they require a
step-up converter with low-input current ripple; because of the longer life of the fuel cell catalyst, the current
∗ Correspondence:
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vahidi@aut.ac.ir
SALEHI et al./Turk J Elec Eng & Comp Sci
ripple at the fuel cell output must be very low. Three basic topologies of appropriate converters were introduced
in [24]. The proposed converter in [24] is a kind of current-fed PWM converter. This converter is employed
by two boost circuits at the input, which work by half-period delay, so the input current ripple is reduced.
Current-fed converters in general have lower transformer turns ratio than voltage-fed, which results in lower
leakage inductance and copper losses and improves efficiency [24].
+ S4
VC1
_
S2
Lk1
S1
Co1
+ Vlk1 _
+
T1 D2
b
a
C1
Co2
RL
N3:N4
iS1
Vin
D1
N1:N2
iS2
iLB1 LB1
LB2
C4
+ S3
VC1
_
C3
D3
Co3
VO
_
Lk2
T2 D4
Co4
Figure 1. Proposed converter.
Many current-fed topologies have been discussed and analyzed in recent years. In [25–28], converters
have hard switching and switches suffer from high voltage stress at switch turn-off. Thus, losses will increase
and reduce efficiency. In [28] extra components are used to achieve ZVS, but this results in complex topology
and lower efficiency.
The proposed converter, as compared to that in [24], has a lower current stress on switches (approximately
half), so it has lower switching losses, but it could have more conduction losses. However, by using switches
with low ON-state resistance, conduction losses of the proposed converter and that of [24] would be the same.
ZCS in output diodes also alleviates the reverse recovery problem of the diodes. In this converter, like in [24],
an interleaved boost circuit is used. Using interleaved boost topology requires lower transformer turns ratio.
Outputs of these boost circuits are applied to the output of the converter by two high-frequency transformers.
In the output two voltage doubler circuits, which are connected in series, make the DC voltage.
Leakage inductance of transformers is used for the resonant circuit. The converter works at high frequency,
which causes lower weight and smaller size of transformers, inductors, and capacitors.
2. Operation principle and converter analysis
The proposed converter circuit is shown in Figure 1. Input boost circuits consist of inductance L B1 and L B2 ,
and switches S 1 and S 2 . Leakage inductance of transformers in the primary side is modeled as L k1 and L k2 .
Capacitors C 1 and C 2 with leakage inductances L k1 and L k2 provide the resonant circuits, respectively. Active
clamp circuits are made by C 2 and C 4 and switches S 2 and S 4 , respectively. In the secondary side of the
transformers, diodes D 1 , D 2 and D 3 , D 4 work as a half-bridge rectifier, providing two voltage doubler circuits
with capacitors C O1 , C O2 , C O3 , and C O4 , which are connected in series at the output. Voltage polarization of
capacitors C 1 and C 2 , current direction of switches S 1 and S 2 , and inductor L B1 are shown in Figure 1. The
same components of the second leg have the same voltage polarization and current direction as in the first leg.
In this converter, the resistance of switches is neglected. Because of ZCS on the output diodes, fast
diodes are not necessary. Moreover, R L is the candidate for the load resistance. N 1 and N 2 are the primary
and secondary turn ratio of transformer T 1 , respectively, and N 3 and N 4 for transformer T 2 . The turn ratios
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SALEHI et al./Turk J Elec Eng & Comp Sci
of these two transformers are the same, so is defined as. f s and f r are switching and resonant frequencies,
respectively.
The operation of the proposed converter has twelve intervals. The first and second six intervals are the
same, so here the first six intervals will be described. Important currents and voltage curves are shown in
Figure 2 and circuit diagrams are shown in Figure 3. At the time before t 0 , switches S 2 and S 4 are turned on.
Inductances L B1 and L B2 are large enough to alleviate input current ripple, so it is assumed that the input
current has a constant value of I in . Furthermore, it is assumed that the voltage of C 2 and C 4 has a constant
value of V C .
S1
S2
S4
S3
t
S3
i1
t
ilk1
ilk2
t
ilk1
iS1
i 1 -Iin
iS2
t
-Iin
iS3
iS4
t
V1
V3
VT1
V2
t
V1
V3
VT2
V2
VC1
VC
i1
Iin
t
VC3
t
i C3
i C1
t
iD1
iD2
t
iD4
iD3
t
iin
iLB1
iLB2
t 0 t1t 2 t 3
d1Ts
t4 t 5
d2Ts
(1-D)Ts
t 6 t7 t 8 t 9
d3Ts
d1Ts
t10 t 11
t12
t
(1-D)Ts
d2Ts
Figure 2. Important waveforms of proposed converter.
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SALEHI et al./Turk J Elec Eng & Comp Sci
1) Interval 1 [ t0 − t1 ]
At t 0 , S 2 turns off and the difference of I LB1 and the transformer T 1 current flows through the
antiparallel diode of switch S 1 . As long as this current flows, voltage across S 1 is zero and gate pulse can
be applied to achieve ZVS. The current of transformer T 2 is zero, but the current of S 3 remains I LB2 in the
entire interval and the power supply charges the inductor L B2 .
At the output, diodes D 2 , D 3 , and D 4 are turned off. This interval will finish when the reverse current
of S 1 decreases to zero.
2) Interval 2 [ t1 − t2 ]
At t 1 , the current of switch S 1 changes its direction and flows through the switch because S 1 was turned
on in the previous interval. I in circulates through S 1 and the source, and V in charges input inductor L B1 . By
applying voltage V 1 = V O1 /2n via transformer T 1 , primary winding to C 1 and L k1 in two last intervals, i lk1 ,
decreases to zero. This interval will finish when i lk1 reaches zero. In the output D 1 is conducting. Thus:
−i1 =
−Vo1 /2n − VC′
d1 TS ,
Lk
d1 TS = t2 − t0 ,
(1)
(2)
where VC′ is the voltage of capacitor C 1 at time t 0 .
3) Interval 3 [ t2 − t3 ]
At t 2 , the current of transformer T 1 changes its direction and the voltage of output capacitor C O2 is
reflected via this transformer to the primary side, and C 1 and L k1 make resonance. During this interval, as a
result of V in across L B1 , the current of the input inductance is rising. Because of changing the direction of
i lk1 in this interval, the direction of the secondary current is also changed, so in the output doubler circuit, D 2
is conducting and supplies output capacitor C O2 . In these two last intervals, the second leg operates the same
as in the first interval.
4) Interval 4 [ t3 − t4 ]
At t 3 , S 3 turns off and the difference of i LB2 and the current of transformer T2 flows through antiparallel
diode of switch S 4 and charges C 4 . At the beginning of this interval, the parasitic capacitor of S 4 and S 3 is
discharged and charged to V in /(1 – D). As long as the current flows through the body diode of S 4 , voltage
across S 4 is zero and the gate pulse can be applied to achieve ZVS. In the output, D 2 and D 3 are conducting.
This interval will finish when the reverse current of S 4 reaches zero.
5) Interval 5 [ t4 − t5 ]
When the current of the antiparallel diode of S 4 reaches zero, its direction changes, and it flows through
switch S 4 , which has been turned on in the previous interval. The current of transformer T 2 is rising just like
in the previous interval. In these two later intervals, the constant current of L LB2 flows through transformer
T 2 and charges C 3 . The current of capacitor C 4 circulates through transformer T 2 . This interval finishes by
removing the pulse gate of S 4 . In these two last intervals, the second leg operates the same as in interval 3.
For this interval:
d2 TS = t5 − t2 ,
(3)
ilk (t5 ) =
Vo2 /2n − VC′
√
sin(ωr d2 TS ) = 0,
(4)
Lk
C1
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SALEHI et al./Turk J Elec Eng & Comp Sci
d2 TS = π
√
Lk C1 ,
(5)
where V 2 = V O2 /2n is voltage of capacitor C O2 , reflected to the primary side of the transformer.
6) Interval 6 [ t5 − t6 ]
This interval will begin when the current of transformer T 1 reaches zero. Capacitor C 1 and inductor L k1
transfer their energy to the output, and consequently the voltage across transformer T 1 reaches zero. However,
the current of S 1 remains I LB1 in the entire interval and the power supply charges inductor L B1 . Based on
the diagrams shown in Figure 2:
d3 TS = t9 − t5 = DTS − d1 TS − d2 TS ,
(6)
and, by applying the volt-second law to the transformer winding:
d1 V1 + d3 V3 = d2 V2 ,
V3 =
d2 V2 − d1 V1
.
d3
(7)
(8)
At the output, diodes D 1 and D 2 are turned off because the secondary current is zero. At time t 3 the
current of transformer T 2 rises linearly from 0 until t 6 reaches t 1 . Thus:
i1 =
VC − VO3 /2n
(1 − D)Ts ,
Lk
(1 − D)Ts = t6 − t3 .
(9)
(10)
V c is the voltage of the clamp capacitor and V O3 /2n is the voltage of C O3 on the output, which was reflected
to the primary side of the transformer, which is equal to V 1 , and DT s is duty cycle of switch S 1 .
3. Theoretical analysis
3.1. Voltage gain
Here it is assumed that the voltage of capacitors C1 , C2 , output capacitors, and input current I in are constant.
According to proposed converter in Figure 1, by applying KCL to node “a”, the average current of C 1 , C 2 ,
and L k is zero.
⟨ilk1 ⟩ + ⟨iC1 ⟩ + ⟨iC2 ⟩ = 0
(11)
Here, “ ⟨•⟩ ” means the average value of “ •”. In the steady state, the average current of the capacitors is zero;
that is:
⟨iC1 ⟩ = ⟨iC2 ⟩ = 0,
(12)
and therefore:
⟨ilk1 ⟩ = 0.
(13)
However, during time (1 – D)T s = t 6 – t 4 , by applying KCL in node “b”:
iC1 + Iin = iLK .
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(14)
SALEHI et al./Turk J Elec Eng & Comp Sci
Here I in is the average input current. Switch S 2 is in series with capacitor
C 2 (i C2 -i S2 ) so from Eq. (13) its average current is zero. From Figure 2 during time (1 – D)T s , the
average current of i lk is equal to I in , and then:
1
i1 (1 − D)TS = Iin (1 − D)TS ,
2
(15)
i1 = 2ILB = Iin .
(16)
⟨Vin ⟩ = ⟨VLB1 ⟩ + ⟨VT 1 ⟩ + ⟨VLk1 ⟩ + ⟨VC1 ⟩ .
(17)
By applying KVL:
In the steady state the average voltage of the inductors and the windings of the transformer are zero, and so:
⟨Vin ⟩ = ⟨VC1 ⟩ .
(18)
As shown in Figure 3 at time t 9 to t 12 the current I in flows through C 1 and then the current of C 1 jumps
to i 1 ; after that it decreases almost linearly to zero. Simultaneously the voltage of C 1 during time t 9 to t 12
increases linearly and after that it has resonance and reaches its peak value at t 8 . Its minimum occurs at t 11
and it is constant to t 3 .
Voltage of C 1 increases linearly from t 9 to t 12 . The time interval between t 6 and t 8 is too short, and
consequently it can be assumed that in this interval voltage of C 1 is constant. From Eq. (18) it can thus be
said that:
S2
+ S4
VC1
_
C2
C4
Lk1
LB2
+
T1 D2
b
a
C1
S1
S2
C2
Co2
RL
N3:N4
iS1
+ S3
VC1
_
C3
+ S4
VC1
_
C4
D3
Co3
LB2
Lk1
_
T2 D4
Co4
D1
Co1
N1:N2
+ Vlk1 _
+
T1 D2
b
a
N3:N4
C1
Co2
RL
iS1
S1
VO
Lk2
iS2
iLB1 LB1
Vin
Co1
+ Vlk1 _
iS2
iLB1 LB1
Vin
D1
N1:N2
+ S3
VC1
_
C3
D3
Co3
VO
_
Lk2
T2 D4
Co4
Figure 3. Operating intervals of quasi-resonant converter.
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SALEHI et al./Turk J Elec Eng & Comp Sci
S2
C4
Lk1
+
T1 D2
b
a
S2
C2
+ S3
VC1
_
C3
+ S4
VC1
_
C4
Lk1
_
D1
Co1
N1:N2
+ Vlk1 _
C2
Co2
RL
N3:N4
+ S3
VC1
_
C3
+ S4
VC1
_
C4
D3
VO
Co3
_
Lk2
Lk1
T2 D4
Co4
D1
Co1
N1:N2
+ Vlk1 _
iS2
+
T1 D2
b
a
N3:N4
C1
S1
S2
C2
Co2
RL
iS1
+ S3
VC1
_
C3
+ S4
VC1
_
C4
D3
VO
Co3
_
Lk2
T2 D4
Lk1
D1
N1:N2
Co4
Co1
+ Vlk1 _
iS2
iLB1 LB1
+
T1 D2
b
a
C1
Co2
RL
N3:N4
iS1
S1
Co4
T1 D2
C1
iLB1 LB1
Vin
T2 D4
a
S2
LB2
Co3
+
b
S1
Vin
VO
Lk2
iS1
LB2
D3
iS2
iLB1 LB1
Vin
Co2
RL
N3:N4
C1
S1
LB2
Co1
+ Vlk1 _
iS1
Vin
D1
N1:N2
iS2
iLB1 LB1
LB2
+ S4
VC1
_
C2
+ S3
VC1
_
C3
D3
Co3
VO
_
Lk2
T2 D4
Co4
Figure 3. Continued.
∆VC1 =
VC′ = VC1 (t0 ) = Vin +
2188
Iin
(1 − D)TS ,
C1
∆VC1
Iin
= Vin +
(1 − D)TS .
2
2C1
(19)
(20)
SALEHI et al./Turk J Elec Eng & Comp Sci
From Figure 4 and by applying volt-second product equations on output capacitors, relations among V O1 , V O2 ,
and V O can be easily obtained as follows [29]:
VO1 = (1 − D + d1 )VO /2,
(21)
VO2 = (D − d1 )VO /2.
(22)
V C can be represented as:
VC = (
D
)Vin .
1−D
(23)
From Eqs. (1), (9), (20), (21), and (23)
iD2(peak)
iD1(peak)
d1 Ts
(1-D)Ts
d2 Ts
d3 Ts
DTs
Figure 4. Output diode current.
T 1 can be obtained as:
d1 =
VO
D
(1 − D)( 1 −
D Vin − (D − d1 ) 2n )
O
+ Vin +
(D − d1 ) V2n
Iin
2C1 (1
− D)TS
.
(24)
The average current of each output diode is equal to the output current, because the average current capacitors
are zero. Thus:
IO =
1
iD2(peak) (1 − D + d1 ).
2
(25)
From Figure 2 and Eq. (16):
iD2(peak) .n = i1 = Iin .
(26)
By using Eqs. (25) and (26), the output current can be obtained as:
IO =
Iin
(1 − D + d1 ).
2n
(27)
By assuming that the converter is lossless, it can be said that:
M =
VO
Iin
2n
=
=
,
Vin
IO
1 − D + d1
(28)
and so if the transformers are assumed to be ideal, leakage inductance and d 1 can be neglected and ideal voltage
gain will be as follows:
2n
M =
.
(29)
1−D
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SALEHI et al./Turk J Elec Eng & Comp Sci
By using Eqs. (9), (25), and (26), the output current can be obtained as:
[
IO =
D
1 − D Vin
O
− (D − d1 ) V2n
2nLLk
]
.(1 − D)(1 − D + d1 )TS =
VO
,
RL
(30)
and:
M =
2nLlk fS
( RL (1
− D + d1 )
D
.
D
+ (D − d1 ) 1 −
2n )
(31)
3.2. Input current ripple
The current of inductances L B1 and L B2 and input current are shown in Figure 5. The average currents of
L B1 and L B2 are I LB1 and I LB2 , respectively, so:
ILB1 = ILB2 =
1
Iin .
2
(32)
Assume that:
LB1 = LB2 = LB .
(33)
I in is the average of the input current. The current ripple of each inductance is obtained as in the following
relation:
Vin DTS
i2 − i1 =
,
(34)
LB
and for i 1 and i 2 it can be said that:
i1 =
Iin
Vin DTS
−
,
2
2LB
(35)
i2 =
Iin
Vin DTS
+
.
2
2LB
(36)
To achieve input current ripple, the maximum and minimum of the input current should be calculated at t 6
and t 9 . At time t 6 the value of I LB2 is i 1 , so:
Vin TS
Iin
V TS
=
− in (D − 1),
2LB
2
2LB
(37)
Vin TS
Iin
Vin TS
(D − 0.5) =
+
(3D − 1).
LB
2
2LB
(38)
iin (t6 ) = i1 +
and at time t 9 :
i2 +
Thus, the input current ripple is obtained as:
∆Iin = iin (t9 ) − iin (t6 ) =
The input current ripple will be zero if D = 0.5.
2190
Vin TS
(2D − 1).
LB
(39)
SALEHI et al./Turk J Elec Eng & Comp Sci
imax
iin
imin
iLB1
iLB2
i2
i1
DTs
Ts/2
(1-D)Ts
(D-0.5)Ts
(1-D)Ts
t3
t6
t9
t 12
Figure 5. Current of input and input inductors.
3.3. ZVS conditions
According to interval 4, when switch S 3 goes off the current of input inductance L B1 flows through the body
diode of S 4 , and the parasitic capacitors of S 4 and S 3 are discharged and charged, respectively. The following
condition should thus be satisfied to ensure ZVS for S 4 :
1
1
2
LB ILB
= LB
2
2
(
Iin
2
)2
(
> COSS
Vin
1−D
)2
.
(40)
C oss is the parasitic capacitor of the switches. This shows that ZVS for switches S 2 and S 4 is achieved for
all load ranges. At t 6 when S 4 turns off, the difference of i LB2 and i lk2 flows through the body diode of S 3 .
Thus:
Iin
−iS3 (t6 ) = ilk2 (t6 ) − iLB2 (t6 ) = i1 − ILB2 =
.
(41)
2
The current of the body diode of S 2 is I in /2, and the ZVS condition is obtained the same as for the switch.
3.4. Boundary between the CCM and DCM
As mentioned before, the proposed converter operates in DCM, but the boundary between DCM and continuous
conduction mode (CCM) for the first leg is at t 5 , where the current of leakage inductance reaches zero. If the
duty cycle is longer than t 5 , the proposed converter goes to DCM, and so the boundary duty (D b ) cycle is
obtained as:
t5 − t0
Db =
= d1 + d2 .
(42)
TS
4. Comparison and experimental and simulation results
A comparison between the L-type half-bridge converter and isolated boost converter that was proposed in [20]
was done in [20] with the following properties: P o = 1 kW, V in = 26-50 V, V o = 400 V, ∆ I in = 10%, f s =
50 kHz.
In this paper, a comparison among the proposed converter, L-type half-bridge converter, and proposed
converter of [24] is presented in the Table, and simulations and experimental results are shown in Figures 6
and 7, respectively. All three converters have the same specifications, except that in the proposed converter the
switching frequency and output voltage ripple are 100 kHz and 0.2%, respectively.
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SALEHI et al./Turk J Elec Eng & Comp Sci
Table. Comparison among proposed converter in [24], L-type half-bridge converter, and proposed converter.
Component
Switch
Design items
Conventional
L-type HB
converter
Proposed
converter in
[20]
Vpk
140 V
90 V
Vstress
140 V
90 V
0.054
Main
Clamp
Main
Clamp
Main
Clamp
Main
Clamp
0.06
400 V
208 V
200 V
I pk
11 A
16 A
PO/(Vpk Ipk q)
0.056
0.15
Turns ratio
1:3.5
76 V
15 A
265 V
4.3 A
Main
Clamp
Main
Clamp
0.037
Ipk
Istress
PO/(Vpk Ipk q)
Vpk
Diode
Output
capacitor
Auxiliary
capacitor
Switching
losses (PU)
51 A
51 A
D1
D2
0.21
12 A
11.4 A
KVA
1140 VA
Capacitance
5.5 µF
Vpk
400 V
139 V
CV (PU)
Inductance
1
17 µH × 2
0.54
13 µH × 2
7 µF × 4
C1
89 V
C2
112 V
0.32
50 µH × 2
Irms
25 A
25 A
16 A
0.76
14 µF × 2
63 V
0.81
1.2
14 µF × 2
54 V
0.60
Main
0.086
Clamp
0.27
Secondary
2
Input
inductor
60 A
35 A
60 A
35 A
137 V
150 V
45 V
150 V
44 A
15 A
16 A
15 A
1:2.5
36.8 V
16.2 A
92.2 V
6.42 A
590
VA 2
7 µF × 4
Primary
Transformer
Proposed
converter
LI2(PU)
Capacitance
Vpk
CV2(PU)
Vrms
Irms
Vrms
Irms
1
7 µF
140 V
1
Main
1
Clamp
0.58
0.55
1:2.5
34 V
16.4 A
85.6 V
6.5 A
555 VA 2
According to the Table, the peak voltage of the proposed converter and the L-type half-bridge converter
are the same and are double the peak voltage of the proposed converter in [24]. Thus, MOSFETs chosen for the
proposed converter would have more R on , and conduction losses in the proposed converter will be greater than
those of the proposed converter in [24]. However, because of the resonance nature, voltage stress at switch S 1 is
half in comparison with the proposed converter in [24], which causes very lower switching losses. Peak current
of the main switch of the proposed converter is lower than that of the other two converters. This difference
for clamp switch and current stress of the switches in the proposed converter is very high, so in the proposed
converter the switching losses are much lower than the others. Because of the resonance nature, current stress
is much lower than the current peak in the main switch. The reverse voltage of the diodes in the proposed
converter is approximately the same as that of the proposed converter in [24]. The utilization factor has been
improved for the switches and diodes in the proposed converter. Input inductors in the proposed converter are
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30
30
20
10
ilk1
Current (A)
Current (A)
40
ilk2
0
−10
iS2
iS1
20
10
0
−10
−20
−30
5 5.002 5.004 5.006 5.008 5.010 5.012 5.014 5.016 5.018 5.020
Time (ms)
−20
5
5.002 5.004 5.006 5.008 5.010 5.012 5.014 5.016 5.018 5.020
Time (ms)
12
8
6
iD1
iD2
Current (A)
Current (A)
10
4
2
0
5 5.002 5.004 5.006 5.008 5.010 5.012 5.014 5.016 5.018 5.020
Time (ms)
Current (A)
−2
28
27.8
27.6
27.4
27.2
27
26.8
26.6
26.4
26.2
265
14
13.8
13.6
13.4
13.2
13
12.8
12.6
12.4
12.2
12
iLB1
5
iLB2
5.002 5.004 5.006 5.008 5.010 5.012 5.014 5.016 5.018 5.020
Time (ms)
iin
5.002 5.004 5.006 5.008 5.010 5.012 5.014 5.016 5.018 5.020
Time (ms)
Figure 6. Simulation waveforms of proposed converter: (a) i lk1 and i lk2 , 5 A/div; (b) i S1 and i S1 , 10 V/div; (c) i D1
and i D2 , 2.5 A/div; (d) i LB1 and i LB2 , 2.5 A/div; (e) I in , 5 A/div.
larger and their energy is greater than in the others, but the output and auxiliary capacitors are the same and
their energy in the proposed converter is lower than in the others.
For switching losses, it is assumed that the base losses are the switching losses of the main switch of the
L-type half-bridge converter, so other switches losses are presented as per unit. According to the Table, the
switching losses of the proposed converter in [24] are two and six times greater than those of the clamp and
main switch in the proposed converter. In the L-type converter the switching losses of the main and clamp
switches are about twelve and two times greater than those of the same switches in the proposed converter.
In this proposed converter leakage inductance of transformers is L k = 2 µ H, and other component values
are mentioned in the Table. Figure 7a shows the current of switches S 1 and S 2 , and the turning on of ZVS
is shown here. As shown in Figure 7a, because of the resonance nature in switch S 1 , current stress is much
lower than the current peak, as mentioned before. In Figure 7b the current of the leakage inductance of the
transformers is shown, and it is clear that the proposed converter works in DCM. In Figure 7c the current of
the output diodes and the turning on and off of ZCS are shown. Because of the ZCS in the output diodes, the
reverse recovery problem of these diodes is alleviated and there is no need for fast diodes anymore. In Figure 7d
the current of input inductors and input current are shown, respectively. According to this figure, the current
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i S1 [30A/div]
i lk1 [30 A/div]
i S2 [30A/div]
i S3 [30A/div]
i lk2 [30 A/div]
i S4[30A/div]
[2.5 µs/div]
[2.5 µs/div]
i D1[15A/div]
i LB1 [10A/div]
i LB2 [10A/div]
i in [10A/div]
i D2 [15A/div]
[2.5µs/div]
[2.5µs/div]
Figure 7. Exprimental waveforms of the proposed converter: (a) i lk1 and i lk2 , (b) i S1 and i S1 , (c) i D2 and i D2 , (d)
i LB1 , i LB1 , and I in .
of input inductors by half-period time delay causes lower ripple at the input current. Voltage gain against duty
cycle for some leakage inductance values is plotted in Figure 8. Here the boundary duty cycle between DCM
and CCM is about 0.4. According to Figure 8, the proposed converter can be controlled by the duty cycle in
both DCM and CCM. The efficiency of the proposed converter and the converter in [24] is plotted in Figure
9. Maximum efficiency of the proposed converter is 97.9%, which occurs at 320 W output power, and full load
efficiency is 95.7%.
5. Conclusion
In this paper an interleaved quasi-resonant current-fed converter is proposed and compared with two other
converters. Voltage and current stress of the proposed converter are lower than those of the others and so
switching losses in the turn-off state are improved. Because of ZVS in the turn-on state, it has minimum
switching losses. As a result of ZCS in the output diodes, the reverse recovery problem is alleviated and diode
switching losses are reduced. Because of this reduction of losses, efficiency is improved. A major disadvantage
of resonant converters is their control complexity. In this paper, the proposed converter works in DCM, so, as
is proved before, it can be controlled by the PWM method and therefore its control complexity is reduced.
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100
98
25
96
Voltage gain (M)
CCM
DCM
15
L=2 µH
L=3 µH
L=4 µH
L=6 µH
L=8 µH
L=12 µH
10
5
0
0
Efficiency (%)
L=1 µH
20
0.1
0.2
0.3
0.4 0.5 0.6
Duty cycle (D)
0.7
0.8
0.9
94
92
90
88
86
Proposed Convertrt
Proposed Converter in [20]
84
1
Figure 8. Output voltage against duty cycle for various
leakage inductances.
82
0
100
200
300
400 500 600 700
Output power (w)
800
900 1000
Figure 9. Efficiency at different output power.
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