CoPEC
Custom IC Blocks for Enabling
Digital Control in
Switching Power Converters
Dragan Maksimovic and Regan Zane
July 11, 2003
Colorado Power Electronics Center
University of Colorado, Boulder
July 11, 2003
1
Outline
CoPEC
• Motivations & CoPEC directions
• “Buffalo switcher”
– Complete 1 MHz digital PWM controller IC
– Hybrid digital PWM
– Delay-line A/D
• CoPEC research highlights
• Education:
– focus on power electronics & mixed-signal IC
design
July 11, 2003
2
Power Electronics Applications
CoPEC
Portable devices
• On-chip power management /mW
• Power supplies for LCD-s / hundreds of mW
• Switching voltage regulators/ up to tens of Watts
Computers and Consumers Electronics
• Power supplies for components/ several watts
• Micro-processor supplies: Voltage Regulator
Modules (VRMs)/ up to hundreds of Watts
• Off-line power supplies / up to kW
Telecomm. equipment
Industrial
Automotive
Lighting (HID, fluorescent)
Aerospace
July 11, 2003
3
PDA Example: Power Management
USB
Memory
Expansion
SDRAM
SRAM
FLASH
ROM
Power
Power
Switch
Switch
Logic
Bus Drvr
Wired I/F
Bluetooth
Audio
Audio
Codec
Codec
Wireless
Access
Wireless
Ethernet
802.11b
Wireless I/F
Processing
Core
1.5 / 1.8V / 2.5V
Core Supply
3.3V / 5V
System Supply
Supply
Buck
SupplyVoltage
Voltage Low-Dropout
Low-Dropout
Buck
Supervisor
Regulator
Converter
Supervisor
Regulator
Converter
Power Management
July 11, 2003
Touchscreen
Touchscreen
Control
Control
Buck-Boost
Boost
Buck-Boost
Boost
Converter
Converter
Converter
Converter
Battery
Battery
Monitor
Monitor
Battery
Li+ Ni+ Alkaline
Li-Ion
Li-Ion
Protector
Protector
Battery
Battery
Battery
Charger
Management
Charger
Microphone
Microphone
Amp
Amp
Microphone
Audio
AudioPwr
Pwr
Amp
Amp
Loudspeaker
Headphones
CoPEC
Color or B/W LCD
with Touchscreen
Frontlight Backlight
White LED CCFL
Charge
Charge
Pump
Pump
CCFL
CCFLCtrl
Ctrl
Wall Supply
USB Power
4
CoPEC
Buck Switching Converter Example
Control
L
M
+
Vin
+
C
vD
_
vD(t)
Vin
Vout
Load
M -state ON
Ts
OFF
pulse width
modulator
compensator
Power Processing
Vout = DVin
July 11, 2003
switching
converter
Load
d(t)
t
DTs
•
•
•
•
•
Vin
Vout
- Vref
+ +
e(t)
Controller
Duty ratio
Switching operation controls the average value of vD
LC low-pass filter reduces the voltage ripple in the dc output Vout
High switching frequency (hundreds of kHz to MHz), small size
Ideally lossless, very high efficiency in practice
Tightly regulated Vout through a feedback loop
5
Controller Implementation: Analog vs. Digital
Analog Implementation
+
C
D
July 11, 2003
D
C
H
H
Hvout(t)
vc(t)
t
saw-tooth
waveform
generator
e(t)
error amplifier
and compensator
Hvout(t)
DPWM
d[n]
-
+
Vref
Analog controller
R
-
driver
comparator
Ts
Vin
+
-
driver
VM
vout +
+
R
-
+
L
M
vout +
+
Vin
Digital Implementation
L
M
CoPEC
Compensator
d[n]=f{d[n-1], d[n-2],..,e[n],e[n-1]..}
Digital Controller
A/D
e[n]
+
Hvout[n]
Vref[n]
6
Research Motivation – Why Digital?
CoPEC
• Analog PWM controllers (30 year old technology)
• Simple, low-cost
• Well established design practices
• What can be accomplished with digital control in power
electronics applications?
• Programmability (e.g. one controller can serve a much
wider range of applications)
• Elimination or reduction of the number of passive
components
• System integration (e.g. dynamic voltage scaling),
diagnostics, etc.
• Static and dynamic performance (e.g. through adaptive
control techniques)
• Reduced sensitivity to tolerances, process and
temperature variations
• Reduced cost
July 11, 2003
7
Practical Limitations
+
Switching
Converter
V in
Load
v out
-
n dpwm
Digital Controller
could be simpler than a high-speed,
• Processing unit -Available
Digital Pulse W idth
M odulator
text
• A/D –A complete analog controller
high-resolution A/D
d[n]
Processing
Unit
CoPEC
microcontroller/DSP systems are still
n a/d
A/D
too slow, or too complex/costly
• DPWM – High-speed/ High-resolution
(ns) digital pulse width modulators are
needed
New design and implementation approaches for all functional
blocks are needed
July 11, 2003
8
CoPEC Research Program
CoPEC
Power Electronics and Mixed-Signal IC Design
Pin
New converter configurations tied
to more sophisticated control
techniques
Switching power converter
Gate-drive waveforms
Programmable
digital
modulators
Pout
Voltage/current sensing
Hardwareaccelerated
computational
unit
Small, fast,
scalable A/D
converters
Serial I/O
Standard µC or DSP core and peripherals
Digital signal transmission
across isolation boundary
New SMPS-specific
controller building
blocks
New controller
architectures for
wide range of
applications
Digital SMPS controller
Converter/controller co-design for
significant gains in performance, size
and/or cost:
• reduced size of passive components
• improved efficiency
• improved dynamic responses, etc.
July 11, 2003
System interface
New control algorithms
• parameter/state estimation
• adaptive control
• nonlinear control, etc.
Modeling techniques
9
Examples of CoPEC Research Results
CoPEC
• Complete 1 MHz digital PWM controller IC
– small size, programmable compensator, no discretes
• Standard-cell based A/D converter ICs
– small size, fast sampling, scalable with digital technology
• Digitally controlled 3.3 V, 20 A DC power supply
– chipset for isolated DC power supplies
• Digital predictive current-mode control
– very fast response
– applications to PFC and DC-DC converters
• Digitally-controlled power-factor correction rectifiers
– order-of-magnitude improvement in dynamic response
July 11, 2003
10
CoPEC
Buffalo Switcher
Complete High-Frequency Digital
PWM Controller IC
Delay-line A/D
Vg
L
+
–
+
C
Vo
_
DPWM, Compensator,
Memory interface
Switching power converter
fs = 1MHz
c(t)
Vsense
OUT
SENSE
e
d
Hybrid
DPWM
Compensator
(look-up table)
Vref
Digital controller IC
External
memory
July 11, 2003
Delay-line
A/D
•
•
•
•
•
•
1 MHz switching frequency
Programmable compensator
0.5µ CMOS technology
Chip area: 0.96 mm2
All-digital, HDL-based design
Standard digital design flow:
• HDL (Verilog) based design
• Synthesis to standard-cell gates
• Automated place & route
11
CoPEC
Chip architecture
fs = 1/Ts
dTs
c(t)
Vsense
Ts
SENSE
OUT
DPWM
Digital
pulse-width
modulator
d[n+1]
+
d[n]
Table A
Ts
Table B
Ts
e[n-1]
Ts
Table C
System
clock
e[n] +4
+3
+2
+1
0
-1
-2
-3
-4
e[n-2]
Programmable compensator
e
Vq
Vref
Vo
Vref
(∆Vo)max
A/D converter
Look-up table programming interface
External memory
July 11, 2003
12
CoPEC
A/D requirements
Static voltage regulation
e
Only a few
digital error
outputs
needed
Vq ≤ ∆Vo
Vq
+4
+3
+2
+1
0
-1
-2
-3
-4
Vo
Vref
(∆Vo)max
Dynamic voltage regulation
July 11, 2003
small conversion range
13
CoPEC
Delay-line A/D
Delay td versus VDD
Analog input is the supply voltage
VDD for a chain of logic gates
1200
1000
Analog input Vsense
SENSE
test
td (ps)
800
VDD
VDD
VDD
VDD
VDD
R
R
R
R
R
600
400
delay
cell
200
0
0
1
2
3
4
5
VDD
t1
t2
D Q
t3
D Q
t8
D Q
D Q
sample
q1
q2
q3
Encoder
Digital output e
July 11, 2003
q8
Digital output q
(in “thermometer” code)
Digital output e
14
Delay-line A/D Operation
Start
conversion
CoPEC
End
conversion
test
t1
t2
td
1
1
t3
1
t4
1
1
t5
t6
t7
1
0
t8
0
q = {11111100}
e = -2
sample
0
July 11, 2003
Ts
15
Delay-line A/D Experimental Results
Vq = 53mV, σ = 3.6mV
fs = 1 MHz sampling
Error e
+4
e
Zero-error bin
+3
Vq
+2
+1
0
–1
–2
–3
–4
Vsense
Vref – 0.2 V
Vref – 0.1 V
Vref
Vref +0.1 V
Vref +0.2 V
Sampled output voltage Vsense
July 11, 2003
CoPEC
Advantages:
• Small area/low power
• Averaging over
conversion time
• All digital
implementation
Problem:
• Basic configuration is
highly susceptible to
process/temperature
• How to implement
calibration to a reference
voltage?
16
CoPEC
Strobe-Calibrated Delay-Line A/D
Vsense
delay
block
2
delay
block
1
delay input
delay
block
N/2
delay
block
N-1
delay
block
N
reset
D
Vref
D
Q
Strobe Delay
D
Q
D
Q
D
Q
Q
strobe
therm<0>
therm<1>
therm<N/2>
therm<N-1>
therm<N>
• Delay blocks constructed with standard cells
• Matched “strobe delay” added to provide selfcalibrated reference point
July 11, 2003
17
CoPEC
Strobe-Calibrated Delay-Line A/D Exp Results
July 11, 2003
9
8
7
Output Code
• 1.8 V reference
• 250ns typical
conversion time (500ns
worst case)
• Standard-cell HDLbased design, 0.5µ
CMOS process
• Automated place-androute of primary and
matched delay lines
• Tested over the
temperature range from
-40ºC to 100ºC
6
5
4
3
2
1
0
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
Vsense
Experimental characteristics over temperature
18
CoPEC
Strobe-Calibrated Delay-Line A/D Exp Results
Histogram of the measured offset over
18 prototype chips
July 11, 2003
• Average offset: 1.56mV
(4% LSB)
• 11 of 18 chips < 2 mV
offset
• Good performance holds
over temperature
• The worst offset prototype
chip of 18 samples at the
worst temperature corner:
-7.3 mV offset
• Total current
consumption:
– less than 100 µA
19
CoPEC
Look-up Table Based
Programmable Compensator
Duty-cycle d[n+1]
to
DPWM 8-bit
+
d[n]
e[n]
Table A
Ts
Table B
Ts
Error
from
A/D
e[n-1]
Ts
Table C
e[n-2]
Programmable compensator
External memory
PID compensator: d[n+1] = d[n] + a e[n] + b e[n-1] + c e[n-1]
•“Zero” steady-state error
•Programmable response
•Very small area, very low power
July 11, 2003
Table A
Table B
Table C
20
Conventional Counter-based DPWM Design
N-bit Counter
nDPWM
A
Comparator
in=A
Incr.
Comparator
in=0
Set
Reset
CoPEC
clock
f clk ≥ 2 N DPWM ⋅ f s
fsw: switching frequency
fclk: processor clock frequency
nDPWM: number of bits of DPWM
DPWM
d[n]
10-bit @ 1 MHz => 1 GHz clock signal!?
July 11, 2003
21
CoPEC
High-Resolution Hybrid DPWM
Combines a delay line (ring oscillator) with a counter to reduce the
maximum clock speed
Conventional DPWM:
fclk = 2n ⋅ fs
Hybrid DPWM:
fs ≤ fclk ≤ 2n ⋅ fs
Prototype:
n = 8 bits
fs = 1 MHz
fclk = 8 MHz
July 11, 2003
+VDD
R
D Q
R
D Q
Q1
Q0
d[1:0]
input
d[3:0]
0
1
2
nd
R
D Q
nd
2
:1 MUX
R
D Q
Q2
+1 out[1:0]
cnt[1:0]
Q3
nc
nc-bit
comparator 1
(a ?= b)
3
a[1:0]
n
nc
system
clock
2-bit
counter
b[1:0]
out
(a=b)
d[3:2]
nc-bit
comparator 2
(a ?= b)
cnt[1:0]
a[1:0] out
nc
(a=b)
b[1:0]
Reset
Set
R
Q
S
c(t)
OUT
22
CoPEC
DPWM Experimental Results
Output duty ratio [%]
100
90
80
70
60
50
40
30
20
10
0
July 11, 2003
0
32
64
96
128
160
DPWM input (decimal)
192
224
255
23
CoPEC
High-Resolution Hybrid DPWM
Hybrid DPWM combines a delay line (ring oscillator) with a
counter to reduce the maximum clock speed
Conventional DPWM:
fclk = 2n ⋅ fs
n = 8 bits
fs = 1 MHz
fclk = 256 MHz
Hybrid DPWM:
fs ≤ fclk ≤ 2n ⋅ fs
Buffalo switcher hybrid
DPWM prototype:
n = 8 bits
fs = 1 MHz
fclk = 8 MHz
July 11, 2003
+VDD
R
D Q
R
D Q
Q1
Q0
d[1:0]
input
d[3:0]
0
1
2
nd
R
D Q
nd
2
:1 MUX
R
D Q
Q2
+1 out[1:0]
cnt[1:0]
Q3
nc
nc-bit
comparator 1
(a ?= b)
3
a[1:0]
n
nc
system
clock
2-bit
counter
b[1:0]
out
(a=b)
d[3:2]
nc-bit
comparator 2
(a ?= b)
cnt[1:0]
a[1:0] out
nc
(a=b)
b[1:0]
Reset
Set
R
Q
S
c(t)
OUT
4-bit hybrid DPWM example
24
10-bit DPWM With Programmable Frequency
CoPEC
Delay line
fsel[1:0]
DQ
clr
Vdd
Power On
reset-start
ndpw
delay
delay
DQ
clr
DQ
clr
delay
DQ
clr
delay
reset
start
Input register
[9:0]
reset
reset
reset
I0
in [4:0]
32:1 Multiplexer
in[9:0]
A
reset
I31
I1
B
10-bit NOR
inc.
5-bit counter
in[9:5]
A
B
5-bit comp.
cnt[4:0]
Vdd
B
A
5-bit OR
delay block
cnt[4]
DQ
clr
in
I0
S0
fsel[1]
fsel[0]
S
I2
I3
4:1 Multiplexer
S1
I7
I1
out
Q
DPWM
R
MR
Delay- line/counter combination provides low power consumption, low
on-chip area and high resolution at high frequencies
July 11, 2003
25
10-Bit Hybrid DPWM Implementation
CoPEC
• 10-bit resolution
• Programmable switching
frequency: 750 kHz, 400 kHz,
200 kHz and 100 kHz/ 1.3 ns
resolution
• 32 times higher clock frequency
• 0.5µ CMOS
• Active chip area: 0.16 mm2
• Completely HDL coded
July 11, 2003
26
Experimental Digitally Controlled Power Supply
CoPEC
Vg
L
+
–
+
C
Vo
_
4 V < Vg < 6 V
Switching power converter
fs = 1MHz
c(t)
OUT
Hybrid
DPWM
Vsense
e
d
Compensator
(look-up table)
L = 1 µH, C = 22 µF
SENSE
Delay-line
A/D
Vo = 2.7 V +/- 25 mV
0 < Io < 1.5 A
fs = 1 MHz
Vref
Digital controller IC
External
memory
July 11, 2003
27
CoPEC
Experimental Results
Vo – Vref [mV]
Output voltage error
+30
+20
Static line regulation
Vo(t) [50 mV/div]
+10
0
–10
Vq
–20
Vg [V]
–30
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Input voltage
Vo – Vref [mV]
Output voltage error
+30
Io(t) [1 A/div]
1A
+20
+10
0A
0
–10
–20
–30
Static load regulation
0
0.2
0.4
0.6
0.8
1.0
1.2
Io [A]
1.4
1.6
1.8
Load Transient Response
2.0
Load current
July 11, 2003
28
Conclusions
CoPEC
• Complete 1 MHz digital PWM controller IC
• New architecture and HDL-based design of the key building
blocks:
– Calibrated delay-line A/D
– Programmable look-up table compensator
– Hybrid DPWM
• Small area, low power, fast response
• Design scales with digital technology
• Open possibilities for a new generation of controller ICs
(standard parts and ASICs) for power electronics
July 11, 2003
29
Extension: Digital Chipset for Isolated Power Supply
CoPEC
Analog implementation
Isolated DC-DC switching converter
1:n
Vin
vout
Secondary
C
side
Primary side
c(t)
e(t)
Modulator
Opto-coupler
+
+
-
load
• Opto-coupler operates in linear
mode
H
Hvout
Vref
Digital solution based on serial communication
Isolated DC-DC switching converter
1:n
Vin
Primary side
Secondary
C
side
• Transfers just the error signal
H
DPWM
e[n]
Tx
Rx
Opto-coupler
July 11, 2003
mode (as a logic gate)
+
c(t)
regulator
• Opto-coupler operates in digital
vout
e[n]
Hvout
A/D
Vref[n]
• Potential for less conservative
design of the feedback loop
30
Isolated DC-DC: Test System
CoPEC
Tyco HW 100F
• Isolated converter
• 36 V ÷ 72 V to 3.3 V
• up to 20 Amps load
• 400 kHz switching
frequency
d[n]
fsel[1:0]
DPWM
ndpw
Regulator
Primary side IC
July 11, 2003
16 x fsw
e[n]
Serial
receiver
clk_out
clk_in
oc1
ser_in
oc2
ser_out
Vref
+
e[n]
Serial
transmitter
• Replaced original analog
current-mode controller on
the board
Secondary side IC
31
CoPEC
Experimental Results
output voltage
output voltage
load current
50%
25%
50%
25%
Original analog controller
July 11, 2003
load current
Digital controller IC set
32
CoPEC
Digital Controller for AC/DC PFC
+
Switching Power Converter
Vin
vo(t)
Rectified AC line
voltage input
Load
-
vin(t)
ig(t)
A/D
Analog/Digital
Interface
DPWM
A/D
vin[n]
vo(t)
d(t)
ig[n]
A/D
d[n]
vo[n]
v
L
d [ n] = 2 − d [ n − 1] −
(ig [n − 1] − iref ) − 2 in
VTs
V
Deadbeat Control
iref [n]
1 N
x[ n ]
N n=1
s[n]
y[n]
comparator
u[n]=avu[n-1]+Kv(bvev[n]cvev[n-1])
Voltage loop regulator
July 11, 2003
ev[n]
(1 − rz −1 ) ⋅ (1 − z − ( M +1) )
H (z) =
(1 − z −1 ) ⋅ (1 − r −( M +1) z −1 )
Comb Filter
Sampling frequency
selector
vo[n]
e[n]
+
- V [n]
ref
+
Computational Unit
33
CoPEC
PFC Experimental Results (current loop)
Line frequency: 800Hz
Switching frequency: 200KHz
THD: 2.2%
July 11, 2003
Switching frequency: 100KHz
THD: 2.4%
Dead-beat digital current mode control: near-perfect PFC
even in demanding next-generation avionics applications
(AC system with the line frequency up to 800 Hz)
34
CoPEC
PFC Experimental Results (voltage loop)
Output voltage
Conventional
voltage loop
High-bandwidth loop with and
without a notch filter
Load current
Line current
Without comb
THD > 20%
With comb
THD = 4.3%
Output voltage
With STCF
Load current
Line current
July 11, 2003
35
CoPEC
Other CoPEC Research Projects (2003)
• Advanced digital control of DC-DC converters
High-performance predictive digital current-mode control for DC-DC converters
(TI)
• Power management for low-power electronics
Digital DC-DC switcher for battery-powered systems (NSC)
Adaptive DC-DC converters for RF power amplifiers (DARPA)
Adaptive DC-DC converters and power management architecture for base-band
µP/DSP (NSF, NSC)
Energy harvesting for wireless sensors and Implantable sensors for neuronal
recording (Coleman Institute)
• Microprocessor power supplies
Multi-phase digital controller for microprocessor power supplies (Artesyn)
• Off-line switching power supplies
Modular mixed-signal control for electronic ballasts (GE)
Digital controllers for solar/utility power system (Philips)
Digitally controlled matrix converters for wind power system (NREL)
July 11, 2003
36
CoPEC Educational Program Objectives
CoPEC
• Strong undergraduate and graduate programs in
power electronics and mixed-signal IC design
• Internship and job opportunities for students
• Continuing education
– Courses available through CATECS
– Certificate program in power electronics
• Technology transfer to CoPEC sponsors
– Jointly defined and directed projects
– Access to CoPEC IP
July 11, 2003
37
CoPEC
Growth of Program: Enrollment
Enrollment for Analog IC Design, Spring 2002: 31, Spring 2003: 66
Enrollment for Mixed-Signal IC Design, Fall 2002: 15
Our visibility is increasing, and we are attracting more students to the
power electronics and micro-electronics areas
July 11, 2003
38
CoPEC
Growth of Program: Graduate Students
Power Electronics Program
16
Number of graduate students
14
12
other
10
TA
8
other RA
6
CoPEC RA
4
2
0
2000
2001
2002
2003
Year
With increased visibility and availability of projects, we are able to
attract better students into our program
July 11, 2003
39
CoPEC
Mixed-Signal IC Design Flow
4228/5008: Analog IC
• Spring 2003
• Analog portion only
System/Application Specification
IC Specification
IC Functional Description
Analog/Digital Distribution
Functional Analog
Analog
Sim
Circuit & Verilog-A
Mixed-Signal
Simulation
Functional Digital
Verilog/VHDL
Synthesis
Complete Analog
Digital
Sim
Complete Design
5007: Mixed-Signal IC
• Fall 2003
• Full System
• Emphasis on mixed blocks
July 11, 2003
Verification
Layout
LVS, Extraction
Custom, Place & Route, DRC
Tape-Out
40
Analog IC Course Outline
CoPEC
• Week 1: Review circuits I-II
• Text Ch. 1, Appendix A & C; Supplementary notes
• Week 2: Review CMOS technology and device models
• Text Ch. 2-3
• Weeks 3-4: Analog CMOS sub-circuits
• Text Ch. 4
• Weeks 5-7: CMOS amplifiers
• Text Ch. 5
• Weeks 8-10: CMOS operational amplifiers
• Text Ch. 6
• Weeks 11-13: High-performance CMOS op-amps
• Text Ch. 7
• Weeks 14-15: Comparators and select advanced topics
• Text Ch. 8, Supplementary notes
Text used: Allen/Holberg, Gray/Meyer, Johns/Martin
July 11, 2003
41
Mixed-Signal IC Lecture Topics
Comparators
• 2-stage amp, hysteresis, latched, high-speed
Sample & Hold Circuits
Discrete-Time Signals (Fundamentals)
Sampled-Data Circuit Techniques
• SC & SI Circuits: Filter Design, Amplifiers,
Applications
• Non-idealities: clock-feedthrough, matching
Data Converters
• Fundamentals
• Nyquist Rate D/A, A/D
• Oversampling Converters
System Level IC Design
• System Description & Specification
• IC Functional Specification
• Top Down & Bottom Up Methodologies
• System Planning: fabrication options, foundry
selection, silicon area estimation, packaging
options, prototype and production cost & time
estimation
• Design for Testability
• Reviews: data sheet preparation, design reviews,
risk analysis
July 11, 2003
CoPEC
System Simulation
•
Software Preparation: technology files, model
files, standard cell libraries, software setup
•
Functional Simulation: Verilog-A and Verilog
HDL languages, hierarchical designs with multiple
cell-views
• Mixed-Signal Simulation: co-simulation of analog
& digital, functional and circuit level blocks in the
Cadence tools
• Ballast Controller & PLL Case Studies
Physical Layer (time & setup permitting)
• Floorplanning & Layout: custom and semi-custom
layout in Cadence
• Practical Considerations: matching, digital/analog
isolation, latch-up, ESD and pad design, power
distribution, noise coupling
• Verification: LVS, DRC, extracted simulation
• Fabrication: GDSII extraction to foundry
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Mixed-Signal IC Final Project
CoPEC
• Select a mixed-signal project that targets a specific application
• Work in teams of 1 to 4
• Deliverables include:
• Proposal: Create a final project website with an overview of the target
application, preliminary IC specifications, and a functional description
Industry
Involvement
(?)
of the digital & Local
analog IC
blocks – Due
Oct 17
• Suggest
project/research
• Functional Design
Review:relevant
In-class presentation
on your topics
results to
date, which must
include
systemwith
level simulations
verifying
• Be
involved
design and/or
finalyour
functional blocksreviews
in the application environment. Simulations must
include at least one
blockfabrication
of each: Verilog-A,
holdand a
• Fund
of best Verilog
designsor VHDL,
circuit level block. Include your presentation and simulation files on
competition?
your project website.
Reviews Scheduled Nov 5-14
• Final Design Review: Final in-class presentation on your project. The
complete “front-end” design of the projects must be complete, ready
for transition to a layout engineer. Time permitting, various phases of
layout and verification may be required as well.
July 11, 2003
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