Intrinsic Silicon Properties
• Read textbook, section 3.2.1, 3.2.2, 3.2.3
• Intrinsic Semiconductors
– undoped (i.e., not n+ or p+) silicon has intrinsic charge
carriers
– electron-hole pairs are created by thermal energy
– intrinsic carrier concentration ≡ ni = 1.45x1010 cm-3,
at room temp.
– function of temperature: increase or decrease with temp?
– n = p = ni, in intrinsic (undoped) material
• n ≡ number of electrons, p ≡ number of holes
– mass-action law, np = ni2
• applies to undoped and doped material
ECE 410, Prof. A. Mason
Lecture Notes 6.1
Extrinsic Silicon Properties
• doping, adding dopants to modify material properties
– n-type = n+, add elements with extra an electron
• (arsenic, As, or phosphorus, P), Group V elements
•
•
•
•
nn ≡ concentration of electrons in n-type material
nn = Nd cm-3, Nd ≡ concentration of donor atoms
pn ≡ concentration of holes in n-type material
Nd pn = ni2, using mass-action law
– always a lot more n than p in n-type material
– p-type = p+, add elements with an extra hole
• (boron, B)
• pp ≡ concentration of holes in p-type material
• pp = Na
cm-3,
Na ≡ concentration of acceptor atoms
• np ≡ concentration of electrons in p-type material
• Na np = ni2, using mass-action law
– always a lot more p than n in p-type material
– if both Nd and Na present, nn = Nd-Na, pp=Na-Nd
ECE 410, Prof. A. Mason
n-type Donor
+
P
group V
element
-
P+
electron
free
carrier
ion
n+/p+ defines region
as heavily doped,
typically ≈ 1016-1018 cm-3
less highly doped regions
generally labeled n/p
(without the +)
p-type Acceptor
-
B
group III
element
B+
ion
+
hole
free
carrier
do example on board
ni2 = 2.1x1020
Lecture Notes 6.2
Conduction in Semiconductors
• doping provides free charge carriers, alters conductivity
• conductivity, σ, in semic. w/ carrier densities n and p
– σ = q(μnn + μpp), q ≡ electron charge, q = 1.6x10-19 [Coulombs]
• μ ≡ mobility [cm2/V-sec], μn ≅ 1360, μp ≅ 480 (typical values)
• in n-type region, nn >> pn
– σ ≈ qμnnn
• in p-type region, pp >> np
– σ ≈ qμpnp
mobility = average velocity per Mobility often
assumed constant
unit electric field
μn > μp
electrons more mobile than holes
⇒conductivity of n+ > p+
• resistivity, ρ = 1/σ
• resistance of an n+ or p+ region
– R = ρ l , A = wt
but is a function of
Temperature and Doping
Concentration
t
w
A
l
• drift current (flow of charge carriers in presence of an electric field, Ex)
– n/p drift current density: Jxn = σn Ex = qμnnnEx, Jxp = σp Ex = qμpppEx
– total drift current density in x direction Jx = q(μnn + μpp) Ex = σ Ex
ECE 410, Prof. A. Mason
Lecture Notes 6.3
pn Junctions: Intro
• What is a pn Junction?
boundaries
– interface of p-type and
pn diode
n-type semiconductor
junction
– junction of two materials forms a diode
p-type -
– ionization of dopants
at material interface
contact
to n-side
p+
n+
depletion region
+
+
+
+
- - -
dielectric
insulator
(oxide)
n “well”
p-type Si wafer
p-type
• In the Beginning…
contact
to p-side
n-type
+
-
+
+
+
- - - + -+ - + - +
3
NA acceptors/cm
-
-
n-type
+
-
-
-
+
+
+
3
ND donors/cm
-
hole diffusion
hole current
electron diffusion
electron current
+
+
-
+
donor ion and electron free carrier
acceptor ion and hole free carrier
• Diffusion -movement of charge to regions of lower concentration
– free carries diffuse out
– leave behind immobile ions
– region become depleted of
free carriers
– ions establish an electric field
• acts against diffusion
electric field
depletion region
p-type
3
NA acceptors/cm
immobile acceptor ions
(negative-charge)
-
E
- + ++
- + +
- +
- + +
xp
xn
n-type
3
ND donors/cm
immobile donor ions
(positive-charge)
W
ECE 410, Prof. A. Mason
Lecture Notes 6.4
pn Junctions: Equilibrium Conditions
electric field
• Depletion Region
depletion region
E
- - + +
n-type
p-type
– area at pn interface
+
- - - + + + ND
NA
void of free charges
- - + +
N acceptors/cm
N donors/cm
– charge neutrality
x
x
immobile acceptor ions
immobile donor ions
(positive-charge)
• must have equal charge on both sides (negative-charge)
W
• q A xp NA = q A xn ND , A=junction area; xp, xn depth into p/n side
• ⇒ xp NA = xn ND
• depletion region will extend further into the more lightly doped side
of the junction
3
3
A
D
p
n
• Built-in Potential
– diffusion of carriers leaves behind immobile charged ions
– ions create an electric field which generates a built-in potential
⎛ NAND
Ψ0 = VT ln⎜⎜
2
n
⎝ i
⎞
⎟
⎟
⎠
• where VT = kT/q = 26mV at room temperature
ECE 410, Prof. A. Mason
Lecture Notes 6.5
pn Junctions: Depletion Width
electric field
• Depletion Width
depletion region
use Poisson’s equation & charge neutrality
p-type
– W = xp + xn
⎡ 2ε (Ψ0 + VR )N D ⎤
xp = ⎢
⎥
(
)
qN
N
N
+
A ⎦
⎣ A D
NA
1
2
⎡ 2ε (Ψ0 + V R )N A ⎤
xn = ⎢
⎥
qN
N
N
+
(
)
A ⎦
⎣ D D
• where VR is applied reverse bias
⎡ 2ε (Ψ0 + VR ) N D + N A ⎤
W =⎢
⎥
q
N
N
D
A ⎦
⎣
1
2
1
3
NA acceptors/cm
2
immobile acceptor ions
(negative-charge)
-
E
n-type
- + ++
- + + N
D
- +
N donors/cm
- + +
3
D
xp
xn
immobile donor ions
(positive-charge)
W
⎛N N
Ψ0 = VT ln⎜⎜ A 2 D
⎝ ni
⎞
⎟
⎟
⎠
ε is the permittivity of Si
ε = 1.04x10-12 F/cm
ε = KSε0, where ε0 = 8.85x10-14 F/cm
and KS = 11.8 is the relative permittivity of silicon
• One-sided Step Junction
⎡ 2ε (Ψ0 + V R ) ⎤
– if NA>>ND (p+n diode)
W ≅ xn = ⎢
⎥
qN
• most of junction on n-side
D
⎣
⎦
– if ND>>NA (n+p diode)
1
2
⎡ 2ε (Ψ0 + VR ) ⎤
• most of junction on p-side W ≅ x p = ⎢
⎥
qN
A
⎣
⎦
ECE 410, Prof. A. Mason
1
2
Lecture Notes 6.6
pn Junctions - Depletion Capacitance
• Free carriers are separated by the depletion layer
• Separation of charge creates junction capacitance
– Cj = εA/d ⇒ (d = depletion width, W)
1
⎞ ε is the permittivity of-12Si
⎡ qεN A N D ⎤ 2 ⎛⎜
1
⎟ ε = 11.8⋅ε0 = 1.04x10 F/cm
C j = A⎢
⎥ ⎜
⎣ 2(N A + N D ) ⎦ ⎝ Ψ0 + VR ⎟⎠ VR = applied reverse bias
– A is complex to calculate in semiconductor diodes
• consists of both bottom of the well and side-wall areas
– Cj is a strong function of biasing
• must be re-calculated if
bias conditions change
⎛
⎜
⎜ C jo
Cj = ⎜
VR
⎜
⎜ 1+ Ψ
0
⎝
– CMOS doping is not linear/constant
• graded junction approximation
• Junction Breakdown
⎞
⎟
1
⎟
2
⎡
⎤
qεN A N D
⎟ C = A
jo
⎢
⎥
⎟
⎣ 2Ψ0 ( N A + N D ) ⎦
⎟
⎠
⎛
⎜
⎜ C jo
Cj = ⎜
VR
⎜3
⎜ 1+ Ψ
0
⎝
⎞
⎟
⎟
⎟
⎟
⎟
⎠
– if reverse bias is too high (typically > 30V) can get strong reverse current flow
ECE 410, Prof. A. Mason
Lecture Notes 6.7
Diode Biasing and Current Flow
+ VD p
+ VD -
n
ID
•
ID
Vf
ID
VD
Forward Bias; VD > Ψ0
– acts against built-in potential
– depletion width reduced
– diffusion currents increase with VD
• minority carrier diffusion
(
ID = IS e
•
VD VT
)
−1
⎛ 1
1 ⎞
⎟⎟
I S ∝ A⎜⎜
+
N
N
A ⎠
⎝ D
Reverse Bias; VR = -VD > 0
–
–
–
–
acts to support built-in potential
depletion width increased
electric field increased
small drift current flows
• considered leakage
• small until VR is too high and breakdown occurs
ECE 410, Prof. A. Mason
Lecture Notes 6.8
MOSFET Capacitor
• MOSFETs move charge from drain to source underneath the gate,
if a conductive channel exists under the gate
• Understanding how and why the conductive channel is produced is
important
• MOSFET capacitor models the gate/oxide/substrate region
– source and drain are ignored
– substrate changes with applied gate voltage
• Consider an nMOS device
– Accumulation, VG < 0, (-)ve charge on gate
G
S
D
G
gate
gate oxide
channel
Si substrate = bulk
• induces (+)ve charge in substrate
• (+)ve charge accumulate from substrate holes (h+)
– Depletion, VG > 0 but small
V <0
• creates depletion region in substrate
------• (-)ve charge but no free carriers
+++++++
– Inversion, VG > 0 but larger
• further depletion requires high energy p-type Si substrate
B
• (-)ve charge pulled from Ground
Accumulation
• electron (e-) free carriers in channel
G
ECE 410, Prof. A. Mason
=
B
B
VG >> 0
VG > 0
+++++++
+++++++++++
++++++++++
-------
-- --- -- --- -- --- --
p-type Si substrate
p-type Si substrate
depletion layer
depletion layer
B
B
Depletion
Inversion
Lecture Notes 6.9
Capacitance in MOSFET Capacitor
• In Accumulation
– Gate capacitance = Oxide capacitance
– Cox = εox/tox [F/cm2]
• In Depletion
– Gate capacitance has 2 components
– 1) oxide capacitance
– 2) depletion capacitance of the substrate depletion region
• Cdep = εsi/xd, xd = depth of depletion region into substrate
Cox
Cdep
– Cgate = Cox (in series with) Cdep = Cox Cdep / (Cox+Cdep) < Cox
• C’s in series add like R’s in parallel
• In Inversion
– free carries at the surface
– Cgate = Cox
Cgate
Cox
accumulation
inversion
VG
depletion
ECE 410, Prof. A. Mason
Lecture Notes 6.10
Inversion Operation
• MOSFET “off” unless in inversion
– look more deeply at inversion operation
• Define some stuff
–
–
–
–
–
–
Qs = total charge in substrate
VG = applied gate voltage
Vox = voltage drop across oxide
φs = potential at silicon/oxide interface (relative to substrate-ground)
Qs = - Cox VG
VG = Vox + φs
• During Inversion (for nMOS)
– VG > 0 applied to gate
– Vox drops across oxide (assume linear)
– φs drops across the silicon substrate, most near the surface
ECE 410, Prof. A. Mason
Lecture Notes 6.11
Surface Charge
• QB = bulk charge, ion charge in depletion region under
1
the gate
2
⎡
⎤
– QB = - q NA xd, xd = depletion depth xd = ⎢ 2εφs ⎥
⎣ qN A ⎦
– QB = - (2q εSi NA φs)1/2 = f(VG)
– charge per unit area
• Qe = charge due to free electrons at substrate surface
• Qs = QB + Qe < 0 (negative charge for nMOS)
depletion
region
QB, bulk
charge
electron
layer, Qe
ECE 410, Prof. A. Mason
Lecture Notes 6.12
Surface Charge vs. Gate Voltage
• Surface Charge vs. Gate Voltage
– VG < Vtn, substrate charge is all bulk charge, Qs = QB
– VG = Vtn, depletion region stops growing
• xd at max., further increase of VG will NOT increase xd
• QB at max.
– VG > Vtn, substrate charge has both components, Qs = QB + Qe
• since QB is maxed, further increases in VG must increase Qe
• increasing Qe give more free carriers thus less resistance
• Threshold Voltage
– Vtn defined as gate voltage where Qe starts to form
– Qe = -Cox (VG-Vtn)
– Vtn is gate voltage required to
• overcome material difference between silicon and oxide
• establish depletion region in channel to max value/size
ECE 410, Prof. A. Mason
Lecture Notes 6.13
Overview of MOSFET Current
• Gate current
– gate is essentially a capacitor ⇒ no current through gate
– gate is a control node
• VG < Vtn, device is off
• VG > Vtn, device is on and performance is a function of VGS and VDS
• Drain Current (current from drain to source), ID
– Source = source/supply of electrons (nMOS) or holes (pMOS)
– Drain = drain/sink of electrons (nMOS) or holes (pMOS)
– VDS establishes an E-field across (horizontally) the channel
• free charge in an E-field will create a drain-source current
• is ID drift or diffusion current?
nMOS
• MOSFET I-V Characteristics
VDS = VGS - Vtn
source @ ground
↑ VGS
Charge Flow
Current Flow
ECE 410, Prof. A. Mason
drain @ (+)ve potential
Electron Flow
Current Flow
Lecture Notes 6.14
Channel Charge and Current
• Threshold Voltage = Vtn, Vtp
– amount of voltage required on the gate to turn tx on
– gate voltage > Vtn/p will induce charge in the channel
• nMOS Channel Charge
– Qc = -CG(VG-Vtn), from Q=CV, (-) because channel holds electrons
channel charge is
• nMOS Channel Current (linear model:) assumes
constant from source to drain
– I = |Qc| / tt , where tt = transit time, average time to cross channel
• tt = channel length / (average velocity) = L / v
• average drift velocity in channel due to electric field E Æ v = μn E
• assuming constant field in channel due to VDS Æ E = VDS / L
VDS
μn
• Æ
L
I = Qc
L
CG = CoxWL ⇒| Qc |= CoxWL(VG − Vtn )
– I = μnCox (W/L) (VG-Vtn) VDS : linear model, assumes constant charge in channel
similar analysis applies for pMOS, see textbook
ECE 410, Prof. A. Mason
Lecture Notes 6.15
Transconductance and Channel Resistance
• nMOS Channel Charge: Qc = -CG(VG-Vtn)
• nMOS linear model Channel Current:
– I = μnCox(W/L)(VG-Vtn) VDS
• assumes constant charge in channel, valid only for very small VDS
• nMOS Process Transconductance
– k’n = μnCox [A/V2] ⇒ I = k’n (W/L) (VG-Vtn) VDS
• nMOS Device Transconductance
– βn = μnCox (W/L) [A/V2] ⇒ I = βn (VG-Vtn) VDS
– constant for set transistor size and process
• nMOS Channel Resistance
– channel current between Drain and Source
– channel resistance = VDS / IDS
– Rn = 1/( βn (VG-Vtn) )
• pMOS: k’p = μpCox, βp = μpCox (W/L)
ECE 410, Prof. A. Mason
similar analysis
applies for pMOS,
see textbook
Rn =
1
W
(VGS − Vtn )
L
1
Rp =
W
μ p Cox VSG − Vtp
L
μ nCox
(
)
Lecture Notes 6.16
nMOS Current vs.Voltage
• Cutoff Region
General Integral for expressing ID
• channel charge = f(y)
• channel voltage = f(y)
• y is direction from drain to source
– VGS < Vtn
⇒ ID = 0
VD
• Linear Region
I D = α ∫ QI ( y )δV ( y )
– VGS > Vth, VDS > 0 but very small
0
• Qe = -Cox (VGS-Vtn)
• ID = μn Qe (W/L) VDS
VDS = VGS - Vtn
⇒ ID = μnCox (W/L) (VGS-Vtn) VDS
↑ VGS
• Triode Region
– VGS > Vth, 0 < VDS < VGS-Vth
• surface potential, φs , at drain now f(VGS-VDS=VGD) ⇒ less charge near drain
• assume channel charge varies linearly from drain to source
– at source: Qe = -Cox (VGS-Vtn), at drain: Qe = 0
⇒
ID =
[
2(V
L
μ n COX W
2
GS
2
− Vt )V DS − V DS
]
ECE 410, Prof. A. Mason
Lecture Notes 6.17
nMOS Current vs.Voltage
• Saturation Region (Active Region)
– VGS > Vtn, VDS > VGS-Vtn
• surface potential at drain, φsd = VGS-Vtn-VDS
• when VDS = VGS-Vtn, φsd = 0 ⇒ channel not inverted at the drain
– channel is said to be pinched off
• during pinch off, further increase in VDS will not increase ID
– define saturation voltage, Vsat, when VDS = VGS-Vtn
⇒
square law
equation
• current is saturated, no longer increases
• substitute Vsat=VGS-Vtn for VDS into triode equation
ID =
μ n C OX W
2
L
(VGS − Vt )
2
ECE 410, Prof. A. Mason
ID =
[2(V
L
μ n COX W
2
GS
2
− Vt )V DS − V DS
Lecture Notes 6.18
]
Other Stuff
• Transconductance
– process transconductance, k’ = μn Cox
• constant for a given fabrication process
– device transconductance, βn= k’ W/L
• Surface Mobility
– mobility at the surface is lower than mobility deep inside silicon
– for current, ID, calculation, typical μn = 500-580 cm2/V-sec
• Effective Channel Length
– effective channel length reduced by
• lateral diffusion under the gate
• depletion spreading from drain-substrate junction
L (drawn)
S
Leff = L(drawn) − 2 LD − X d
⎛ 2ε (V − (VG − Vt )) ⎞
⎟⎟
X d = ⎜⎜ s D
qN
A
⎝
⎠
ECE 410, Prof. A. Mason
D
G
xd
LD
~xd
Leff
Lecture Notes 6.19
Second Order Effects
• Channel Length Modulation
– Square Law Equation predicts ID is constant with VDS
– However, ID actually increases slightly with VDS
• due to effective channel getting shorter as VDS increases
• effect called channel length modulation
– Channel Length Modulation factor, λ
• models change in channel length with VDS
– Corrected ID equation
ID =
• Veff = VGS - Vtn
μ nCOX W
2
L
(
(VGS − Vt ) 2 1 + λ (VDS − Veff )
)
• Body Effect
–
–
–
–
so far we have assumed that substrate and source are grounded
if source not at ground, source-to-bulk voltage exists, VSB > 0
VSB > 0 will increase the threshold voltage, Vtn = f(VSB)
called Body Effect, or Body-Bias Effect
ECE 410, Prof. A. Mason
Lecture Notes 6.20
pMOS Equations
• Analysis of nMOS applies to pMOS with
following modifications
– physical
• change all n-tpye regions to p-type
• change all p-type regions to n-type
– substrate is n-type (nWell)
• channel charge is positive (holes) and (+)ve charged ions
– equations
• change VGS to VSG (VSG typically = VDD - VG)
• change VDS to VSD (VSD typically = VDD - VD)
• change Vtn to |Vtp|
– pMOS threshold is negative, nearly same magnitude as nMOS
– other factors
• lower surface mobility, typical value, μp = 220 cm2/V-sec
• body effect, change VSB to VBS
ECE 410, Prof. A. Mason
Lecture Notes 6.21
Transistor Sizing
• Channel Resistance
“ON” resistance of transistors
– Rn = 1/(μnCox (W/L) (VGS-Vtn) )
Rn
Rp
– Rp = 1/(μpCox (W/L) (VSG-|Vtp|) )
• Cox = εox/tox [F/cm2], process constant
• Channel Resistance Analysis
Vtn
VDD-|Vtp|
VG
– R ∝ 1/W (increasing W decreases R & increases Current)
– R varies with Gate Voltage, see plot above
– If Wn = Wp, then Rn < Rp
• since μn > μp
• assuming Vtn ~ |Vtp|
– to match resistance, Rn = Rp
• adjust Wn/Wp to balance for μn > μp
ECE 410, Prof. A. Mason
Lecture Notes 6.22
Transistor Sizing
• Channel Resistances
– Rn = 1/(μnCox (W/L) (VG-Vtn) )
– Rp = 1/(μpCox (W/L) (VG-|Vtp|) )
– Rn/Rp = μn/μp
• if Vtn = |Vtp|, (W/L)n = (W/L)p
• Matching Channel Resistance
– there are performance advantage to setting Rn = Rp
• discussed in Chapter 7
– to set Rn = Rp
• define mobility ratio, r = μn/μp
• (W/L)p = r (W/L)n
– pMOS must be larger than nMOS for same resistance/current
• Negative Impact
– ⇒ CGp = r CGn larger gate = higher capacitance
ECE 410, Prof. A. Mason
How does this impact
circuit performance?
Lecture Notes 6.23
MOSFET RC Model
• Modeling MOSFET resistance and capacitance is very
important for transient characteristics of the device
• RC Model
time constant
at drain, τD
τD = CD Rn
• Drain-Source (channel) Resistance, Rn
– Rn = VDS / ID
• function of bias voltages
– point (a), linear region
• Rn = 1/[βn(VGS-Vtn)]
– point (b), triode region
• Rn = 2/{βn[2(VGS-Vtn)-VDS]}
– point (c), saturation region
• Rn = 2VDS / [βn (VGS-Vtn)2]
– general model equation
ECE 410, Prof. A. Mason
• Rn = 1/[βn(VDD-Vtn)]
Lecture Notes 6.24
MOSFET Capacitances -Preview
• Need to find CS and CD
• MOSFET Small
Signal model
Gate
vg
Cgs
Cgd
+
vgs
-
•
•
•
•
•
•
Cgs
Cgd
Cgb
Cdb
Csb
no Csd!
gmvgs gmbvsb
is vs
Source
– Model Capacitances
Cgb
ro
Drain v
d
id
Cdb
Csb
Body (Bulk)
• MOSFET Physical
Capacitances
– layer overlap
– pn junction
ECE 410, Prof. A. Mason
Lecture Notes 6.25
RC Model Capacitances
• Why do we care?
– capacitances determine switching speed
• Important Notes
– models developed for saturation (active) region
– models presented are simplified (not detailed)
• RC Model Capacitances
– Source Capacitance
• models capacitance at the Source node
• CS = CGS + CSB
– Drain Capacitance
• models capacitance at the Drain node
• CD = CGD + CDB What are CGS, CGD, CSB, and CDB?
ECE 410, Prof. A. Mason
Lecture Notes 6.26
MOSFET Parasitic Capacitances
• Gate Capacitance
– models capacitance due to overlap of Gate and Channel
• CG = Cox W L
– estimate that CG is split 50/50 between Source and Drain
• CGS = ½ CG
• CGD = ½ CG
– assume Gate-Bulk capacitance is negligible
• models overlap of gate with substrate outside the active tx area
• CGB = 0
• Bulk Capacitance
– CSB (Source-Bulk) and CDB (Drain-Bulk)
• pn junction capacitances
1
⎞
⎛
⎡ q εN A N D ⎤ 2
V
R
⎟ C jo = A⎢
C j = ⎜⎜ C jo 1 +
⎥
⎟
(
)
2
Ψ
N
+
N
Ψ
D ⎦
0 ⎠
⎣ 0 A
⎝
ND
NA
What are VR, Ψ0, NA, and ND?
ECE 410, Prof. A. Mason
Lecture Notes 6.27
MOSFET Junction Capacitances
• Capacitance/area for pn Junction
1
C j = C jo
⎛ VR ⎞
⎜⎜1 +
⎟⎟
⎝ Ψ0 ⎠
⎡ q εN A ⎤
C jo = ⎢
⎥
Ψ
2
0 ⎦
⎣
mj
mj = grading coefficient (typically 1/3)
2
⎛ N AND
Ψ0 = VT ln⎜⎜
2
n
⎝ i
⎞
⎟
⎟
⎠
assuming ND (n+ S/D) >> NA (p subst.)
• S/D Junction Capacitance
– zero-bias capacitance
• highest value when VR = 0, assume this for worst-case estimate
• Cj = Cjo
– CS/Dj = Cjo AS/D, AS/D = area of Source/Drain
• what is AS/D?
• complex 3-dimensional geometry
– bottom region and sidewall regions
– CS/Dj = Cbot + Csw
• bottom and side wall capacitances
ECE 410, Prof. A. Mason
Lecture Notes 6.28
Junction Capacitance
• Bottom Capacitance
– Cbot = Cj Abot
• Abot = X W
xj
• Sidewall Capacitance
– Csw = Cjsw Psw
• Cjsw = Cj xj [F/cm]
– xj = junction depth
• Psw = sidewall perimeter
– Psw = 2 (W + X)
• Accounting Gate Undercut
– junction actually under gate also due to lateral diffusion
– X ⇒ X + LD (replace X with X + LD)
• Total Junction Cap
– CS/Dj = Cbot + Csw = Cj Abot + Cjsw Psw = CS/Dj
ECE 410, Prof. A. Mason
Lecture Notes 6.29
MOSFET Bulk Capacitances
• General Junction Capacitance
– CS/Dj = Cbot + Csw
• CSB (Source-Bulk)
– CSB = Cj ASbot + Cjsw PSsw
• CDB (Drain-Bulk)
– CDB = Cj ADbot + Cjsw PDsw
Gate
vg
Cgs
• RC Model Capacitances
– Source Capacitance
• CS = CGS + CSB
– Drain Capacitance
• CD = CGD + CDB
ECE 410, Prof. A. Mason
Cgd
+
vgs
-
i s vs
Source
Cgb
ro
gmvgs gmbvsb
Drain v
d
id
Cdb
Csb
Body (Bulk)
Lecture Notes 6.30
Junction Areas
• Note: calculations assume following design rules
–
–
–
–
poly size, L = 2λ
poly space to contact, 2λ
contact size, 2λ
active overlap of contact, 1λ
⇒
W = 4λ
X1 = 5λ, X2= 2λ, X3 = 6λ
X1
• Non-shared Junction with Contact
– Area: X1 W = (5)(4) = 20λ2
– Perimeter: 2(X1 + W) = 18λ
• Shared Junction without Contact
– Area: X2 W = (2)(4)λ2 = 8λ2
– Perimeter: 2(X2 + W) = 12λ
X2
• much smaller!
• Shared Junction with Contact
(6)(4)λ2
24λ2
– Area: X3 W =
=
– Perimeter: 2(X3 + W) = 20λ
X3
• largest area!
ECE 410, Prof. A. Mason
Lecture Notes 6.31