A Reduced Switching Frequency Modulation Algorithm for High Power Multilevel Inverters
J. Rodrı́guez, S. Kouro, J. Rebolledo and J. Pontt
Universidad Técnica Federico Santa Marı́a
Department of Electronics Engineering
Av. España 1680, Valparaı́so, CHILE
Email: samir.kouro@ieee.org
Multilevel modulation
Abstract— Multilevel inverters have emerged as the state of
the art power conversion systems for high power medium voltage applications. Many topologies and modulation methods are
commercially available. This paper presents a new adaptive duty
cycle modulation algorithm, that reduces the switching frequency
and consequently the switching loses. This can be important
for high power applications, where high frequency modulation
methods like PWM are not suitable. Results are shown for a nine
level asymmetric cascaded inverter. Output voltage waveforms
obtained for references with variable frequencies and amplitudes
show a similar switching pattern, with a reduced and near
constant number of commutations per cycle, regardless the
reference frequency and amplitude. The proposed modulation
is compared to a Multiple Carrier PWM method, achieving
the same fundamental reference tracking performance with a
reduced number of commutations.
I. I NTRODUCTION
Multilevel inverters are considered today the most suitable
power converters for high voltage capability and high power
quality demanding applications [1]–[4]. Voltage operation
above classic semiconductor limits, lower common mode
voltages, near sinusoidal outputs together with small dv/dt’s,
are some of the characteristics that have made this power
converters popular for industry and research, specially for
medium-voltage applications.
There are several topologies available, being the Neutral
Point Clamped [5], Flying Capacitor [6] and Cascaded Hbridge inverter [7] the most studied and used. In recent years
many variations and combinations of these topologies have
been reported, one of them is the cascaded H-bridge fed
by non equal DC sources, known as asymmetric multilevel
inverter [8], [9]. The main characteristic of this topology is
the reduction, or even elimination of redundant output levels
to maximize the output power quality of the inverter using less
semiconductors.
Many modulation algorithms have been adapted or created
for multilevel inverters [1]–[3]. Most of them are based on
multiple carrier Pulse Width Modulation (PWM) techniques:
Phase Disposition (PD), Phase Opposition Disposition (POD),
Alternative Phase Opposition Disposition (APOD) and Phase
Shifted (PS) carrier PWM have been studied [10]. Space
Vector Modulation (SVM) is also extended for the multilevel
case [11]. Selective Harmonic Elimination [12] and Space
Vector Control [13] are used for lower switching frequency
applications. These modulation methods are summarized in
Fig. 1.
In this paper, a new modulation method is presented based
on time domain duty cycle calculation between the two nearest
output voltage levels to the reference. An adaptive modulation
0-7803-9033-4/05/$20.00 ©2005 IEEE.
Fundamental Switching
Frequency
Space Vector
Control
High Switching
Frequency PWM
Selective Harmonic
Elimination
Space Vector
PWM
Phase Shifted
PWM
Phase Disposition
PWM
a1 a2 a3
Symmetric
Disposition
Fig. 1.
Opposition
Disposition
Alternate Opposition Disposition
Principal modulation methods for multilevel inverters.
time calculation based on the reference voltage slope is
derived, and used to achieve a reduction in the number of
commutations.
The multilevel modulation algorithm proposed in this
paper is applicable to any multilevel inverter topology, with
an arbitrary number of levels, either for single-phase or
three-phase applications. In this work, it is tested on a nine
level, three phase, asymmetric H-bridge cascaded inverter.
Results are compared, under same conditions, to Multicarrier
PD-PWM .
II. T HE I NVERTER
A generalized power circuit of an asymmetric H-bridge
cascaded inverter is shown in Fig. 2. The inverter is composed
by the series connection of m monophasic H-bridges fed by
non equal DC sources (vk , with k = 1, . . . , m). The use
of asymmetric input voltages can reduce, or when properly
chosen, eliminate redundant output levels, maximizing the
number of different levels generated by the inverter. Therefore
this topology can achieve the same output voltage quality
with less number of semiconductors, space and costs than the
symmetric fed topology.
When cascading three level inverters like H-bridges (output
levels: −vdc , 0 and +vdc ), the optimal asymmetry is obtained
by using voltage sources scaled proportional to the power of
three. Applying this criteria to the voltage sources illustrated
in Fig. 2, optimal design leads to
⎤ ⎡
⎤
⎡
30
v1
⎥
⎢ v2 ⎥ ⎢ 31
⎥ ⎢
⎥
⎢
⎥
⎢ v3 ⎥ ⎢ 32
(1)
⎥=⎢
⎥ · vdc .
⎢
⎥
⎢ .. ⎥ ⎢
..
⎦
⎣ . ⎦ ⎣
.
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vm
3(m−1)
v1
b
va1
v2
c
vb 1
va2
vc 1
vb 2
v o*
vo
5vdc
Voltage Levels
a
4v
dc
3vdc
2v
dc
tcom
vdc
vc 2
Tm
2Tm
Time
3Tm
4T m
(a)
vo*
vo
5vdc
vam
vcm
vbm
Voltage Levels
vm
n
Fig. 2.
Asymmetric cascaded H-bridge multilevel inverter.
4vdc
3vdc
vdc
Tm
Then the individual output voltages per H-bridge are
Voltage Levels
(2)
vam ∈ {−3(m−1) vdc , 0, +3(m−1) vdc },
for phase a, which is analog for phases b and c of the inverter.
The total phase voltages generated by the inverter can be
expressed as
vaj ;
j=1
vbn =
m
vbj ;
Time
3T m
4T m
vo*
vo
5vdc
va2 ∈ {−3vdc , 0, +3vdc },
..
.
m
2T m
(b)
va1 ∈ {−vdc , 0, +vdc },
van =
tcom
2vdc
vcn =
j=1
m
vcj .
4vdc
3vdc
2vdc
tcom
vdc
Tm
(3)
2Tm
Time
3Tm
4
4Tm
(c)
j=1
Replacing in (3) the different combinations of individual
outputs generated by each H-bridge given in (2), a total of
3m different levels per phase can be generated to the load.
Fig. 3.
Duty Cycle Modulation: (a) Left-justified timer schedule when
dvo∗ /dt > 0; (b) Left-justified timer schedule when dvo∗ /dt < 0; (c) Rightjustified timer schedule when dvo∗ /dt < 0.
This can be expressed mathematically by
III. M ODULATION STRATEGY
vo∗ (2Tm ) = v̄o (∆T3 )
3Tm
1
=
vo (t)dt
(4)
Tm 2Tm
2Tm +tcom
3Tm
1
=
dt + 3vdc
dt .
2vdc
Tm
2Tm
2Tm +tcom
A. Basic principle
The proposed modulation algorithm is based on a combination of left-justified timer scheduling and right-justified
timer scheduling duty cycle modulation [14], together with
an adaptive commutation time calculation derived from the
voltage reference slope. The aim of the proposed method is
to change the modulation time frame to reduce the switching
frequency.
The left-justified timer scheduling operating principle is
shown in Fig. 3(a). Consider, for example, the third modulation
period ∆T3 =[2Tm , 3Tm ] in Fig. 3(a) (shadowed area). To
achieve fundamental frequency tracking, the mean output
voltage during this period, v̄o (∆T3 ), has to be equal to the
sampled reference at the beginning of the interval, vo∗ (2Tm ).
Then, the commutation time, tcom is computed by solving (4).
This task can be simplified seeing the modulation of vo∗ (2Tm )
as a duty cycle between the two nearest output voltage levels.
Then tcom can be easily computed by
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tcom
∗
∗
vo (2Tm )
vo (2T )
= 1−
− f loor
· Tm . (5)
vdc
vdc
Once tcom is calculated by (5), the nearest lower voltage level
to the reference,
∗
vo (2Tm )
f loor
(6)
· vdc ,
vdc
Voltage [pu]
1
−0.5
−1
is generated to complete the duty cycle from t = 2Tm + tcom
to t = 3Tm .
The qualitative example explained before and illustrated
in Fig. 3(a) looks adequate for positive voltage reference
slopes. However the negative slope case, shown in Fig. 3(b),
reveals that the commutation sequence (first the lower level
and then the higher level) still achieves fundamental reference
tracking, but introduces higher harmonic distortion due to
higher dv/dt’s since a two level difference appears in the
switching pattern. It clearly follows that a right-justified timer
schedule would be more appropriate for the negative slope
case as shown in Fig. 3(c). In this case tcom is computed by
0.5
vo∗ (2Tm )
− f loor
vdc
vo∗ (2T )
vd c
· Tm .
(8)
Once tcom is determined by (8) first the nearest upper level is
generated and is switched to the nearest lower level at tcom .
The slope sign detection and timer schedule justification is
selected according to the following criteria:
vo∗ (t) > vo∗ (t − Tm ),
=⇒ use left-justified timer schedule
else,
if
(9)
=⇒ use right-justified timer schedule
Voltage [pu]
1
0.5
0
Vo
V *
−0.5
−1
o
0
0.02
0.04
0.06
Time[s]
0.08
0.1
0.12
(a)
Voltage [pu]
1
0.5
0
Vo
Vo*
−0.5
−1
0
0.02
0.04
0.06
0.08
Time[s]
0.1
0.12
(b)
Fig. 4.
Results for a 81 level asymmetric inverter with Duty Cycle
Modulation: (a) Left-justified timer schedule; (b) left&right-justified timer
schedule with voltage reference slope sign detection.
o
vo
0
is generated from t = 2Tm up to t = 2Tm + tcom , then the
nearest upper voltage level,
∗
vo (2Tm )
ceil
(7)
· vdc ,
vdc
tcom =
v *
0.5
0
0.005
0.01
0.015
0.02
Time [s]
0.025
0.03
0.035
0.04
(a)
Voltage[pu]
1
v *
o
v
o
0
−0.5
−1
0
0.025
0.05
0.075
0.1
Time[s]
0.125
0.15
0.175
0.2
(b)
Fig. 5. A 9 level asymmetric H-bridge inverter with left&right-justified timer
schedule modulation: (a) Output voltage for a 50[Hz] reference; (b) Output
voltage for a 10[Hz] reference.
Figure 4(a) and (b) show results for a 81 level inverter
(4 asymmetric H-bridges per phase) with left-justified timer
schedule and the combined left&right-justified timer schedule
respectively. It is clear that the voltage reference slope sign
detection reduces dv/dt’s by alternating both methods adequately. This algorithms ensures mean voltage tracking with
zero error in each modulation interval. However, since the
modulation period is fixed (Tm = constant), the selected
value for implementation has to be sufficiently small to allow
good performance for the highest voltage reference frequencies. When using this small Tm for a low frequency reference, unnecessary additional commutations will be performed
with this modulation algorithm (this occurs with all PWM
methods).This effect is shown in Fig. 5(a) and (b), where
the same algorithm (same Tm ) is applied to a 50[Hz] and
10[Hz] voltage references respectively. It can be seen that the
considered modulation period of 1[ms] produces a minimum
necessary commutations for the fast reference, while to many
commutations are performed to follow the 10[Hz] reference.
For High power applications those extra switching losses can
be avoided introducing a variable modulation period, which
should be determined according to the reference frequency.
B. Adapting the modulation period
It is possible to reduce the number of commutations by
using appropriately an estimation of the voltage reference
slope. Assuming for a certain instant t = t(k) that the slope
mk stays fixed over one modulation period Tmk , and that in
addition the difference between two adjacent voltage levels
is always vdc , a modulation period that produces only one
commutation can be calculated by
vdc
,
(10)
Tmk =
mk
This holds only if no big changes occur in the reference slope,
which is common in high power applications.
The estimated slope is calculated using a least squares
algorithm and some past samples of the voltage reference. For
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n samples and a fixed sampling period Ts = t(i) − t(i − 1),
the slope is given by
n
mk =
k
t(i) · v ∗ (i) −
i=k−n
n·
k
t(i) ·
i=k−n
k
2
t (i) −
i=k−n
k
k
2) Use the last n samples to compute the reference slope
mk according to (11), and compare to mmin .
3) Calculate the modulation period Tmk using (10).
4) Determine the nearest voltage levels to the reference as
given in (6) and (7).
5) Compute commutation time tcom :
a) using (5), if mk > 0 (left timer scheduling).
b) using (8), if mk < 0 (right timer scheduling).
6) Tmk , tcom and the nearest voltage levels are sent to
a FPGA to schedule the commutation and deliver the
gating signals necessary to generate the desired voltage
levels at the corresponding times.
7) Save the last n voltage reference samples before the
modulation period Tmk is finished.
8) Begin algorithm again.
v ∗ (i)
i=k−n
2
. (11)
t(i)
i=k−n
Figure 6 illustrates this operating principle. For example, at
t = t2 the slope m2 is computed according to (11), then the
modulation period Tm2 is calculated using (10), finally the
left timer schedule modulation is performed since m2 > 0.
Note that the adaptive modulation time will adjust itself to the
reference signal.
C. Modulation period saturation
There is however a drawback at this point with this strategy,
from (10) it follows that for mk ’s close to zero, too large
modulation periods are obtained. Therefore Tmk has to be
saturated using a certain criteria; when the estimated slope
of the reference is lower than a specified limit mmin , the last
modulation time will be used. When the estimated slope is
higher than mmin the calculated modulation time will be used.
This can be summarized as follows:
if
mk < mmin ,
=⇒ use Tm(k−1)
else,
(12)
=⇒ use Tmk
The design of mmin will depend on the highest frequency
available in the reference bandwidth.
D. Algorithm summary
IV. R ESULTS
Figure 7(a) and (b) show output voltage results for a 9 level
asymmetric H-bridge inverter controlled with the proposed
slope sign detection and adaptive modulation time calculation
for a 10[Hz] and 50[Hz] reference respectively. The algorithm
was tested using a least squares estimation with n = 5
samples and a sample period Ts = 10[µs]. It can be seen
that both waveforms are very similar in shape, due to the
adaptation of the algorithm to both reference frequencies. The
results confirm that the algorithm works properly, achieving
fundamental frequency control and similar waveforms, same
number of commutations per cycle, independently of the
voltage reference frequency.
Note that this modulations techniques introduces a zeroorder-hold effect, because of its discrete time nature [14].
Figure 8 shows the algorithm timer. Each saw tooth
represents the execution of the algorithm, showing clearly
how the modulation periods change according to the slope of
the reference. Note that the modulation period is saturated
The following is a simplified overview of the necessary
steps to perform the proposed modulation algorithm:
1) Continuously sample the voltage reference at DSP clock
time Ts .
Voltage[pu]
1
4vdc
vo*
0.5
v
o
0
−0.5
−1
0
m
1
2vdc
Tm1
t1 t2
Fig. 6.
0.04
1
v o*
vo
Tm2
0.08
0.1
(a)
Tm3
2
0.06
Time [s]
Voltage [pu]
m
3vdc
vdc
0.02
m3
vo*
0.5
v
o
0
−0.5
−1
0
0.02
0.04
0.06
0.08
0.1
Time [s]
t3
Time
t4
Adapting modulation time operating principle.
(b)
Fig. 7. Results for a 9 level asymmetric H-bridge inverter with the adaptive
modulation period algorithm: (a) Output voltage for a 10[Hz] reference; (b)
Output voltage for a 50[Hz] reference.
870
1
Voltage [pu]
Modulation timer [s]
0.01
0.008
0.006
0.004
0.002
0
0.5
0
v *
o
−0.5
v
o
−1
0
0.025
0.05
0.075
0.1
Time [s]
0.125
0.15
0.175
0
0.2
0.02
0.04
0.06
0.08
0.14
0.16
0.18
0.2
0.14
0.16
0.18
0.2
(a)
(a)
1
Voltage [pu]
0.002
Modulation timer [s]
0.1
0.12
Time [s]
0.001
0.5
0
v *
o
−0.5
vo
−1
0
0
0.005
0.01
0.015
0.02
Time [s]
0.025
0.03
0.035
0
0.04
0.02
0.04
0.06
0.08
0.1
0.12
Time [s]
(b)
(b)
Fig. 8. Adaptive modulation periods: (a) For a 10[Hz] reference; (b) For a
50[Hz] reference.
Fig. 9. Response to step change in amplitude and frequency: (a) Proposed
algorithm; (b) Multiple carrier Phase Disposition PWM.
0.06
Voltage [pu]
when mmin is reached, and that two to three sample periods
have he same time length until the slope restriction is
deactivated.
0.02
0
V. C OMPARISON
VI. C ONCLUSION
In this paper a new duty cycle modulation technique, with
adaptive modulation periods has been presented. Reduced
commutations and similar output voltage quality, independently of the reference frequency, are the main features
achieved.
The algorithm is by nature developed in discrete time,
and therefore its DSP implementation is straightforward. The
algorithm can be easily extended for any multilevel inverter
topology, either for one or three-phase applications.
0
200
400
600
800
1000 1200
Frequency [Hz]
1400
1600
1800
2000
(a)
0.06
Voltage [pu]
Figure 9(a) and (b) present a comparison between the
proposed method and Multiple Carrier Phase Disposition
PWM operating in a 9 level Asymmetric Inverter. Both
methods are tested under same conditions, showing the
dynamic behavior when a simultaneous step is applied in
amplitude and frequency at t = 0.1[s]. Both methods achieve
fundamental frequency control, however the carrier frequency
for the PD-PWM was designed to follow correctly the
high frequency component of the reference, and therefore it
produces a large number of commutations until t = 0.1[s].
The proposed method adapts the modulation period, obtaining
almost a constant number of commutations per cycle. The
steady state spectrum for both methods for a 10[Hz] reference
are plotted in Fig. 10(a) and (b). As expected, the harmonic
content for PD-PWM is concentrated around multiples of
the carrier frequency 1[kHz), while the proposed algorithm
produces a dispersed low frequency harmonic content. This
is a drawback considering the filtering nature of most loads.
However this work is focused for high power applications
where reducing commutation losses is required. If this issue
becomes relevant the use of an output filter is recommended.
THDv = 12.2
0.04
THDv = 15.7
0.04
0.02
0
0
200
400
600
800 1000 1200
Frequency [Hz]
1400
1600
1800
2000
(b)
Fig. 10. Steady state output voltage spectrum: (a) Proposed Algorithm; (b)
Multiple carrier Phase Disposition PWM.
Compared to high switching frequency modulations methods (like carrier based PWM), less commutations are obtained
while achieving same reference tracking. This makes the
algorithm suitable for high power applications.
Compared to low frequency modulation methods, the
proposed algorithm ensures fundamental reference tracking,
and also can be applied to inverters with reduced number
of levels and achieves high quality outputs even for low
modulation indexes (not achieved with Space Vector Control).
In addition it is easy to implement and not limited to pure
sinusoidal references (necessary for Selective Harmonic
Elimination).
ACKNOWLEDGMENT
The authors gratefully acknowledge financial support provided by the Chilean National Fund of Scientific and Technological Development (Fondecyt), under grant No. 1040183,
and by the General Direction of Research (DGIP) of the
Universidad Técnica Federico Santa Marı́a.
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R EFERENCES
[1] J. S. Lai and F. Z. Peng, “Multilevel converters–A new breed of power
converters,” IEEE Trans. Ind. Applicat., vol. 32, no. 3, pp. 509–517,
May/June 1996.
[2] R. Teodorescu, F. Blaabjerg, J. K. Pedersen, E. Cengelci, S. Sulistijo,
B. Woo, and P. Enjeti, “Multilevel converters – A survey,” in European
Power Electronics Conference, 1999, Lausanne, Switzerland.
[3] J. Rodrı́guez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey
of topologies, controls and applications,” IEEE Trans. Ind. Electron.,
vol. 49, no. 4, pp. 724–738, 2002.
[4] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, “Multilevel converters
for large electric drives,” IEEE Trans. Ind. Applicat., vol. 35, no. 1, pp.
36–44, January/February 1999.
[5] A. Nabae and H. Akagi, “A new neutral-point clamped pwm inverter,”
IEEE Trans. Ind. Applicat., vol. 17, no. 5, pp. 518–523, September 1981.
[6] T. Meynard and H. Foch, “Multi-level choppers for high voltage applications,” Eur. Power Electron. Journal, vol. 2, no. 1, pp. 45–50, March
1992.
[7] M. Marchesoni, M. Mazzucchelli, and S. Tenconi, “A non conventional
power converter for plasma stabilization,” in Power Electronics Specialist Conference, 1988, pp. 122–129.
[8] O. M. Mueller and J. N. Park, “Quasi-linear IGBT inverter topologies,”
in APEC’94, February 1994, pp. 253–259.
[9] S. Mariethoz and A. Rufer, “Design and control of asymmetrical multilevelinverters,” in IECON’02, November 2002, pp. 840–845, Sevilla,
Spain.
[10] B. P. McGrath and D. G. Holmes, “Multicarrier PWM strategies for
multilevel inverters,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp.
858–867, August 2002.
[11] N. Celanovic and D. Boroyevich, “A fast space-vector modulation algorithm for multilevel three-phase converters,” IEEE Trans. Ind. Applicat.,
vol. 37, no. 2, pp. 637–641, Mar./Apr. 2001.
[12] L. Li, D. Czarkowski, Y. Liu, and P. Pillay, “Multilevel selective harmonic elimination pwm technique in series-connected voltage inverters,”
pp. 1454–1461, October 1998.
[13] J. Rodrı́guez, L. Morán, P. Correa, and C. Silva, “A vector control
technique for medium-voltage inverters,” IEEE Trans. Ind. Electron.,
vol. 49, no. 4, pp. 882–888, August 2002.
[14] K. Corzine and J. Baker, “Multilevel voltage-source duty-cycle modulation: Analysis and implementation,” IEEE Trans. Ind. Electron., vol. 49,
no. 5, pp. 1009–1016, October 2002.
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