8th International Conference on Power Electronics - ECCE Asia
May 30-June 3, 2011, The Shilla Jeju, Korea
[ThA2-4]
ZVS Half-Bridge Zeta Converter with
Center-Tapped Rectifier
Jae-Bum Lee1, Ki-Bum Park2, Hyoung-Suk Kim1, Hyun-Wook Seong1, Gun-Woo Moon1,
and Myung-Joong Youn1
1
KAIST, 335 Gwahangno (373-1 Guseong-dong), Yuseong-gu, Daejeon 305-701, Korea
2
ABB, Switzerland Ltd, Segelhofstrasse 1 K CH-5405, Baden-Dättwil, Switzerland
Abstract-- In this paper, a new half-bridge zeta converter
employing a center-tapped rectifier is proposed. The
proposed converter provides a bidirectional powering path
in the rectifier. As a result, its improved rectifier voltage
waveform reduces the output filter size. Also, it has a wide
ZVS range due to the characteristic of the conventional
single-ended half-bridge zeta converter. The operational
principles, the characteristics, and the design considerations
of the proposed converter are analyzed. To verify the
performance of the proposed converter, experimental
results from a 180W prototype are presented.
Fig. 1. (a) Circuit diagram of the SHBZ converter.
Index Terms-- Single-ended rectifier (SER), half-bridge
zeta (HBZ) converter, center-tapped rectifier (CTR), zerovoltage switching (ZVS).
I. INTRODUCTION
To minimize the size and weight of the converters, a
high switching frequency is generally required. However,
the hard switching of power switch causes high switching
losses and high electromagnetic interference (EMI) noise.
As a result, various types of the soft switching dc/dc
converter have been highlighted for decades [1]-[6].
Among them, the half-bridge type converters are very
attractive because of a wide ZVS range, the reasonable
number of components, and clamping voltage stress on
the primary switches to the input voltage level without an
additional circuit [3]-[7].
The conventional single-ended half-bride zeta (SHBZ)
converter, which is derived from the zeta converter, is
one of the most attractive half-bridge type converters due
to a wide ZVS range, a linear voltage conversion ratio,
and the reasonable number of components [4]-[7].
However, it features a single-ended type converter, as
shown in Fig. 1 (a). That is, while Q1 only turns on, the
power is transferred from the primary side to the output
as can be seen in the voltage waveform of rectifier.
To solve the aforementioned drawback of SHBZ
converter caused by single-ended rectifier (SER), this
paper proposes the center-tapped half-bridge zeta
converter. As shown in Fig. 2, the structure of the
proposed converter is similar to that of the SHBZ
converter except for the center-tapped transformer. By
adopting the center-tapped rectifier (CTR) to provide the
bidirectional powering path, the proposed converter
reduces the output filter size while maintaining a wide
ZVS range, a linear voltage conversion ratio, and the
Fig. 1. (b) Key waveforms of the SHBZ converter.
reasonable number of components.
II. OPERATIONAL PRINCIPLE
Fig. 2, 3 and 4 show the circuit diagram, key
waveforms, and topological states of the proposed
converter, respectively. The proposed circuit consists of
one blocking capacitor (CB), two primary switches (Q1,
Q2), one center-tapped transformer (T1), one rectifier
diode (Ds), one link capacitor (Cs), one output filter
inductor (Lo), and one output filter capacitor (Co). For the
mode analysis, several assumptions are made as follows:
y The proposed converter operates under the steadystate conditions.
y Switches (Q1, Q2) are ideal, except for the output
capacitor and the internal antiparallel diode.
y The rectifier diode (Ds) is ideal, except for the
junction capacitor (Cj).
y Lm and Lo are constant current sources.
y The blocking capacitor voltage (VB) and the link
978-1-61284-957-7/11/$26.00 ©2011 IEEE
Fig. 2. Circuit diagram of the proposed converter.
ILo/2 and -ILo/2. When ILlkg becomes 0, ICs is 0 and IDs is
the same as the load current. After ILlkg changes its
direction to negative, IDs fully supplies the load current
and the rest of IDs charges the link capacitor to supply
charges dissipated.
Mode 4[t3 ± t4]
When Q2 is turned off at t3, mode 4 begins. Since Ds is
still turned on, Vsec is kept -VCs and Vpri is kept -VCs/Į.
The energy stored in Llkg charges Coss2 to Vs and
discharges Coss1 to 0. If the energy stored in Llkg is large
enough, the ZVS of Q1 is easily achieved.
Mode 5[t4 ± t5]
When Vds1 becomes 0 and Vds2 becomes Vs at t4, mode
5 begins. Vpri and Vsec are still kept -VCs/Į and -VCs,
respectively. Since Vs+VCs/Į-VB is applied across Llkg,
ILlkg increases linearly. As ILlkg increases, IDs decreases.
When IDs is 0, ICs is the same as the load current.
Fig. 3. Key waveforms of the proposed converter.
III. CHARACTERISTICS
capacitor voltage (VCs) are constant.
One switching period is divided into five subintervals
and each mode is explained as follows:
Mode 1[t0 ± t1]
When Ds is turned off at t0, mode 1 begins. The power
is transferred to the output only through Cs. Vs-VB is
applied to the primary side of the transformer and (VsVB)Ns1/Np+VCs is applied to the output LC filter.
Mode 2[t1 ± t2]
After Q1 is turned off at t1, the power is still transferred
to the output only through Cs. Coss1 is charged to Vs and
Coss2 is discharged to 0 by the reflected load current.
Since the ZVS of Q2 is accomplished by the reflected
load current, the ZVS of Q2 is easily achieved.
Mode 3[t2 ± t3]
Ds begins to conduct when Vpri becomes -VCs/Į at t2.
Since VB-VCs/Į is applied across Llkg, ILlkg decreases.
When decreasing ILlkg reaches ILm, IDs and ICs become
This section presents the characteristics of the
proposed circuit in detail as follows:
A. Voltage Conversion Ratio
To obtain the voltage conversion ratio considering the
resonant effect among the components (Llkg, CB, Cs), it is
assumed that the voltage across CB and Cs is constant.
VB can be derived from the voltage-second balance on
Lm, and Vk and VCs can be obtained from Fig. 3 and mode
3, respectively. The voltage conversion ratio of the
proposed converter can be derived from the voltagesecond balance on Lo by using VB, Vk, and VCs as follows:
Vo
Vs
1
DD
, Q
2D 2 DQ
L lkg
RoTs
, D
N s1 N s 2
Np
(1)
(1 D)2
If Q is small enough, the voltage conversion ratio can
be approximated as follows:
B. ZVS Conditions
The ZVS of the switch (Q1) is achieved by the energy
stored in Llkg as mentioned in mode 4. The ZVS
conditions of the switch (Q1) can be expressed as follows:
2
ª D (1 D) I o º
1
1
˜ Llkg ˜ «
t 2 ˜ ˜ Coss ˜ Vs2
»
2
2
¬ (1 D) ¼
The ZVS of the switch (Q2) is easily achieved since the
ZVS of the switch (Q2) is accomplished by the reflected
load current as mentioned in Mode 2. The ZVS conditions
of switch (Q2) can be obtained as follows:
(a)
1
1
1
2
˜ Lo ˜ I o2 ˜ Lm ˜ I Lm
t 2 ˜ ˜ Coss ˜ Vs2
2
2
2
(c)
D. Output Filter
Fig. 5 shows the comparative waveforms of the
rectifier voltage (Vrec) and output inductor current (I Lo) of
the SHBZ converter and the proposed converter. As can
be seen in this figure, the ac content of Vrec is much
smaller in the proposed converter compared with the
SHBZ converter.
The peak-to-peak output filter inductor current ripples
of the SHBZ converter and the proposed converter are
respectively calculated by using the voltage-second
balance on Lo as follows:
(d)
(e)
Fig. 4. Topological states of the proposed converter. (a) Mode 1 (t0
± t1). (b) Mode 2 (t1 ± t2). (c) Mode 3 (t2 ± t3). (d) Mode 4 (t3 ± t4).
(e) Mode 5 (t4 ± t5).
D ˜D
(4)
C. Commutation Energy
In most converters with the center-tapped transformer,
zero voltage is applied across the primary side of the
transformer while the rectifier diodes of the secondary
side are commutated. Therefore, the power is not
transferred to the output during the commutation period
[3]-[4].
The proposed converter has one link capacitor instead
of one diode on the upper of the secondary side of the
conventional CTR. Due to this characteristic, either VsVB or VCs/Į without zero voltage is always applied to the
primary side of the transformer during the commutation
period. Therefore, the proposed converter transfers power
even in the commutation period.
(b)
Vo
Vs
(3)
'iLo _ SHBZ
'iLo _ proposed
(2)
Since the voltage conversion ratio of the SHBZ
converter is approximately DNs/Np, Ns should be the
same as Ns1+Ns2 to operate both converters with the same
duty.
Vo (1 D)Ts
Lo
N
1
˜ (Vo t ˜ VB ) ˜ (1 D) ˜ Ts
Lo
Np
(5)
(6)
Therefore, the proposed converter can employ smaller
output filter inductance than the SHBZ converter.
IV. DESIGN CONSIDERATIONS
A. Rectifier Capacitor
Fig. 6 shows the simplified current waveforms of ILm,
Cs
(1 D)2 I oTs
4'VCs
'Q
'VCs
(8)
The value of the link capacitor can be selected with the
desired link capacitor voltage ripple conditions.
B. Selecting turn ratio
Lo and the offset current (ILm,offset) of Lm is related to
Ns2/Np as follows:
(a) SHBZ converter.
(Vo Lo
Ns2
VB )(1 D)Ts
Np
(9)
'I Lo
I Lm, offset
Ns 2 Io
Np
(10)
If Ns2 is large, the output filter inductor size can be
reduced, but ILm,offset increases. Therefore, it increases the
transformer size. If Ns2 is small, ILm,offset decreases, but the
output filter inductor size will be increased. Therefore,
the appropriate Ns2 should be designed by considering
this trade-off.
(b) Proposed converter.
Fig. 5. Rectifier voltage and output inductor current waveforms.
C. Device stress
The current stress of the switches (Q1, Q2) and the
rectifier diode (Ds), and the voltage stress of the rectifier
diode (Ds) can be approximated as follows:
(11)
I
D ˜I
ds1
I ds 2
I Ds
o
D (1 D) I o
(1 D)
2Io
(1 D)
VDs D ˜ Vs
Fig. 6. Simplified current waveforms.
ILlkg, ICs, and IDs under the assumption the commutation
period is small enough. After ILlkg becomes less than 0,
IDs fully supplies the load current and the rest of IDs
charges the link capacitor to supply charges. The total
amount of the charge (¨Q) stored in the link capacitor is
the same as the shaded area in Fig. 6 and can be
calculated as follows:
'Q
(1 D)2 I oTs
4
(7)
By using ¨Q, the value of the link capacitor can be
obtained as follows:
(12)
(13)
(14)
D. RCD snubber
In general, isolated converters with the LC output filter
suffer from a voltage ringing across the rectifier diode
due to the resonance between the leakage inductance of
the transformer and the junction capacitance of the
rectifier diodes. The voltage ringing results in the
overvoltage stress on the rectifier diode. Therefore, the
RCD snubber is required to prevent the overvoltage stress
[8]. The RCD snubber consists of one resistor (Rsnb), one
capacitor (Csnb), and one diode (Dsnb) as shown in Fig. 7.
The operational principle is briefly presented as follows.
After the commutation ends between the link capacitor
(Cs) and the rectifier diode (Ds), VCj increases by the
resonance between Llkg and Cj. When VCj reaches Vsnb,
Dsnb begins to conduct and VCj is clamped to Vsnb. Losses
due to the snubber circuit (Psnb) can be expressed as
follows [8]:
(a)
Fig. 7. Circuit diagram of the secondary RCD snubber.
(b)
Fig. 9. ZVS waveforms (Q1, Q2). (a) at a full load. (b) at a 40% load.
(a)
Fig. 10. Measured efficiency.
(b)
Fig. 8. Experimental waveforms at a full load with the RCD snubber.
(a) Q1, ILlkg, and Vrec. (b) ICs, IDs, and VDs.
Psnb
C j (2VSr Vsnb )(Vsnb Vo )2 Vsnb
2(Vsnb Vo )(Vsnb VSr )Ts
(15)
Where VSr is the sum of the input voltage (Vs) and the
blocking capacitor voltage (VB) reflected to the secondary
side.
V. EXPERIMENTAL RESULTS
To verify the proposed converter, a prototype was
built with the following specifications: Vs = 300V~400V,
Vo = 200V, rated power = 180W, fs = 65kHz, Q1 and Q2 =
FCPF16N60, Ds = RHRP1560, Lm = 2mH, Llkg = 40μH,
Lo = 1.3mH, Co = 225nF, CB = Cs = 2.2μF, Np = 50Turns,
Ns1 = 27Turns, Ns2 = 34Turns. To remove the voltage
ringing across the rectifier diode of the secondary side,
the RCD snubber circuit is added with the following
specifications: Rsnb = 14kȍ, Csnb = 10nF, Dsnb = UF4004.
Fig. 8 shows the key experimental waveforms for the
nominal input voltage of 400V at a full load. It is shown
that all waveforms are agreed with the theoretical
analysis. To use the 600V rating diode for the rectifier
diode in the secondary side, the voltage stress on the
rectifier diode is limited to 500V as shown Fig. 8.
Fig. 9 shows gate-to-source and drain-to-source
voltages of Q1 and Q2 at a 40% and a full load. Llkg is
designed to achieve the ZVS of the switch (Q1) until a
35% load conditions. It is noted that the ZVS of Q2 is
easily achieved by the reflected load current at a 40%
load, and the ZVS of Q1 is achieved at a 40% load by the
energy stored in Llkg.
Fig. 10 shows the measured efficiency curves of the
SHBZ converter and the proposed converter according to
the load variation. The efficiency of the proposed
converter, through an overall load range, is improved
about 0.7% over the SHBZ converter. The reduced output
filter size contributes to the efficiency improvement.
However, the efficiency of both converters decreases
dramatically from a 30% load conditions since the losses
dissipated on the RCD snubber become dominant and the
ZVS of Q1 is not entirely achieved.
VI. CONCLUSIONS
A center-tapped half-bridge zeta converter, which has a
bidirectional powering path in the rectifier, is proposed.
Its improved rectifier voltage waveform reduces the
output filter size while maintaining the same number of
the components as the SHBZ converter. Also, it has a
wide ZVS range due to the characteristic of the
conventional single-ended half-bridge zeta converter. To
reduce the voltage ringing on the rectifier diode, the RCD
snubber is adopted.
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