Vector Control and Monitoring of Grid
Connected Active Front End Converter
A Project Report
Submitted in Partial Fulfillment of the
Requirements for the Degree of
Master of Engineering
In
Electrical Engineering
By
Narasimha Reddy . B
Department of Electrical Engineering
Indian Institute of Science
Bangalore-560012
India
June, 2011
Acknowledgements
I am grateful to Dr.Vinod John for taking me as his student and providing me the
opportunity to work in the area of Power Electronics. I have learnt lot a of lessons in
work ethics professional behaviour and meticulous approach to problem solving from him
, which will inspire me for the rest of my life. I feel highly fortunate to have worked under
him.
I express my heartfelt gratitude to Prof.V.T. Ranganathan for his constant supervision
and motivation during course work. Course dealt by him on ELECTRIC DRIVES was
very helpful in understanding the fundamentals of the project work.
I wish to express my gratitude to Prof.V.Ramanarayanan and Dr.G.Narayanan for their
courses, which I had the opportunity to attend.
I specially thank Anirban and Siva Prasad for patiently helping at many critical junctures
of my project. I also thank all other PhD students of PEG group.
I am also grateful to all Professors of Electrical Engineering Department for providing me
knowledge and proper understanding during my course work. I acknowledge the MHRD,
Government of India for the financial support.I would like to thank IISc administration
for giving me nice accomodation and mess facility.
I also thank Mrs. Silvi Jose for maintaining the Power Electronics stores,and helping in
purchase of the components in purchase of the components and Mr.K.C.Ramachandran,
Mr. H.Nagaraj and other EE work- shop staff for their help. I am thankful to Mr.
D.M.Channegowda and his colleagues for their assistance and co-operation. I also thank
all of seniors, my classmets and all my juniors of Electrical Engineering Depatrment and
friends at IISc for giving me a nice company during the two years.
Finally, I want to acknowledge my beloved parents for their eternal love and encouragement.
iii
iv
Abstract
The aim of the project is controlling and monitoring of 3φ − 3wire grid connected Active
Front End Converter ( named as AFEC ). AFEC is also called as a 3-phase PWM rectifier.
Normally in most of the applications it is connected at utility/front end of the grid, so
thats why it is called as Front End Converter.
The ideal requirements of an FEC are,
• Sinusoidal input current at any given power factor (preferably unity)
• DC bus voltage control
• Bi-directional power flow
• Fast dynamic response
1. Should be able to track DC bus voltage reference and power reference quickly
2. Easy reference generation
The FEC can be controlled in many ways to satisfy the above requirements.In this report
controlling part of FEC uses Vector Contol approach in stationary reference Frame(i.e
, reference frame) where PR-Controllers are used to handle the AC quantities in
, reference frame . And in Vector control we can handle active power and reactive
independently along with the ideal requirements of FEC. In this project FPGA(ALTERA)
digital controller board is used.
a b
ab
Now a days monitoring is necessary to detect dynamic changes in certain important
electrical parameters and to provide safe operation of the system by sending/receiving
control signals from computer to protect the entire hardawre system from anywhere. And
we can observe the power quality of the system also.
Monitoring of FEC setup mainly includes
• Sensing of line voltages, line currents, DC bus voltage through ADC chip present
in digital controller board.
• with the help of these signals do the calculations necessary for contol.
v
vi
• store certain number of samples of required signals in the memory of FPGA board
with proper timing and proper order of the signals.
• Send those signals stored in memoy through RS-232 CABLE from FPGA to PC for
display.
• Display them in to the Graphical User Interface (GUI) built in Visual Basic (VB)
platform in Personal Computer (PC) screen to monitor these electrical quantities.
Then the PC can act as a power converter management system that keeps track of
long term trends in the power converter operation.
Contents
Table of Contents
vii
List of Figures
xii
1 Introduction
1
1.1
Back ground of the project . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.2
Block diagram of the project setup . . . . . . . . . . . . . . . . . . . . .
2
1.3
Goals of the project work . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
1.4
Organization of the report . . . . . . . . . . . . . . . . . . . . . . . . . .
4
2 Hardware Overview of the System
7
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.2
Hardware overview of 10KVA converter . . . . . . . . . . . . . . . . . . .
7
2.2.1
Power circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
2.2.2
Protection and Interface card . . . . . . . . . . . . . . . . . . . .
9
2.2.3
Gate drive card . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
2.2.4
Voltage sensing card . . . . . . . . . . . . . . . . . . . . . . . . .
10
2.2.5
Current sensing card . . . . . . . . . . . . . . . . . . . . . . . . .
11
2.2.6
Annunciation card . . . . . . . . . . . . . . . . . . . . . . . . . .
12
2.3
Pre charging of DC-bus of the converter( Rectifier ) . . . . . . . . . . . .
12
2.4
Digital Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.4.1
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.4.2
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2.4.3
DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2.4.4
Digital I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
P.U System in digital platform. . . . . . . . . . . . . . . . . . . . . . . .
15
2.5
vii
CONTENTS
2.6
viii
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Vector control of FEC in stationary reference frame
15
17
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
3.2
Vector control basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
3.3
Principle of operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
3.4
Vector control approach . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
3.4.1
Comparision b/w reference frames . . . . . . . . . . . . . . . . . .
22
3.4.2
Modelling of the system . . . . . . . . . . . . . . . . . . . . . . .
22
3.4.3
Phase locked loop ( PLL) . . . . . . . . . . . . . . . . . . . . . .
24
3.4.4
T.F Implementation and design of PR-current controller . . . . .
28
3.4.5
T.F Implementation and design of PI-voltage controller . . . . . .
31
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
3.5
4 Communication between FPGA and PC
35
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
4.2
UART Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
4.2.1
Transmitting and receiving serial data . . . . . . . . . . . . . . .
36
4.2.2
Synchronous Serial Transmission . . . . . . . . . . . . . . . . . .
37
4.2.3
Asynchronous Serial Transmission . . . . . . . . . . . . . . . . . .
37
4.3
Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
4.4
RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
4.5
Serial communication control structure . . . . . . . . . . . . . . . . . . .
40
5 Visual Basic Interface
43
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
5.2
Basics of Serial Communications . . . . . . . . . . . . . . . . . . . . . . .
44
5.2.1
Establishing the Serial Connection . . . . . . . . . . . . . . . . .
44
5.2.2
Opening the serial port. . . . . . . . . . . . . . . . . . . . . . . .
45
5.2.3
Communication settings . . . . . . . . . . . . . . . . . . . . . . .
45
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
5.3
6 Results and Conclusions
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
51
ix
CONTENTS
6.2
PLL results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
6.2.1
Stand alone mode of operation . . . . . . . . . . . . . . . . . . . .
55
6.3
Testing of PR-current control loops . . . . . . . . . . . . . . . . . . . . .
55
6.4
AFEC results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
6.5
Monitoring results
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
6.6
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
Bibliography
63
Tables
2.1 Converter details
2.2 Gains of Voltage sensing cards
2.3 Gains of current sensing cards
2.4 Cyclone IC details
2.5 P.U system in digital platform
3.1 Design specifications of the PLL
3.2 Design specifications of FEC set-up
5.1 Handshaking settings
5.1 Settings of communication events
xi
CONTENTS
xii
List of Figures
1.1
FEC setup with controlling system . . . . . . . . . . . . . . . . . . . . .
2
1.2
block diagram to transfer data from FPGA board to PC . . . . . . . . .
4
2.1
Block diagram of 10 kva converter . . . . . . . . . . . . . . . . . . . . . .
8
2.2
Power circuit of the converter . . . . . . . . . . . . . . . . . . . . . . . .
8
2.3
Charging of DC-bus with input to Rectifier is from auto transformer . . .
12
2.4
Block diagram of FPGA board . . . . . . . . . . . . . . . . . . . . . . . .
13
3.1
Classification of grid side converter control strategies . . . . . . . . . . .
17
3.2
PWM rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
3.3
α-β and d-q frames phasor representation . . . . . . . . . . . . . . . . . .
19
3.4
Equivalent circuit and phasor diagrams of the FEC . . . . . . . . . . . .
20
3.5
Control structure of FEC(PWM rectifier) in stationary reference frame .
24
3.6
PLL control structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
3.7
a-b and d-q frames phasor representation . . . . . . . . . . . . . . . . . .
3.8
Simplified block diagram of dq-PLL . . . . . . . . . . . . . . . . . . . . .
27
3.9
Frequency change from 50HZ to 51Hz . . . . . . . . . . . . . . . . . . . .
27
3.10 PR-controller structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
3.11 Resonant controller implementation . . . . . . . . . . . . . . . . . . . . .
28
3.12 Bode-plot of the resonant controller
. . . . . . . . . . . . . . . . . . . .
29
3.13 Block diagram of current control loop. . . . . . . . . . . . . . . . . . . .
30
3.14 Bode plot of current control open loop transfer function . . . . . . . . . .
31
3.15 PI-controller structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
3.16 Block diagram of voltage control loop . . . . . . . . . . . . . . . . . . . .
33
3.17 Bode plot of voltage control open loop transfer function . . . . . . . . . .
34
xiii
25
LIST OF FIGURES
xiv
4.1
Block diagram of serial communication control . . . . . . . . . . . . . . .
40
5.1
Monitoring of FEC setup before executing . . . . . . . . . . . . . . . . .
49
5.2
Monitoring of FEC setup just after executing
. . . . . . . . . . . . . . .
50
6.1
Grid line voltages Vry ; Vyb . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
6.2
Grid Phase voltages Vr ; Vy
. . . . . . . . . . . . . . . . . . . . . . . . .
52
6.3
Voltages Valpha ; Vbeta . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
6.4
Vd ; Vq voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
6.5
PLL unit Sine ; PLL unit Cosine. . . . . . . . . . . . . . . . . . . . . . .
53
6.6
PLL Frequency; PI-controller output . . . . . . . . . . . . . . . . . . . .
54
6.7
Frequency transient when it changes from 25Hz to 50Hz. . . . . . . . . .
54
6.8
o/p Phase to neutral voltage; o/p phase current. . . . . . . . . . . . . . .
55
6.9
PR-current controllers testing setup . . . . . . . . . . . . . . . . . . . . .
55
6.10 I actual tracking the ref, when DC bus changes from 0 to 200V . . . . .
56
6.11 Current error when DC-bus changes from 100V to 200V . . . . . . . . . .
56
6.12 Current tracking for 0.25P.U . . . . . . . . . . . . . . . . . . . . . . . . .
57
6.13 Current tracking for 1.P.U . . . . . . . . . . . . . . . . . . . . . . . . . .
57
6.14 DC-bus voltage tracking from 164V to 200V . . . . . . . . . . . . . . . .
58
6.15 DC-bus voltage transient while tracking . . . . . . . . . . . . . . . . . . .
58
6.16 Alpha currents([ref]; [actual] tracking under loaded condition . . . . . . .
59
6.17 Alpha currents([ref]; [actual] tracking from no-load to loaded condition .
59
6.18 Grid phase voltage and current waveforms under no-load . . . . . . . . .
60
6.19 Grid phase voltage and current waveforms under R-load(107.5 ) . . . .
60
6.20 DC bus voltage monitoring set-up . . . . . . . . . . . . . . . . . . . . . .
61
6.21 Snap shot of the monitoring system
62
a
. . . . . . . . . . . . . . . . . . . .
Chapter 1
Introduction
1.1
Back ground of the project
Three phase AC to DC converter is oftenly used to obtain DC supply from three phase
AC mains. Typical applications of it are UPS, battery chargers and motor drives etc. In
most of the applications it is connected at front/utility end of the supply, so thats why
it is called as front end converter.
The use of three phase diode/ thyristor bridge rectifiers as front end converter lead to
degradation in power quality due to input current distortion caused by them. The input
current distortion caused by diode/thyristor bridge rectifiers can be reduced by using a
bulk input filter, but sometimes it is also required to have a converter with bi-directional
power flow capability. In such application the attractive solution is a three phase PWM
AC to DC converter.
The ideal requirements of an FEC are:
• Sinusoidal input current at any given power factor (preferably unity)
• DC bus voltage control
• Bi-directional power flow
• Fast dynamic response
1. Should be able to track DC bus voltage reference and power reference quickly
2. Easy reference generation
1
1.2. Block diagram of the project setup
2
The FEC can be controlled in many ways to satisfy the above requirements.In this report
controlling part of FEC uses Vector Contol approach in stationary reference Frame(i.e
a, b reference frame) where PR-Controllers are used to handle the AC quantities in a,
b reference frame . And in Vector control we can handle active power and reactive
independently along with the ideal requirements of FEC.
Now a days monitoring is necessary to detect dynamic changes in certain important
electrical parameters and to provide safe operation of the system by sending/receiving
control signals from computer to protect the entire hardawre system from anywhere. And
we can observe the power quality of the system in power generation applications.
1.2
Block diagram of the project setup
Figure 1.1: FEC setup with controlling system
The FEC setup mainly consists of three phase 3 wire grid connected active front end
converter through line inductances, restive load across DC bus, FPGA digital controller(
cyclone EP1C12Q240C8) and RS-232 cable for serial communication purpose.
3
1.3. Goals of the project work
1.3
Goals of the project work
Vector control of FEC in stationary reference frame:
Basically in vector control we have 3 loops
1. Outer DC bus loop
2. Inner active current control loop
3. Inner reactive current control loop
Achievements with vector control in this project are
• In stationary reference frame we can control currents as AC quantities,so we use
PR-current controllers (which ensures almost zero steady state error) instead of PIcurrent controllers which does not ensure zero steady state error for AC quantities.
• DC bus voltage regulation
Suppose load increases our DC-bus voltage reduces.We will give this information to DCbus voltage controller which increases the current reference so that active current drawn
from the supply increases to maintain active power balance between DC-bus side and
grid side.
Similarly if load decreases our DC-bus voltage increases, we will give this information
to DC-bus voltage controller which reduces the active current drawn from the supply to
maintain active power flow balance between DCside andgrid side.
• Unity power factor operation
If we make reactive current reference equal to zero in inner reactive current loop then we
get unity power facor operation.
• Drawing nearly sinusoidal current
By switching the FEC at higher frequencies lower order harmonics get converted to
switching harmonics which can be easily eliminated by choosing proper value of line
inductance.
1.4. Organization of the report
4
Monitoring of the FEC setup:
Figure 1.2: block diagram to transfer data from FPGA board to PC
• Store certain number of samples of required signals in the memory of FPGA board
with proper baud rate, timing and proper order of the signals as shown like above.
• In this project baud rate choosen is 9600 bits/sec
• Send those signals stored in memoy through Max-232 chip via RS-232 CABLE from
FPGA to PC for display. Here MAX 232 is a level converter which converts signal
levels compatial with PC as well as FPGA board.
• Display them in to the Graphical User Interface (GUI) built in Visual Basic (VB)
platform in Personal Computer (PC) screen to monitor these electrical quantities.
1.4
Organization of the report
The overview of the report is stated as
In chapter1: “Introduction” about the project is presented.
In chapter2: “Hardware Overview of the 10kva Inverter and FPGA board” is Presented
In chapter3: “Vector Control of FEC in stationary reference frame” is presented.
5
1.4. Organization of the report
In chapter4: “ Communication between PC and FPGA” is explained.
In chapter5: “ Visual Basic Interface” is explained.
In chapter6: “ Results and conclusions” were explained.
1.4. Organization of the report
6
Chapter 2
Hardware Overview of the System
2.1
Introduction
This chapter explains about brief hardware overview ( means various cards present in
the converter) of the converter(actually we can use this converter as either rectifier or
inverter) ,testing procedure of the converter ,digital controller board which is Cyclone
FPGA device EP1C12Q240C8 and interfacing scheme between the FEC-setup and the
monitoring processor.
2.2
Hardware overview of 10KVA converter
The main outlook of the converter is shown in fig.2.1. It mainly consists of power circuit,
gate drive card, protection and delay card, front panel/annunciation card.It also contains
current sensing cards and voltage sensing cards to sense various voltages and currents
to provide overvoltage,under voltage ,over current protection.Also these sensed signals
can be routed to the processor for the purpose of computation from the PD card of the
converter.
7
2.2. Hardware overview of 10KVA converter
Figure 2.1: Block diagram of 10 kva converter
2.2.1
Power circuit
Figure 2.2: Power circuit of the converter
8
9
2.2. Hardware overview of 10KVA converter
The power circuit is shown above in fig.2.2.The power circuit of the converter includes
an IGBT based three phase leg , each leg consists of two IGBT swiches each rated for
50A and 1200V. The DC-bus of the converter consists of two capacitances connected in
series each rated for 3300µF,350V. So net capacitance at the DC_bus becomes 1650 µF
and DC-bus voltage becomes 700V.
A precharging circuit is used to charge the DC-bus capacitors before releasing the control
pulses during line side operation. For precharging circuit ref.[1].In the project totally
3 Hall-effect current sensors (two used to sense line currents and one is used to sense
DC-bus current) are used to sense currents from the power circuit, and 3 voltage sensors
(2 used for line voltages and 1 for DC-bus voltage) are used to sense voltages from power
circuit.
The converter details is given as
Module
Converter(FEC)
Devices
SKM12350GB IGBT modules(50A,1200V0
Heat sink
Afcoset 80 AD(forced cooling)
Bus bar
Sandwiched
DC bus rating
700V
Gate drive
Built in lab
Table 2.1 Converter details
2.2.2
Protection and Interface card
The features of protection and interface card are summarized below[4].
• Protection
1. Over current protection for line side currents
2. Over current protection for DC bus current
3. Over voltage protection for DC bus voltage
4. Under voltage protection for DC bus voltage
5. Short circuit protection
2.2. Hardware overview of 10KVA converter
10
• Dead time between top and bottom devices of the same leg
• Control of precharging circuit for the DC capacitors
• Provides interface to the gate drive cards
• Provides interface between digital controller and power circuit
• Provides signals to annunciation card for indication of status signals
2.2.3
Gate drive card
Gate drive card receives the PWM signals from the protection and delay card and turns
the IGBT ON or OFF. The features of gate drive card for a 10kVA converter are as
follows[4]:
• Capable of providing short circuit protection through Vce sensing.
• Capable of driving four parallel legs, in the project we are using only three legs.
• In built isolated (Fly back converter) power supply for driver circuits.
• Provides the optical isolation between power ground and DSP ground using HP3101.
2.2.4
Voltage sensing card
Voltage sensing card is used to sense the voltages and to provide electrical isolation between power circuit and control circuit, It also scale down the voltages.The specifications
of a voltage sensing card used are given below[4]:
• Range of input voltage is ± 600V
• Range of output voltage is ±10V
• Band width is 20KHZ
• Isolation amplifier between input and output
The current project uses three voltage sensing cards, out of them two are used to sense
line voltages and one is used to sense DC-bus voltage respectively. The gains of the
voltage sensing cards are given as
11
2.2. Hardware overview of 10KVA converter
Signal
Gain
Vry
1/26.24 v/v
Vyb
1/26.58 v/v
Vdc
1/45.19 v/v
Table 2.2 Gains of Voltage sensing cards
2.2.5
Current sensing card
The current project uses two current sensors to sense line currents.The specifications and
features are given as follows[4].
• Specifications
1. Maximum Range of i/p current is ±50
2. Maximum Range of o/p voltage is ±10
3. Bandwidth is 100kHz.
4. Maximum Non-linearity is 0.2%.
• Features
1. Low non-linearity and High bandwidth.
2. Precision ac / dc current transducer.
3. Uses low profile Hall effect current transformer HTP50
The gains of the current sensing cards are given as follows
Signal
Gain
Ir
1A/0.473V
Iy
1A/0.466V
Table 2.3 Gains of current sensing cards
2.3. Pre charging of DC-bus of the converter( Rectifier )
2.2.6
12
Annunciation card
Annunciation card displays/indicates the status of the following using LEDs.
• Indication of manual ON/OFF switch.
• Indication of Vce trip (Vce1, Vce2, Vce3, Vce4, Vce4, Vce5, Vce6).
• Indication of DC-bus voltage trip( Over voltage,Under voltage).
• Indication of over current trip.
2.3
Pre charging of DC-bus of the converter( Rectifier
)
To precharge the DC-bus,we have to operate the conveter as diode bridge rectifier till
preset value (means DC obtained with diode bridge rectifier) is reached i.e gate signals
to IGBT switches are off and only diode devices of IGBT switches are used to precharge
the DC-bus.
X-axis: 43.15v/div ; Y-axis:5secs/div
Figure 2.3: Charging of DC-bus with input to Rectifier is from auto transformer
The capacitor of a DC-bus charges through a line resistance in each phase till 70 to 80 %
of its preset value is reached, after that the DC-bus voltage abruptly changes to preset
13
2.4. Digital Controller
value due to closure of the contactor at the line resistance in each phase. And i/p to the
converter is variable AC which is from auto transformer.
2.4
Digital Controller
The digital controller used to implement the control in this project is ALTERA EP1C12Q240C8
FPGA[6] board. In FPGA hardware is programmable so user friendly programming is
possible. This FPGA board was programmed using Quartus-II (version 8.0) software.
2.4.1
FPGA
Figure 2.4: Block diagram of FPGA board
The block diagram of the digital platform is shown in above fig 2.3. The digital platform
consists of cyclone FPGA, configuration device (EEPROM), and other interfacing devices such as Analog to Digital converter(ADC), Digital to Analog converter(DAC) and
2.4. Digital Controller
14
digital I/O’s which are dedicated I/O pins of the FPGA device. ADC and DAC are also
interfaced using dedicated I/O pins of the FPGA device.
The FPGA board requires +5V, 0V, -5V power supply for its operation. All other levels
such as 3.3V, 1.5V, 2.5V, -2.5V are generated in the board itself. Cyclone FPGA is the
heart of the board in which all the algorithams are implemented. The Cyclone IC details
are given below.
Name
FPGA
Part No
EP1C12Q240C8
Manufacturer
ALTERA
No of Pins
240
Package
PQFP
No of Logic elements
12080
No of PLL
2
Maximum clock frequency using PLL
275MHz
Power supply required for Core
1.5V (VCCINT)
Power supply required for I/O
3.3V (VCCIO)
Power supply required for PLL
1.5V (VCCPLL)
IC No. in the Schematic
U14
Table 2.4 Cyclone IC details
2.4.2
ADC
The ADC is used to convert analog signals to digital signals. The FPGA board has
two ADC chips. The power supply required for AD7864AS-1 is +5V. The analog input
voltages are ranging from -10V to +10V. Each ADC has four channels with conversion
time of 1.6µs per channel. Because of two ADC’s totally we have 8 ADC channels in the
board.
2.4.3
DAC
The DAC is used to convert digital signals to analog signals. The FPGA board has only
one DAC. The power supply required for DAC is ± 5V, ± 2.5V ref respectively. The
15
2.5. P.U System in digital platform.
output analog voltages of the DAC are ranging from +2.5V to -2.5V. The DAC has four
channels with 10µs conversion time per channel.
2.4.4
Digital I/O pins
There are totally 56 I/O pins are available for the user. All the I/O pins are taken through
a bidirectional buffer. So according to the direction bit given by FPGA to buffer the I/O
signals becomes either input or output to FPGA.The input digital signals to the board
should be given +5V and the output digital signals from the board should be given at
+5V.
2.5
P.U System in digital platform.
The P.U system which is required in digital platform is given as below
PU value
Equivalent HEX Equivalent Decimal
2 pu
7FFF
32767
1 pu
3FFF
16383
0 PU
0000
0
-1 PU
C000
49152
-2 PU
8000
65535
Table 2.5 P.U system in digital platform
2.6
Conclusions
In this chapter, details pertaining to power circuit components were furnished. FPGA
based digital controller and its attributes were described along with per-unitization.
2.6. Conclusions
16
Chapter 3
Vector control of FEC in stationary
reference frame
3.1
Introduction
There are different vector control strategies used to perform the control of the grid side
converter. They all are focused on the same topics : i.e the control of the DC-link
voltage, independent acive and reactive power control of the grid, grid synchronization
and to ensure high quality of the injected power.
These control strategies are classified depending on the reference frame used in the control
structure.. In this project the focus is on the stationary reference frame control strategy
and then the PLL method to synchronize the control with the grid is introduced and
tested. Finally, the PI and PR controllers as well as the process of tuning are described.
But for comparision purpose brief introduction of synchronous reference frame is also
included in this literature.
Figure 3.1: Classification of grid side converter control strategies
17
3.2. Vector control basics
18
Synchronous reference frame means d-q frame
ab
Stationary reference frame means - frame
Natural reference frame means a-b-c frame
In d-q reference frame we can control the currents as DC quantities. In stationary reference frame we can control the current as AC quantities and also in natural reference
frame we can control the currents as AC quantities.
3.2
Vector control basics
Fig.3.2 shows the PWM rectifier which has the inverter structure and uses bidirectional
switches (IGBT’s). In most of the applications it is connected at the utility/front end of
the grid,so that is why it is called as front end converter (FEC).
Figure 3.2: PWM rectifier
The three phase grid voltages are given as follows
Va = Vm Cos(wt)....................................................................(3.1)
Vb = Vm Cos(wt − 120)..........................................................(3.2)
Vc = Vm Cos(wt − 240)..........................................................(3.3)
Where Vm is the maximum value of the phase voltage. Transforming these 3-phase
ab
voltages into 2-phase stationary reference frame ( - reference frame) we have, ref[1]
Vα = 1.5 Vm Cos(wt).............................................................(3.4)
Vβ = 1.5 Vm Sin(wt)..............................................................(3.5)
19
3.3. Principle of operation
Consider a grid voltage space vector V = Vα + jVβ = 1.5 Vm ((Cos(wt)+j Sin(wt))
whose magnitude is 1.5*Vm and making an angle wt w.r.t to α-axis at any given instant
of time. Here a synchronous d-q frame which is making an angle θ w.r.t to α-axis is
selected in such a way that grid voltage space vector is aligned along q-axis so that its
component along d-axis is zero to make the analysis becomes simple. Since grid voltage
space vector and d-q axis rotating at same speed as shown in fig3.3 then these are seemed
to be stationary w.r.t each other thus grid voltage space vector appeared as DC quantity
in d-q domain, which is true if grid space vector contains only fundamental component.
Suppose grid space vector contains fundamental and odd harmonic components then in
d-q domain grid space vector appear to contain DC and even order harmonics.
Figure 3.3: α-β and d-q frames phasor representation
From the above fig:
Vd = Vα Cosθ + Vβ Sinθ...............................................................(3.6)
Vq = Vβ Cosθ - Vα Sinθ.................................................................(3.7)
The power equations are given as follows ( Vd =0)
P = 2/3 * ( Vq Iq + Vd Id ) = 2/3 * Vq Iq .......................................(3.8)
Q = 2/3 * ( Vq Id − Vd Iq ) = 2/3 * Vq Id .......................................(3.9)
3.3
Principle of operation
The basic strategy for controlling the FEC can be easily explained by means of phasor
diagrams as follows[1]
3.4. Vector control approach
20
Figure 3.4: Equivalent circuit and phasor diagrams of the FEC
In the above figure Uac indicates ac grid voltage and Ufe indicates voltage at the midpoint of a leg or pole voltage which is PWM in nature. The pole voltage consists of a
fundamental component at line frequency and harmonic components around the switching
frequency of the converter. These harmonic components can be easily filtered out by
choosing proper line inductance. As we know that active power flows from leading voltage
to the lagging voltage, and reactive power flows from higher voltage to the lower voltage.
So both active power and reactive power can be controlled by controlling the fundamental
component of the converter pole voltage with respect to the grid voltage. That is by
controlling the pole voltage w.r.t grid voltage the currents flowing from the grid can be
controlled at any desired power factor as shown in above fig.3.4.
3.4
Vector control approach
This project mainly focus on stationary reference frame. But for comparision purpose
ab
d-q control is also included. In vector control(in - frame) we have 3 loops.
1. Outer DC-bus voltage loop
21
3.4. Vector control approach
2. Inner active current control loop
3. Inner reactive current control loop
The objectives of the vector control are given as
• Voltage regulation of the DC-bus
• Independent active and reactive power control
• Bidirectional power flow
• Operation at any desired power factor
• Low current harmonics.
Achievements with vector control in the project
• In stationary reference frame we can control currents as AC quantities,so we use
PR-current controllers (which ensures almost zero steady state error) instead of PIcurrent controllers which does not ensure zero steady state error for AC quantities
• DC bus voltage regulation
Suppose load increases our DC-bus voltage reduces.We will give this information to DCbus voltage controller which increases the current reference so that active current drawn
from the supply increases to maintain active power balance between DC-bus side and
grid side.
Similarly if load decreases our DC-bus voltage increases, we will give this information
to DC-bus voltage controller which reduces the active current drawn from the supply to
maintain active power flow balance between DCside andgrid side.
• Unity power factor operation
If we make reactive current reference equal to zero in inner reactive current loop then we
get unity power facor operation.
• Drawing nearly sinusoidal current
By switching the FEC at higher frequencies lower order harmonics get converted to
switching harmonics which can be easily eliminated by choosing proper value of line
inductance
3.4. Vector control approach
3.4.1
22
Comparision b/w reference frames
d-q reference frame:
• We can control the currents as DC quantities
• We use PI-current controllers in d-q frame because they ensure zero steady state
error for DC-quantities
• Effective for balanced system because in case of balanced system grid space vector appeared as a DC quantity in d-q domain.In case of unbalanced system grid
space vector appear to contain DC and even order harmonics in d-q domain, since
PI-controllers will not ensure zero steady state error for AC quantities,because of
limited gain at the frequency of intrest
• PI- current controllers will be effective for balanced system rather than unbalanced
system in d-q domain.
a -b
reference frame:
• We can control the currents as AC quantities
ab
• We use PR-current controllers in - frame because they ensure zero steady state
error for AC quantities.
• Since we are controlling the currents as AC quantities, PR-current controllers will
provide high gain at the frequency of intrest, and hence nearly zero steady state
error.
• PR- current controllers will be effective for both balanced and unbalanced systems
ab
in - domain.
3.4.2
Modelling of the system
The control is carried out in stationary reference frame, so the power circuit is modelled
ab
in stationary reference frame ( - frame) to design the controllers. The grid AC equations
in 3-Phase system can be represented as follows.
From fig3.2
23
3.4. Vector control approach
vga = Ria + L( dtd )ia + via ...........................................(3.10)
vgb = Rib + L( dtd )ib + vib ............................................(3.11)
vgc = Ric + L( dtd )ic + vic ............................................(3.12)
ab
The grid equations in stationary reference frame ( - ) frame is given as ref[1]
vgα = Riα + L( dtd )iα + viα ..........................................(3.13)
vgβ = Riβ + L( dtd )iβ + viβ ...........................................(3.14)
0
Riα + L( dtd )iα = vgα − viα = viα .................................(3.15)
0
Riβ + L( dtd )iβ = vgβ − viβ = viβ ..................................(3.16)
In equations (3.15), (3.16) left hand side represents a simple R-L circuit of first order,
which is called as plant. The right hand side of the same two equations correspond to
the excitations to the respective plants.
a
a
a
”
should only drive -axis current iα , through -axis
The -axis current controller output viα
plant equation (3.17)
”
.................................................(3.17)
Riα + L( dtd )iα = Gviα
b
b
b
”
should only drive -axis current iβ through -axis
The -axis current controller output viβ
plant equation (3.18).
”
Riβ + L( dtd )iβ = Gviβ
..................................................(3.18)
Where G is the converter gain, equating right hand sides of equations ( (3.15) and (3.17))
then we have,
”
Gviα
= vgα − viα
”
viα = vgα − Gviα
”
viα =G( VGgα -viα
)
∗
viα = Gviα
; where
∗
”
viα
= ( VGgα −viα
) .......................................................(3.19)
Equating right hand sides of equations, , ((3.16) and (3.18)) then we have,
”
Gviβ
= vgβ − viβ
”
viβ = vgβ − Gviβ
viβ =G(
Vgβ
”
-viβ
)
G
3.4. Vector control approach
24
∗
viβ = Gviβ
; where
∗
=(
viβ
Vgβ
”
)
−viβ
G
..........................................................(3.20)
So from the above knowledge of the system of equations the control structure of the
ab
front end converter in stationary reference frame ( - frame) is given as below.
Figure 3.5: Control structure of FEC(PWM rectifier) in stationary reference frame
In the above control structure to convert the references generated by the outer voltage
control loop (i.e Id∗ , Iq∗ references) into i∗α ,i∗β references we need Sinθ , Cosθ information(i.e
θ information) which is synchronized with the grid frequency . And the inner PR current
controllers provide high gain means nearly zero steady state error at the frequency of
intrest. Suppose grid frequency changes, to make the PR controller effective we have to
track the grid frequency, which can be done using PLL.
3.4.3
Phase locked loop ( PLL)
PLL can be described basically as a device which is used to obtain the phase angle from
the grid voltages. PLL output signal tracks the input one. Therefore PLL provides
25
3.4. Vector control approach
the frequency and phase angle information . The purpose of it is to generate unit Sine
and Cosine signals which are synchronized with the frequency of the utility voltage and
closed loop control of grid connected power converter requires unit vectors of the PLL to
compute modulating and feedback signals to maintain the control to be very effective.
The inputs of the PLL model are the grid phase voltages and the output is the tracked
phase angle. PLL model is implemented in dq synchronous reference frame which means
that a Park transform from abc to dq reference frame is needed. The Park transform
requires the output angle in order to synchronize the dq reference frame.
The PLL control structure is given as
Figure 3.6: PLL control structure
In this control grid voltage space vector is aligned along q-axis, i.e it has component only
along q-axis and its component along d-axis is zero, which proves as
ab
Figure 3.7: - and d-q frames phasor representation
a
i.e V making an angle wt w.r.t -axis at any instant of time , then wt = 90 + θ
3.4. Vector control approach
26
Vd = Vα Cosθ + Vβ Sinθ
= 1.5Vm Coswt Cosθ + 1.5Vm Sinwt Sinθ
= 1.5Vm Cos(wt − θ)
= 1.5Vm Cos(90 + θ − θ)
=0
Vq = Vβ Cosθ - Vα Sinθ
= 1.5Vm Sinwt Cosθ - 1.5 Vm Coswt Sinθ
= 1.5Vm Sin(wt − θ)
= 1.5Vm Sin(90 + θ − θ)
= 1.5 Vm
Suppose the grid frequency changes then the grid voltage space vector may not aligned
along q-axis, in this case we have both d-axis and q-axis components of grid space vector.Let us assume there is a frequency change , at any instant of time V makes an angle
a
wt w.r.t -axis. But earlier wt = 90 + θ now wt = 90 + θ∗ for small θ∗ variations.
Vd = Vα Cosθ + Vβ Sinθ
= 1.5Vm Coswt Cosθ + 1.5Vm Sinwt Sinθ
= 1.5Vm Cos(wt − θ)
= 1.5Vm Cos(90 + θ∗ − θ)
= -1.5Vm Sin(θ∗ − θ) = -1.5Vm (θ∗ − θ) ; change in θ is very small
Vq = Vβ Cosθ - Vα Sinθ
= 1.5Vm Sinwt Cosθ - 1.5 Vm Coswt Sinθ
= 1.5Vm Sin(wt − θ)
= 1.5Vm Sin(90 + θ∗ − θ) = 1.5Vm Cos(θ∗ − θ)
Since Vd is not zero, which violates our assumption, and analysis becomes difficult.So
to validate our assumption Vd =0, and make the analysis becomes simple ,we have to
synchronize the grid voltage space vector with the q-axis such that both are rotating at
grid frequency. This can be ensured with PLL(Phase locked loop). From the knowledge
of above equations the simplified block diagram of the synchronous dq-PLL is given as
27
3.4. Vector control approach
Figure 3.8: Simplified block diagram of dq-PLL
When the frequency changed at the time 0.1 sec from 50HZ to 51HZ, then
Figure 3.9: Frequency change from 50HZ to 51Hz
X-axis:20ms/div; Y-axis:0.5Hz/sec
The transfer function between θ∗ and θ of the PLL is a second order system. The design
specifications of the PLL is given as follows.
Parameter
Specification
Bandwidth
130 rad/sec
Damping ratio
0.7071
Kp
0.4347
KI
46.1156
Settling time
Around 40ms
Table.3.1 Design specifications of the PLL
So with PLL we can track the frequency of the incoming signal (i.e grid frequency). Under
balanced condition 3-phase synchronous reference frame PLL will track the frequencies
very effectively.
3.4. Vector control approach
3.4.4
28
T.F Implementation and design of PR-current controller
ab
In the stationary reference frame control, the grid currents are transformed into -
reference frame. In this case the variables are sinusoidal, thus PI controller cannot be
used due to the fact that they are not able to track a sinusoidal reference without a
steady state error. Therefore, another controller must be used instead of PI, which is
Proportional-Resonant controller. This PR-controller effectively tracks the sinusoidal
references with almost zero steady state error.
T.F Implementation:
The general scheme of the PR controller is shown in Fig. 3.10.
Figure 3.10: PR-controller structure
The PR-controller form is given as G(s) = Kp +
SKI
S 2 +W02
SKI
S 2 +W02
is the resonant part of the PR-controller
Kp is the proportional part of the PR-controller
The resonant part of the controller can be described as
Figure 3.11: Resonant controller implementation
29
3.4. Vector control approach
0
From the figure q (t) = -Wo p(t)
0
KI
p (t) = Wo ( q(t) +e(t) *( W
))
o
Now apply forward rule to descretize p(t) and q(t), then we have
p(n) – p(n − 1) = Wo *q(n − 1)*Ts + KI * Ts * e(n − 1)
p(n) = p(n − 1) + Wo *q(n − 1)*Ts + KI * Ts * e(n − 1)
q(n) = q(n − 1) - Wo * Ts * p(n)
The over all PR-controller implementation is given as
Y (n) = Kp * e(n) + p(n)
The above equations are the required descete equations to implement PR-controller in
digital domain.
In case of grid connected power converters best performance of PR-controller is obtained
when resonant frequency Wo of the controller is identical with the grid angular frequency.
This controller achieves a very high gain in a narrow frequency band centered around
the resonant frequency.The width of this frequency band depends on the integral time
constant KI . Low value of KI gives narrow band and high value of KI gives wider
band.The following fig.3.11 gives the bode-plot of the only resonant controller for different
integral gains and Wo is set to 50HZ.
Figure 3.12: Bode-plot of the resonant controller
3.4. Vector control approach
30
If the grid frequency changes to ±1Hz around the Wo (50Hz), then PR-controller works
satisfactorily. Suppose grid frequency changes to 47Hz or 55Hz then the performance
of the PR-controller is drastically reduced due to the low gain at that frequency, and
hence we have steady state error even with PR-controller. So to avoid this problem use
adaptive PR-controller means grid frequency is tracked using PLL and set this tracked
grid frequency as Wo of the PR-controller.
Design of PR-current controller
Since the current references are AC quantities a PR-current controller is employed for
the inner current control loop which is set to have a resonance at 50Hz. In this project
switching frequency is 4.882Khz. For good control of the system the inner current control
loop is faster than the outer voltage loop.The typical relation is given as
Band width of inner loop is ≤ (Switching frequency/10)
Band width of outer loop is ≤ (Band width of inner loop/10)
As we know that
KI
which
S
is a integrator, if we convert this
KI
S
from synchronous reference
frame(d-q domain) to stationary reference frame it will appear as a resonant integrator
of the form
2SKI
S 2 +W02
.
ab
I
- frame.ref[2]
i.e Kp + KSI in d-q domain is equivalent to Kp + S2SK
2 +W 2 in
0
So to design a PR-controller it is essential to design a PI-controller first , the current
control loop in d-q frame is given as
Figure 3.13: Block diagram of current control loop.
Where ,
Kc : Current controller gain
Tc : Current controller time constant
31
3.4. Vector control approach
K2 : Gain in the current sensing path
T2 : Current sensing path time constant
Td : Converter delay (normally Ts /2)
The loop transfer function GH(s) is given as
Kc (1+STc )(GK2 )
GH(s) = STc Rs (1+ST
d )(1+STa )(1+ST2 )
The bode plot of the open loop transfer function GH(s) is given in fig.3.14
Figure 3.14: Bode plot of current control open loop transfer function
In this the Bandwidth of the current control loop is choosen as 488Hz and Phase margin=25o ;
by using this information calculate Kp and Tc and hence Kp and KI from the above transfer function.
Finally,
(Kc )dq = (Kc )αβ
(2KI )dq = (KI )αβ .
3.4.5
T.F Implementation and design of PI-voltage controller
T.F Implementation:
The PI (proportional-integral) algorithm computes and transmits a signal which is desired to be controlled. The computed output signal Y(t) from the PI depends on the
3.4. Vector control approach
32
parameters, which are the proportional gain Kp , integral time constant Ti , and the error
e(t). Fig 3.13 shows the general scheme of the PI controller.
Figure 3.15: PI-controller structure
The proportional gain Kp makes a change to the output that is proportional to the
current error value. If the value of the proportional gain is too high, the system can
become unstable. On the other hand, a small value gives a small output response to
a large input error making the controller less sensitive. A pure proportional controller
would not be able to drive the signal at its target value. There would remain a steady
state error usually called offset. In order to make the offset zero, the integral term is
needed.
The integral term contribution is proportional to the magnitude and the duration of the
error. The integral gives the accumulated offset which is then multiplied by the inverse of
the integral time and added to the controller output. The magnitude of the contribution
of the integral term to the overall control action is determined by the integral time Ti .
The integral term accelerates the response of the controller and eliminates the residual
steady-state error that occurs with a pure proportional controller. However, since the
integral term is responding to accumulated errors from the past, it can cause the present
value to overshoot the reference value.
In frequency domain PI-controller is represented as
G(s)= Kp + KSI
By discretizing the above equation using trapezoidal rule of integration we have,
Y (k)=Kp e(k) + KI2∗Ts [(e(k)+e(k − 1)]
33
3.4. Vector control approach
Design of PI-voltage controller:
For DC-bus control conventional PI-controller is sufficient. For voltage controller design
the gain of current control loop is assumed to be unity[1].
Figure 3.16: Block diagram of voltage control loop
Where,
Kv : Voltage controller gain
Tv : Voltage controller time constant
K1 : Gain in the voltage sensing path
T1 : Voltage sensing path time constant
K : A constant, which may be found out from input-output power balance as follows
Considering the unity power factor case
Total power = Vdc Idc =3 Vrms(P hase) Irms(P hase) = 32 Vsq Isq
Idc =
2Vsq
I
3Vdc sq
= KIsq
2Vsq
K = 3V
dc
q
V
= 23 ( LL(rms)
).
Vdc
The loop transfer function GH(s) is given by
KV (1+STV )KK1
GH(s)=( ST
)
V (SC)(1+ST1 )
The bode plot of the open loop transfer function GH(s) is given in fig.3.17
3.5. Conclusions
34
Figure 3.17: Bode plot of voltage control open loop transfer function
In this the bandwidth of the voltage control loop is choosen as 3Hz, and phase margin=73o
By choosing this information calculate the values of KV and TV of the voltage controller
from the above loop transfer function. The design specifications of the closed loop grid
connected FEC setup is given as follows:
Parameter Specification
fswitching
4.882 KHz
fbw(inner)
488 Hz
(Kp )I
1.1625
(KI )I
1308.36
fbw(outer)
3Hz
(KV )V
0.3668
(TV )V
320ms
Table3.2 Design specifications of FEC set-up
3.5
Conclusions
In this chapter concept of stationary reference frame was explained along with PLL,
design of voltage controller and design of current controller in detail. Also comparison
between rotating reference frame and stationary reference frame was included.
Chapter 4
Communication between FPGA and
PC
4.1
Introduction
This chapter explains mainly about serial communication interface between FPGA and
PC.The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. UARTs are commonly used
with RS-232 for communications applications.
RS232 is an asynchronous serial communication protocol widely used in computers and
digital systems. In RS-232, user data is sent as a time-series of bits. Since transmit
data and receive data are separate circuits, the interface can operate in a full duplex
manner, supporting concurrent data flow in both directions. The standard does not
define character framing within the data stream, or character encoding. On PC’s side,
Windows’ HyperTerminal program can be used as a virtual terminal to interact with the
FPGA board.
4.2
UART Interfacing
A universal asynchronous receiver/transmitter (usually abbreviated UART )is a type of
"asynchronous receiver/transmitter", a piece of computer hardware that translates data
between parallel and serial forms. UARTs are commonly used in conjunction with other
communication standards such as EIA RS-232. The Serial Port is harder to interface
35
4.2. UART Interfacing
36
than the Parallel Port. In most cases, any device you connect to the serial port will need
the serial transmission converted back to parallel so that it can be used. This can be
done using a UART.
A UART is a chip with programming that controls a computers interface to its attached
serial devices.On older computers the chips were on the disk 10 controller card. The
UART’s purpose is to convert bytes from PC’s parallel bus to a serial bit stream. The
cable going out of the serial port is serial and has only one wire for each direction of
flow.The serial port sends out a stream of bits, one bit at a time.Conversly, the bit
stream that enters the serial port via the external cable is converted to parallel bytes
that the computer can understand.UART deals with the data in byte sized pieces, which
is conveniently also the size of ASCII characters.
Specifically it provides the computer with the RS-232C DTE interface so that it can talk
to and exchange data with modems and other serial devices. As a part of this interface,
the UART also converts the bytes it receives from the computer along the parallel circuits
into a single serial bit stream for outbound transmission.
4.2.1
Transmitting and receiving serial data
The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes
of data and transmits the individual bits in a sequential fashion. At the destination, a
second UART re-assembles the bits into complete bytes. Serial transmission of digital
information (bits) through a single wire or other medium is much more cost effective than
parallel transmission through multiple wires. A UART is used to convert the transmitted
information between its sequential and parallel form at each end of the link. Each UART
contains a shift register which is the fundamental method of conversion between serial
and parallel forms.
The UART usually does not directly generate or receive the external signals used between
different items of equipment. Typically, separate interface devices are used to convert the
logic level signals of the UART to and from the external signaling levels. UARTs are
commonly used with RS-232 for communication applications.
It is useful to communicate between digitalcontrollers and also with PCs. Many chips
provide UART functionality in silicon, and low-cost chips exist to convert logic level
signals (such as TTL voltages) to RS-232 level signals (for example, Maxim’s MAX232).i.e
37
4.2. UART Interfacing
This MAX232 chip converts logic level signals into RS-232 level signals and vice versa.
This serial communications is of two types, they are
• Synchronous serial communication
• Asynchronous serial communication
4.2.2
Synchronous Serial Transmission
Synchronous serial transmission requires that the sender and receiver share a clock with
one another, or that the sender provide a strobe or other timing signal so that the receiver knows when to “read” the next bit of the data. In most forms of serial Synchronous
communication, if there is no data available at a given instant to transmit, a fill character
must be sent instead so that data is always being transmitted. Synchronous communication is usually more efficient because only data bits are transmitted between sender and
receiver, and synchronous communication can be more costly if extra wiring and circuits
are required to share a clock signal between the sender and receiver.
A form of Synchronous transmission is used with printers and fixed disk devices in that the
data is sent on one set of wires while a clock or strobe is sent on a different wire. Printers
and fixed disk devices are not normally serial devices because most fixed disk interface
standards send an entire word of data for each clock or strobe signal by using a separate
wire for each bit of the word. In the PC industry, these are known as Parallel devices.
The standard serial communications hardware in the PC does not support Synchronous
operations. This mode is described here for comparison purposes only.
4.2.3
Asynchronous Serial Transmission
Asynchronous transmission allows data to be transmitted without the sender having
to send a clock signal to the receiver. Instead, the sender and receiver must agree on
timing parameters in advance and special bits are added to each word, which are used to
synchronize the sending and receiving units.
When a word is given to the UART for Asynchronous transmissions, a bit called the
"Start Bit" is added to the beginning of each word that is to be transmitted. The Start
Bit is used to alert the receiver that a word of data is about to be sent, and to force the
clock in the receiver into synchronization with the clock in the transmitter. These two
4.3. Baud rate
38
clocks must be accurate enough to not have the frequency drift by more than 10% during
the transmission of the remaining bits in the word.
After the Start Bit, the individual bits of the word of data are sent, with the Least
Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for
exactly the same amount of time as all of the other bits, and the receiver “looks” at the
wire at approximately halfway through the period assigned to each bit to determine if
the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver
will examine the signal to determine if it is a 1 or a 0 after one second has passed, then it
will wait two seconds and then examine the value of the next bit, and so on. The sender
does not know when the receiver has “looked” at the value of the bit. The sender only
knows when the clock says to begin transmitting the next bit of the word.
When the entire data word has been sent, the transmitter may add a Parity Bit that the
transmitter generates. The Parity Bit may be used by the receiver to perform simple
error checking. Then at least one Stop Bit is sent by the transmitter.
When the receiver has received all of the bits in the data word, it may check for the
Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used),
and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is
supposed to, the UART considers the entire word to be garbled and will report a Framing
Error to the host processor when the data word is read. The usual cause of a Framing
Error is that the sender and receiver clocks were not running at the same speed, or that
the signal was interrupted.
Regardless of whether the data was received correctly or not, the UART automatically
discards the Start, Parity and Stop bits. If the sender and receiver are configured identically, these bits are not passed to the host. If another word is ready for transmission,
the Start Bit for the new word can be sent as soon as the Stop Bit for the previous word
has been sent. Because asynchronous data is “self synchronizing”, if there is no data to
transmit, the transmission line can be idle.
4.3
Baud rate
Baud is a measurement of transmission speed in asynchronous communication. Because
of advances in modem communication technology, this term is frequently misused when
describing the data rates in newer devices.
39
4.4. RS-232 Interface
Traditionally, a Baud Rate represents the number of bits that are actually being sent
over the media, not the amount of data that is actually moved from one DTE device to
the other. The Baud count includes the overhead bits Start, Stop and Parity that are
generated by the sending UART and removed by the receiving UART. This means that
seven-bit words of data actually take 10 bits to be completely transmitted. Therefore, a
modem capable of moving 300 bits per second from one place to another can normally
only move 30 7-bit words if Parity is used and one Start and Stop bit are present.
If 8-bit data words are used and Parity bits are also used, the data rate falls to 27.27
words per second, because it now takes 11 bits to send the eight-bit words, and the
modem still only sends 300 bits per second.
4.4
RS-232 Interface
RS-232 is mainly used for serial communication between computer and peripheral(FPGA).It
can operate in either half duplex or full duplex mode. The possible baud rates are
1200bps, 2400bps, 4800bps, 9600bps, 19200bps, 38400bps, 57600bps and 115200bps.
• In half duplex mode, communication is possible only in only one direction either
FPGA to computer side or computer to FPGA side and for that only one pin has
to be assigned as a input or output, decided by the direction pin.
• In full duplex mode, communication is possible in both the directions. In full duplex
mode two pins are needed in which one pin will be input and the other pin will be
output decided by the direction pins.
The FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim
device, which in turn, converts the logic value to the appropriate RS-232 voltage level.
Likewise,the Maxim device converts the RS-232 serial input data to LVTTL levels for
the FPGA. A series resistor between the Maxim output pin and the FPGA’s RXD pin
protects against inadvertent logic conflicts such as accidentally connecting the board using
a null-modem cable. In this example, both the FPGA and the external serial device are
driving data on the transmit line.
4.5. Serial communication control structure
4.5
40
Serial communication control structure
Figure 4.1: Block diagram of serial communication control
The above figure shows the serial communication control structure. The design started
by listing down the function of the system to design. Importantly system function in this
project includes:
• 1. Supply clock frequency of the FPGA is 20MHz.
• The sampling frequency of the 12bit ADC is 102.4µs.
• Baud rate choosen is 9600.
• Use a dual port memory to store and access the data used for communication.
The 12bit data acquired from ADC channels is converted to 16bit data inside the FPGA
program, and use 16bit RAM to store this data.The RAM is needed when input sampling
frequency of the signals is faster than serial output frequency. In the above system the
parallel input frequency is nearly 10KHz and series output frequency is 9.6KHz. Normally
the WR(write) clock given to memory is the sampling clock of the ADC and RD(read)
41
4.5. Serial communication control structure
clock needs to be recalculating to a suitable clock speed.The MUX at the output of the
RAM is used to send the signals in proper order and the MUX before the Maxim chip is
used to convert the parallel data to serial data which is then processed through RS-232
cable.
The output of FPGA system is send by a bit 0 as a start, bit and another bit 1 as stop
bit. This design is due to the RS-232 cable specification. To send the data to computer
using RS-232 cable, it required those specifications. RS-232 cable can only send data as
maximum 8bit in a group. After the 8bit data was sent, it will only send the next group
of data when it detects a stop bit and a start bit. So we have to put one start bit and
one stop bit for every 8 bits.
Since Baud rate(number of bits per sec) = 9600
Time for one bit per second is = 1/9600 sec
For every 8 bits we add 1 start and 1 stop bit, so for 16 bit sampling data, total no.of
bits becomes 20.
Time taken to transfer one 16bit sampling data = 20* (1/9600).
Time taken for ‘N’ samples of data = 20N(1/9600)
The “rclk” is refer to the read clock of the RAM. The speed of read data from RAM
need to be adjusts so that the time is enough for RS-232 cable to send all the data to
computer. As shown in Figure 4.1, it actually needs to send 20 data in order to send out
all the data in a single address of RAM. Thus, the speed of the read clock has to be at
least 20 times slower than the data out speed.
4.5. Serial communication control structure
42
Chapter 5
Visual Basic Interface
5.1
Introduction
This chapter discusses how Visual Basic can be used to access serial communication functions. Windows hides much of the complexity of serial communications and automatically
puts any received characters in a receive buffer and characters sent into a transmission
buffer. The receive buffer can be read by the program whenever it has time and the
transmit buffer is emptied when it is free to send characters. The MSComm control
provides the following two ways for handling communications:
Event driven: Event-driven communications is a very powerful method for handling serial
port interactions. In many situations you want to be notified the moment an event takes
place, such as when a character arrives or a change occurs in the Carrier Detect (CD) or
Request To Send (RTS) lines. In such cases, use the MSComm control’s OnComm event
to trap and handle these communications events. The OnComm event also detects and
handles communications errors.
Polling: CommEvent properties can be tested to determine if an event or an error has
occurred. For example, the program can loop waiting for a character to be received. once
it is the character is read from the receive buffer. This method is normally used when
the program has time to poll the communications receiver or that a known response is
imminent.
43
5.2. Basics of Serial Communications
5.2
44
Basics of Serial Communications
Every computer comes with one or more serial ports. They are named successively:
COM1, COM2, etc. On a standard PC, the mouse is usually connected to the COM1
port. A modem may be connected to COM2, a scanner to COM3, etc. Serial ports
provide a channel for the transmission of data from these external serial devices.
The essential function of the serial port is to act as an interpreter between the CPU and
the serial device. As data is sent through the serial port from the CPU, Byte values are
converted to serial bits. When data is received, serial bits are converted to Byte values.
A further layer of interpretation is needed to complete the transmission of data. On
the operating system side, Windows uses a communications driver, Comm.drv, to send
and receive data using standard Windows API functions. The serial device manufacturer
provides a driver that connects its hardware to Windows. When you use the Communications control, you are issuing API functions, which are then interpreted by Comm.drv
and passed to the device driver.
As a programmer, you need only concern yourself with the Windows side of this interaction. As a Visual Basic programmer, you need only concern yourself with the interface
that the Communications control provides to API functions of the Windows communications driver. In other words, you set and monitor properties and events of the Communications control.
5.2.1
Establishing the Serial Connection
The first step in using the Communications control is establishing the connection to the
serial port. The following table lists the properties that are used to establish the serial
connection:
• Commport: Sets and returns the communications port number.
• Settings: Sets and returns the baud rate, parity, data bits, and stop bits as a string.
• Port open: Sets and returns the state of a communications port. Also opens and
closes a port.Sets and returns the communications port number.
45
5.2. Basics of Serial Communications
5.2.2
Opening the serial port.
To open a serial port, use the CommPort, PortOpen, and Settings properties. For example:
’ Open the serial port
MSComm1.CommPort = 2
MSComm1.Settings = "9600,N,8,1"
MSComm1.PortOpen = True
The CommPort property sets which serial port to open. Assuming that a modem is
connected to COM2, the above example sets the value to 2 (COM2) and connects to the
modem. You can set the CommPort property value to any number between 1 and 16
(the default is 1). If, however, you set this value to a COM port that does not exist for
the system on which your application is run, an error will be generated.
The Settings property allows you to specify the baud rate, parity, and the number of data
bits and stop bits. By default, the baud rate is set at 9600. The parity setting is for data
validation. It is commonly not used, and set to "N". The data bits setting specifies the
number of bits that represent a chunk of data. The stop bit indicates when a chunk of
data has been received.
Once you’ve specified which port to open and how data communication is to be handled,
you use the PortOpen property to establish the connection. It is a Boolean value, True or
False. If, however, the port is not functional, if the CommPort property is set incorrectly,
or if the device does not support the settings you’ve specified, an error will be generated
or the external device may not work correctly. Setting the value of the PortOpen property
to False closes the port.
5.2.3
Communication settings
*Setting Receive and Transmit Buffer Properties at Design Time:
When a port is opened, receive and transmit buffers are created. To manage these buffers,
the Communications control provides you with a number of properties that can be set at
design time using the control’s Property Pages.
• Buffer Memory Allocation
5.2. Basics of Serial Communications
46
The InBufferSize and OutBufferSize properties specify how much memory is allocated to
the receive and transmit buffers. The larger you make the number, the less memory you
have available to your application. If, however, your buffer is too small, you run the risk
of overflowing the buffer unless you use handshaking.
• The RThreshold and SThreshold Properties
The RThreshold and SThreshold properties set or return the number of characters that
are received into the receive and transmit buffers before the OnComm event is fired. The
OnComm event is used to monitor and respond to changes in communications states.
Setting the value for each property to zero (0) prevents the OnComm event from firing.
Setting the value to something other than 0 (1, for instance) causes the OnComm event
to be fired every time a single character is received into either buffer.
• The InputLen and EOFEnable Properties
Setting the InputLen property to 0 causes the Communications control to read the entire
contents of the receive buffer when the Input property is used. When reading data from
a machine whose output is formatted in fixed-length blocks of data, the value of this
property can be set appropriately.The EOFEnable property is used to indicate when an
End of File (EOF) character is found during data input. Setting this to True causes
data input to stop and the OnComm event to fire to inform you that this condition has
occurred.
• Managing the Receive and Transmit Buffers
As mentioned above, receive and transmit buffers are created whenever a port is opened.
The receive and transmit buffers are used to store incoming data and to transmit outgoing
data. The Communications control allows you to manage these buffers by providing you
with a number of properties that are used to place and retrieve data, return the size of
each buffer, and handle both text and binary data. Properly managing these buffers is
an important part of using the Communications control.
• The Receive Buffer
The Input property is used to store and retrieve data from the receive buffer. For example,
if you wanted to retrieve data from the receive buffer and display it in a text box, you
might use the following code:
47
5.2. Basics of Serial Communications
TxtDisplay.Text = MSComm1.Input
To retrieve the entire contents of the receive buffer, however, you must first set the InputLen property to 0. This can be done at design or run time. You can also receive
incoming data as either text or binary data by setting the InputMode property to one of
the following Visual Basic constants: comInputModeText or comInputModeBinary. The
data will either be retrieved as string or as binary data in a Byte array. Use comInputModeText for data that uses the ANSI character set and comInputModeBinary for all
other data, such as data that has embedded control characters, Nulls, etc.
As each byte of data is received, it is moved into the receive buffer and the InBufferCount
property is incremented by one. The InBufferCount property, then, can be used to retrieve
the number of bytes in the receive buffer. You can also clear the receive buffer by setting
the value of this property to 0.
• The Transmit Buffer
The Output property is used to send commands and data to the transmit buffer. Like
the Input property, data can be transmitted as either text or binary data. The Output
property, however, must transmit either text or binary data by specifying either a string
or Byte array variant.You can send commands, text strings, or Byte array data with the
Output property. For example:
’ Send an AT command
MSComm1.Output = "ATDT 555-5555" & vbCr
’ Send a text string
MsComm1.Output = "This is a text string" & vbCr
’ Send Byte array data
MSComm1.Output = Out
Transmit lines must end with a carriage return character (vbCr). In the example, Out
is a variant defined as a Byte array: Dim Out() As Byte. If it were a string variant, it
would be defined as: Dim Out() As String.You can monitor the number of bytes in the
transmit buffer by using the OutBufferCount property. You can clear the transmit buffer
by setting this value to 0.
• Handshaking
5.2. Basics of Serial Communications
48
An integral part of managing the receive and transmit buffers is ensuring that the backand-forth transmission of data is successful — that the speed at which the data is being
received does not overflow the buffer limits, for example.Handshaking refers to the internal communications protocol by which data is transferred from the hardware port to the
receive buffer. When a character of data arrives at the serial port, the communications
device has to move it into the receive buffer so that your program can read it. A handshaking protocol ensures that data is not lost due to a buffer overrun, where data arrives
at the port too quickly for the communications device to move the data into the receive
buffer.
You set the Handshaking property to specify the handshaking protocol to be used by
your application. By default, this value is set to none (comNone). You can, however,
specify one of the other following protocols:
Settings
Value
Description
comNone
0
No handshaking (default)
comXonXoff
1
Xon/Xoff handshaking
comRTS
2
RTS/CTS(Request to send/Clear to send) handshaking
comRTSXonXoff
3
Both Request To Send and XON/XOFF handshaking
Table.5.1 Handshaking settings
The protocol that you choose depends upon the device to which you’re connecting. Setting
this value to comRTSXOnXOff supports both of the protocols. If you do set this value to
either comRTS or comRTSXOnXOff, you need to set the RTSEnabled property to True.
Otherwise, you will be able to connect and send, but not receive, data.
• The OnComm Event and the CommEvent Property
Depending upon the scope and functionality of your application, you may need to monitor
and respond to any number of events or errors which may occur during the connection
to another device or in the receipt or transmission of data.The OnComm event and the
CommEvent property allow you to trap and check the value of communication events
and errors.
When a communication event or error occurs, the OnComm event is fired and the value of
the CommEvent property is changed. Therefore, if necessary, you can check the value of
49
5.2. Basics of Serial Communications
the CommEvent property each time the OnComm event is fired. Because communications
(especially over telephone lines) can be unpredictable, trapping these events and errors
allows you to respond to them appropriately.The following table lists the communication
events that will trigger the OnComm event. The values will then be written to the
CommEvent property.
Setting
Value
Description
comEvSend
1
There are S threshold number of characters in the transmit buffer
comEvReceive
2
Received R threshold number of characters.
comEvCTS
3
Change in Clear To Send line
comEvDSR
4
Change in Data Set Ready line.
comEvCD
5
Change in Carrier Detect line.
comEvRing
6
Ring detected. Some UART’s may not support this.
comEvEOF
7
End of File(ASCII Character26) is received.
Table.5.2 Settings of communication events
The following fig gives the design of monitoring of FEC setup by indiacting all the quantities as shown.
Figure 5.1: Monitoring of FEC setup before executing
5.3. Conclusions
50
Intially all the values are set to zero, after that actual values enter into the text boxes,
once the program is executed.
Figure 5.2: Monitoring of FEC setup just after executing
5.3
Conclusions
In this chapter Visual Basic, serial communication essentials were explained in detail.
And Graphical user interface(GUI) which is made in VB to monitor the system was also
included.
Chapter 6
Results and Conclusions
6.1
Introduction
In this chapter the experimental results pertaining to this project were presented. The
experimental results corresponding to PLL, stand alone mode of operation, PR-current
controllers testing, grid connected active front end converter control, monitoring results
were included in this chapter.
6.2
PLL results
X-axis: 5msec/div ; Y-axis: 74V/div
Figure 6.1: Grid line voltages Vry ; Vyb .
51
6.2. PLL results
52
PLL is used to track the frequency of the grid as per its control structure given in fig.3.6.
The line grid voltages are given in fig.6.1 and these sensed line voltages are converted to
phase voltages in FPGA. These phase voltages are given in fig.6.2.
X-axis: 5msec/div ; Y-axis: 74V/div
Figure 6.2: Grid Phase voltages Vr ; Vy
The phase voltages in abc-frame are converted into α − β frame. Then Vα , Vβ are given
in fig.6.3
X-axis: 5msec/div ; Y-axis: 74V/div
Figure 6.3: Voltages Valpha ; Vbeta
53
6.2. PLL results
The voltages in α − β frame are converted to d-q as explained in chapter[3]. The Vd ,
Vq are given in fig.6.4.
X-axis: 5msec/div ; Y-axis: 74V/div
Figure 6.4: Vd ; Vq voltages
The θ which is the PLL output is given to sine table to generate unit Sine, unit Cosine
which are further used in the control structure.The unit Sine, Cosine are given in fig.6.5.
X-axis: 5msec/div ; Y-axis: 1V/div
Figure 6.5: PLL unit Sine ; PLL unit Cosine.
6.2. PLL results
54
The PI-controller output and the frequency output of the PLL is given in fig.6.6
X-axis:50µs/div ; Y-axis:50Hz/div
Figure 6.6: PLL Frequency; PI-controller output
In FPGA variable voltage and variable frequency voltages are generated using sine table,
after that PLL is implemented to track the frequencies of the generated voltages. The
fig.6.7 gives frequency transient when it changes from 25Hz to 50Hz.
X-axis:50ms/div ; Y-axis:25Hz/div
Figure 6.7: Frequency transient when it changes from 25Hz to 50Hz.
55
6.2.1
6.3. Testing of PR-current control loops
Stand alone mode of operation
Apply DC-input to the inverter, and connect a load at the AC terminals of the inverter.
PWM signals can be given to the inverter by comparing PLL sine waves with the triangular wave to ensure the frequency of the grid matches with the inverter output frequency
which gives the correct working of the PLL. For RL load: with R=52.7Ω, L=20mh;
almost unity power factor, M=0.9, i/p DC=88.8V, and o/p rms voltage=29V.
X-axis: 2msec/div ;
Figure 6.8: o/p Phase to neutral voltage; o/p phase current.
6.3
Testing of PR-current control loops
The following fig6.9 is used to test the PR- current controllers
Figure 6.9: PR-current controllers testing setup
6.3. Testing of PR-current control loops
56
Actually controllers are designed for 200V, and variable DC voltage i/p to the inverter is
obtained from Auto-T/Fer and diode bridge rectifier setup available in the lab,then
X-axis: 2msec/div ; Y-axis: 6A(peak)/div
a
Figure 6.10: I actual tracking the ref, when DC bus changes from 0 to 200V
Figure 6.11: Current error when DC-bus changes from 100V to 200V
57
6.3. Testing of PR-current control loops
The PR-current controller testing setup is given in fig.6.9. The following fig.6.12 gives
the current tracking for 0.25P.U.Here 1P.U = (10.60A rms)
X-axis: 10msec/div ; Y-axis: 6A(peak)/div
Figure 6.12: Current tracking for 0.25P.U
The following fig.6.13 gives the current tracking for 1P.U.Here 1P.U = (10.60A rms)
X-axis: 10msec/div ; Y-axis: 15A(peak)/div
Figure 6.13: Current tracking for 1.P.U
6.4. AFEC results
6.4
58
AFEC results
The i/p AC to the rectifier is through auto transformer and the DC bus is precharged
by operating the converter as a diode bridge rectifier.After reaching the preset value(here
164V), apply the PWM signals to boost the DC bus voltage to the required value(here
200V).The fig.6.14 gives the DC bus tracking.
X-axis: 5msec/div ; Y-axis: 43.47V/div
Figure 6.14: DC-bus voltage tracking from 164V to 200V
The following fig.6.15 gives the transient in the DC bus when it changes from preset value
to the reference value.
X-axis: 5msec/div ; Y-axis: 43.47V/div
Figure 6.15: DC-bus voltage transient while tracking
59
6.4. AFEC results
The following fig.6.16 gives the α-currents tracking under loaded condition of the FEC.
Here load R=107Ω and DC bus voltage=200V.In the control as per the P.U analysis
adopted the DAC gives 1A/0.35V.
X-axis: 10msec/div ; Y-axis: 4.7275A(peak)/div
Figure 6.16: Alpha currents([ref]; [actual] tracking under loaded condition
The following fig.6.17 gives the α−currents tracking from no-load to loaded condition of
the FEC. Here load R=107Ω and DC bus voltage=200V
X-axis: 10msec/div ; Y-axis: 4.7275A(peak)/div
Figure 6.17: Alpha currents([ref]; [actual] tracking from no-load to loaded condition
6.4. AFEC results
60
The following fig.6.18 gives the phase current and phase voltage under no-load condition
of the FEC
X-axis: 5msec/div ; Y-axis: 3.1516A(peak)/div
Figure 6.18: Grid phase voltage and current waveforms under no-load
The following fig.6.19 gives the phase current and phase voltage under loaded condition
of the FEC.It can be observed that phase current and phase voltage are in phase which
ensures unity power factor operation. The phase current waveform is taken from the
output of the current sensor.The current sensor specifications are 1A/0.473V.
X-axis: 5msec/div ; Y-axis: 3.1516A(peak)/div
Figure 6.19: Grid phase voltage and current waveforms under R-load(107.5 )
61
6.5
6.5. Monitoring results
Monitoring results
Figure 6.20: DC bus voltage monitoring set-up
6.6. Conclusions
62
Figure 6.21: Snap shot of the monitoring system
6.6
Conclusions
The main objective was to implement the control system of the grid connected front end
converter and monitoring of entire system. Therefore good knowledge about control systems,vector control concepts in stationary reference frame,serial communication between
FPGA and PC and Visual Basic coding has been necessary.
Work Summary
• The required hardware(testing of various cards of the inverter,chopper test on inverter,and digital controller board) has been tested.
63
6.6. Conclusions
• Vector control of grid connected FEC in stationary reference frame has been implemented,and objectives of the control like unity power factor operation, drawing
nearly sinusoidal currents, DC-bus voltage regulation were tested. PLL was also
implemented to track the grid frequency and we can generate the unit vectors which
are used in the control loops.
• Algoritham to transfer the data serially from FPGA board to PC has been implemented.
• Graphical User Interface(GUI) has been made in VB environment for monitoring
the various electrical quantities.
Future Work
The current FPGA board has facility to transfer the data serially from FPGA board to
PC only in one direction.i.e there exists lack of synchronization between the sending end
data by FPGA board and receiving the data by GUI of VB via RS-232 cable.Due to this
monitoring of various(more than one signal) electrical quantities of the system becomes
difficult. So by providing the bi-directional facility to transfer the data serially from
FPGA to PC we can monitor various electrical quantities effectively. And we can extend
ab
the vector control of FEC in - reference frame to unbalanced systems and monitor the
quantities in VB as a virtual CRO.
6.6. Conclusions
64
Bibliography
[1] V.T. Ranganathan, ”Course notes on electric drives”, Dept. of Electrical Engg., Indian
Institute of Science, Bangalore, India.
[2] Digital Control in Power Electronics by Simone Buso and Paolo Mattavelli.
[3] “A Method to Improve PLL Performance Under Abnormal Grid Conditions” Anirban
Ghoshal , Dr. Vinod John Department of Electrical Engineering Indian Institute of
Science, Bangalore.
[4] ”Hardware design documentation of 3 phase, 10kVA Inverter”,Technical Document,
Power Electronics Group, Department of Electrical Engineering, Indian Institute of Science, June 2003.
[5] “ Monitoring system for IM DRIVE” rabidra nath bhunia, DR.Vinod jhon Department
of Electrical Engineering Indian Institute of Science, Bangalore
[6] “FPGA BOARD laboratory document” Department of Electrical Engineering Indian
Institute of Science, Bangalore
[7] “Operation of PLL under distorted utility conditions” Vikram kaura, member IEEE.
[8] Daniel Nahum Zmood, Donald Grahame Holmes,\ Stationary Frame Current Regulation of PWM Inverters with Zero Steady-State Error ", IEEE Transactions on Power
Electronics, vol. 18 (3), 2003.
[9] Fukuda S, Yoda T,\A novel current-tracking method for active lters based on a sinusoidal internal model ", IEEE Transactions in Industrial Applications, vol.37(3), 2001.
[10] R. Teodorescu, F. Blaabjerg, M. Liserre and P.C. Loh,\ Proportional-resonant controllers and filters for grid-connected voltage-source converters ", IEE Proc.-Electr. Power
Appl., Vol. 153, No. 5, September 2006.
65