7/10/2003
Introduction to
Push-Pull and Cascaded
Power Converter
Topologies
Bob Bell
Principal Applications Engineer
July 10, 2003
1
Good Morning !
Welcome to National Semiconductor’s continuing series of ON-Line
Seminars
Today our topic is an introduction to a family of DC-DC power
converters referred to as “Cascaded”
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7/10/2003
About the Presenter
The author, Bob Bell, has been
involved in the power conversion
industry for 20 years, currently a
Principal Applications Engineer for
the National Semiconductor Phoenix
Design Center. The Phoenix Design
Center is developing next generation
power conversion solutions for the
telecommunications market.
Education: BSEE Fairleigh Dickinson
University, Teaneck, NJ
2
© 2003 National Semiconductor Corporation
My name is Bob Bell. I have been employed with National
Semiconductor for 2 years.
I am an application engineer at the National Semiconductor Phoenix
Arizona Design Center
Here at the design center we have a team developing next generation
power conversion solutions for the telecommunications industry.
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7/10/2003
Outline:
Buck Regulator Family Lines
Push-Pull Topology Introduction
Push-Pull Controller
Cascaded Push-Pull Topologies
Cascaded Controller
Cascaded Half-Bridge Topology Introduction
3
Today we will start off with a brief review of common DC to DC power
converter topologies.
Our main interest will be several topologies which apply to isolated DC
to DC converters.
The topologies which we will initially spend the most time with will be the
Buck and the Push-Pull topology.
Following the introduction we will introduce benefits and characteristics
of “Cascading” two topologies together.
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7/10/2003
Common One-Switch Power
Converter Topologies
L
Vin
Vin
Vo
Vo
Buck Converter
Boost Converter
L
Vin
Vi n
Np
Ns
Vo
Np
Ns
Vo
Na ux
Forward Converter
Flyback Converter
4
© 2003 National Semiconductor Corporation
Shown on this chart is the power stage arrangements for some of the
most popular power converter topologies which use a single primary
switching element. The Buck and Boost are the simplest and apply to
non-isolated power converters.
The Forwards and Flyback topology are used in isolated converters
where it is desirable to electrically isolate the Primary and Secondary
grounds.
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7/10/2003
Common Two-Switch Power
Converter Topologies
Vin
L
L
Np
Ns
Vo
Ns
Vin
Vo
Np
Np
Ns
Ns
Half Bridge Converter
Push-Pull Converter
Vin
L
Ns
Vo
Np
Ns
Full Bridge Converter
5
© 2003 National Semiconductor Corporation
Shown on this chart are several popular isolated power converters
which use two or more primary switches. The Push-Pull and Half-Bridge
require two switches while the Full-Bridge requires four switches.
Generally the power capability increases from Push-Pull to Half-Bridge
to Full-Bridge.
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7/10/2003
Buck Regulator Basics
VIN
IL
D*Ts
Ts
Q1
I(Q1)
VOUT
L1
D1
C1
I(D1)
VOUT = D * VIN
6
© 2003 National Semiconductor Corporation
A more detailed look at the anatomy of a Buck regulator shows a
switching section, comprised of Q1 and D1, and an output filter
comprised of L1 and C1.
The Buck regulator is used to efficiently step down voltages.
The output voltage is given as Vin * D, where D is the duty cycle of the
main switch Q.
All of the transfer functions we will show assume the inductor current
does not return to zero during the switching cycle, this is said to be
“Continuous” operation.
The Inductor current is made up of two parts; the switch current from Q1
and the rectifier current D1
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7/10/2003
Buck Converter
Characteristics
•
•
•
•
•
•
•
•
•
Non-Isolated Grounds
Voltage Step-down Only
Single Output Only
Very High Efficiency
Low Output Ripple Current
High Input Ripple Current
High Side (Isolated) Gate Drive Required
Large Achievable Duty Cycle Range
Wide Regulation Range (due to above)
7
© 2003 National Semiconductor Corporation
{Read Chart}
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7/10/2003
Forward Converter
L1
D1
+
Vout
Np
Nr
D2
Ns
C1
+
R
Vin
D3
Q1
Vout = Vin x D x Ns
Np
I(L1)
1
2
3
4
1
2
3
4
1
2
3
4
I(D1) =
I(Q1) x Np/Ns
Same transfer function as a
Buck converter with an
added turns ratio term
I(D2)
8
© 2003 National Semiconductor Corporation
The first isolated topology we will look at is the Forward.
A Forward converter is a transformer isolated Buck regulator
The output inductor current is still the composite of two different switch
currents, in this case D1 and D2.
D1 current is the secondary current from the transformer, which equals
I(Q1) times the turns ratio (Np/Ns)
The transfer function is the same as the Buck regulator with an
additional transformer voltage gain term of Ns/Np
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7/10/2003
Forward Diode Currents
Forward Diode D1
Current
Freewheel
Diode D2
Current
Vin =48V
Vout =3.3V
Iout = 5A
9
© 2003 National Semiconductor Corporation
This slide shows each of the rectifier diode currents which sum together
to form the inductor current.
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7/10/2003
Forward Converter
Characteristics
• A Forward Converter is a Buck type converter
with an added isolation transformer
• Grounds are isolated
• Voltage Step-down or Step-up
• Multiple Outputs Possible
• Low Output Ripple Current
• High Input Ripple Current
• Simple Gate Drive
• Limited Achievable Duty Cycle Range
10
© 2003 National Semiconductor Corporation
{Read Chart}
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7/10/2003
Push-Pull Topology
D1
L
+
Vout
np
C
ns
+
R
-
np
Vin
Vg
ns
D2
Q2
PUSH
Q1
PULL
Vout = Vin x D x Ns x 2
Np
Q1
Q2
D
11
© 2003 National Semiconductor Corporation
The Push-Pull topology is basically a Forward converter with two
primaries.
The primary switches alternately power their respective windings.
When Q1 is active current flows through D1. When Q2 is active current
flows through D2.
The secondary is arranged in a center tapped configuration as shown.
The output filter sees twice the switching frequency of either Q1 or Q2.
The transfer function is similar to the Forward converter, where “D” is
the duty cycle of a given primary, that accounts for the “2X” term.
When neither Q1 nor Q2 are active the output inductor current splits
between the two output diodes.
A transformer reset winding shown on the Forward topology is not
necessary.
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7/10/2003
Push-Pull Switching Waveforms
Output
Inductor
Current I(L1)
Vin = 48V
Vout =3.3V
Iout = 5A
Push Primary
Switch V DS(Q1)
Pull Primary
Switch V DS(Q2)
12
© 2003 National Semiconductor Corporation
Shown here are oscilloscope waveforms for the Drain voltages of the
two primary switches and the output inductor current.
When a given primary is active the Drain voltage is zero and the
alternate switches Drain is 2X the input voltage. This is due to the
transformer voltage bring “reflected” from the active primary to in-active
primary.
When neither switch is active then both Drain voltages are at the input
voltage.
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7/10/2003
Push-Pull Diode Currents
Output Diode
Current I(D1)
Vin = 48V
Vout =3.3V
Iout = 5A
Output Diode
Current I(D2)
13
© 2003 National Semiconductor Corporation
Shown here is the current for each of the two output diodes.
These two current sum to form the output inductor current shown on the
previous slide.
Note that as discussed previously when neither of the primary switches
are active, the output inductor current has a negative slope and flows
half in each of the two secondary diodes.
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7/10/2003
Core Utilization: Forward &
Push-Pull Converters
FLUX DENSITY
B (GAUSS)
FLUX DENSITY
B (GAUSS)
Operation in
Quadrant 1 only
BSAT
BSAT
Operation in
Quadrants 1 & 3
BR
MAGNETIC FIELD
INTENSITY
H (OERSTED)
Forward Converter
B-H Operating Area
MAGNETIC FIELD
INTENSITY
H (OERSTED)
Push-Pull Converter
B-H Operating Area
14
© 2003 National Semiconductor Corporation
Shown here are the transformer BH curves for the Forward and the
Push-Pull topology.
The “X” axis represents Magnetic Field Intensity which is proportional to
the Ampere*Turns.
The “Y axis represents Flux Density which is proportional to the Core
area and the Volt * Seconds for the winding that is active.
The slope is proportional to the primary magnetizing inductance.
The Forward converter operates in a single quadrant of the BH curve,
moving up the curve when the switch is active and resetting during the
OFF time.
The Push-Pull converter operates in two quadrants of the BH curve,
see-sawing back and forth as the each primary is activated.
This important fact allows the maximum power capability of a Pus h-Pull
transformer to be twice that of a Forward transformer.
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7/10/2003
Push-Pull Characteristics
• A Push-Pull Converter is a Buck type converter
with a dual drive winding isolation transformer
• Push-Pull transformers and filters are much
smaller than standard Forward converter filters
• Voltage Stress of the Primary Switches is: Vin *2
• Voltage Step-down or Step-up
• Multiple Outputs Possible
• Low Output Ripple Current
• Lower Input Ripple Current
• Simple Gate Drive (dual)
• Large Achievable Duty Cycle Range
15
© 2003 National Semiconductor Corporation
{Read Chart}
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7/10/2003
LM5030 Push-Pull Controller
Vin
ENABLE
Features
• Internal 15-100V start-up
regulator
• CM control, internal slope
comp.
• Set frequency with single
resistor
– 100k – 600kHz
• Synchronizable Oscillator
• Error amp
• Precision 1.25V reference
• Programmable soft-start
• Dual mode over -current
protection
• Direct opto-coupler interface
• Integrated 1.5A gate drivers
• Fixed output driver deadtime
• Thermal shutdown
OSC
Rt / SYNC
Vcc
OUT1
J
45uA
0
5V
COMP
5K
1.25V
K
SLOPECOMP
RAMP
GENERATOR
S
Vcc
R
OUT2
PWM
100K
VFB
RTN
1.4V
LOGIC
50K
SS
2K
CS
0.5V
0.625V
CLK
SS
Packages: MSOP10,
Vcc
7.7V REG
CLK
10uA
SS / SD
LLP10 (4mm x 4mm)
0.45V
16
SHUTDOWN
COMPARATOR
© 2003 National Semiconductor Corporation
National Semiconductor has developed a controller designed
specifically for the Push-Pull topology.
The LM5030 controller has many innovative features.
Although designed for the Push-Pull topology this versatile controller
can be used for most common power converters
<Read Features>
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7/10/2003
LM5030 Push-Pull Demo Board
Performance:
Input Range: 36 to 75V
Output Voltage: 3.3V
Output Current: 0 to 10A
Board Size: 2.3 x 2.3 x 0.45
Load Regulation: 1%
Line Regulation: 0.1%
Current Limit
Measured Efficiency:
84.5% @ 5A
82.5% @10A
17
© 2003 National Semiconductor Corporation
Shown here is a demo board utilizing the LM5030 controller in a PushPull topology.
The power level is on the low side for a Push-Pull implementation.
The purpose is to demonstrate the operation of the controller.
The waveform shown earlier were taken from this board.
<Read Performance>
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7/10/2003
LM5030 Push-Pull Demo Board
36V-75Vin to +3.3V @ 10A
Input:
36 – 75V
Output:
3.3V @ 10A
18
© 2003 National Semiconductor Corporation
Shown here is the schematic for the 33W demo board.
Note the controller connects directly to the input voltage to provide the
initial bias power on Vcc. Once operational, then the winding o n the
output inductor provides the bias power.
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7/10/2003
LM5030 3G Base Station
RF Power Supply
Performance:
Input Range: 36 to 75V
Output Voltage: 27V
Output Current: 0 to 30A
Board Size: 6 x 4 x 2
Load Regulation: 1%
Line Regulation: 0.1%
Line UVLO, Current Limit
Output OV Protection
Measured Efficiency:
91% @ 30A (810W)
19
© 2003 National Semiconductor Corporation
Shown on this slide is an actual application at the higher end of the
Push-Pull power capability.
This unit is designed to power a telcom Base Station RF Power
Amplifier.
<Read Performance>
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7/10/2003
LM5030 3G Base Station RF Supply
-48Vin to +27V @ 30A
20
© 2003 National Semiconductor Corporation
Shown here is the schematic for the 810W design.
The schematic although more complicated then the 33W design, all of
the same basic blocks exist.
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7/10/2003
Cascaded Buck & Push-Pull
Power Converter (Voltage Fed)
Buck
Stage
Push-Pull
Stage
Vin
Vpp
BUCK
CONTROL
CONTROLLER
FEEDBACK
Buck Control Output is
pulse-width modulated to
regulate Vout
N
: N : 1 : 1
Vout
PUSH
OSCILLATOR
PULL
Push-Pull Outputs operate
continuously, alternating at
50% duty cycle
Buck Stage: Vpp = Vin * D
Push-Pull Stage: Vout = Vpp / N
Overall: Vout = Vin x D/N
21
© 2003 National Semiconductor Corporation
Now let’s combine a Buck Regulator stage and a Push-Pull stage.
The first thing to note here is that,each switch of the Push-Pull Stage is
set to operate alternating at 50% duty cycle. This essentially configures
the PP stage as an ideal DC transformer. A voltage presented to the
Vpp node will be transferred to the output divided by the transformer
turns ratio.
It is the Buck stage that is actually used to regulate the output.
If we combine the Buck Stage transfer function and the Push-Pull stage
transfer function we get the overall transfer function as shown.
The Push-Pull stage is said to be “Voltage Fed” since the Vpp node
contains the output capacitor from the Buck Stage.
The Push-Pull switches actually operate slightly less than 50% duty
cycle such that there is no overlap during the switching transitions.
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7/10/2003
Cascaded Voltage-Fed
Converter Benefits
• A Voltage -Fed Push-Pull Converter is a Buck
type converter consisting of a Buck Regulation
stage followed by (cascaded by) a Push-Pull
Isolation Stage
• The Push-Pull Stage FET voltage stresses are
reduced to Vout x N x 2 over all line conditions
• The output rectification can be easily optimized
due to reduced and fixed voltage stresses
• The output rectification is further optimized
since the power is equally shared between the
rectifiers over all load and line conditions
• Favorable topology for wide input ranges
22
© 2003 National Semiconductor Corporation
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7/10/2003
Current Fed Push-Pull Concept
Buck Stage
Push-Pull Stage
OUTPUT INDUCTOR REMOVED
Vout
33 - 76V
Vcc
Vcc
HB
HI
Vin
HO
HD
HS
LD
LI
BUCK OUT CAP
REMOVED
LO
LM5101
LM5041
Vss
PUSH
FEEDBACK
PULL
FB
•
•
•
•
Push and Pull outputs operate continuously, alternating with a s light overlap.
Output voltage is controlled by the Buck stage which operates at 2X the Push-Pull frequency.
Continuous output current from the Push-Pull stage requires minimal filtering.
High Efficiency achieved with low Push-Pull switching losses and matched Sync rectifier loading
23
© 2003 National Semiconductor Corporation
The cascaded “Voltage Fed” Buck and Push-Pull is a viable design
approach, however there are several large components which can be
removed, while still maintaining all of the performance benefits of the
cascaded approach. On the previous Voltage-fed slide, note we had
2 complete L -C filters. The Buck Stage capacitor and the PP stage
inductor can be removed and actually provide several benefits.
Shown here is a Current-fed cascaded Buck and Push-Pull Stage. The
Push-Pull stage is said to be current fed since only the Buck inductor,
which acts a current source feeds the Push-Pull.
In this case the Push-Pull switches need to have a very small overlap at
the switching transitions to maintain the inductor current path. In the
Voltage-fed a small dead time is required.
An example which we will look at next is a 2.5 Volt output, which has
been designed with an 8 to 1 transformer turns ratio. Working from the
output back yields a voltage at the Vpp node of 20 Volts.
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7/10/2003
Cascaded Current-Fed
Converter Benefits
• A Current-Fed Push-Pull Converter is a Buck
type converter consisting of a Buck Regulation
stage followed by (cascaded by) a Push-Pull
Isolation Stage
• There is no high current output inductor!
• Reduced switching loss in Push-Pull stage
• Favorable topology for multiple outputs since all
outputs are tightly coupled
• Favorable topology for wide input ranges, since
the Buck stage pre -regulates while the Push-Pull
and Secondary operate independently of the
input voltage level
24
© 2003 National Semiconductor Corporation
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7/10/2003
Current-Fed Switching Voltages
Trace 1:
Push_Pull SWPUSHV DS
Vin = 60V
Vout =2.5V
Iout = 20A
Trace 2:
Push_Pull SWPULL V DS
Trace 3:
Buck Stage Switching
Node
Note: There is an overlap
time where both the Push
and the Pull switches
are ON.
This is required to
maintain the inductor
current path.
25
© 2003 National Semiconductor Corporation
Shown here are scope plots of the Push-Pull stage drain voltages and
the voltage at the common junction of the Buck stage switches.
Note that the Buck stage operates at twice the frequency of either the
Push or Pull switch.
Also note the overlap of the of the Push-Pull stage.
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7/10/2003
Current-Fed Push-Pull Switches
Ch 1,2
Push-Pull VDS
Ch 3,4
Push-Pull ID S
Vin = 48V
Vout =2.5V
Iout = 20A
26
© 2003 National Semiconductor Corporation
Shown here are scope plots of the Push-Pull Drain voltages and PushPull switch currents.
On the next slide we will take a more detailed look at the switching
transitions of these waveforms
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7/10/2003
Current-Fed Switch Waveforms
Expanded Scale
Ch 1,2
Push-Pull VDS
Ch 3,4
Push-Pull ID S
Note: Each switch carries
½ the current,
during the overlap time
Vin = 48V
Vout =2.5V
Iout = 20A
27
© 2003 National Semiconductor Corporation
One of the many advantages of the cascaded approach is a reduction in
switching losses in the Push–Pull stage switches.
You can note during the overlap time when both switches are ON the
Buck inductor current divides equally between the two switches. At the
conclusion of the overlap time the drain voltage is already at zero and
therefore the switching losses are cut in half.
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7/10/2003
Why is it important to reduce
secondary rectification losses?
Control
10%
Transformer
20%
Filter Inductor
15%
Secondary
Rectifiers
40%
Primary
Switching
15%
Estimate for typical 3.3V Output, 35 – 80V Input
28
© 2003 National Semiconductor Corporation
Why is it important to pick a topology which offers the best opportunities
to reduce losses in the secondary synchronous rectifiers?
A look at a typical power loss budget of a 3.3V power converter shows
approximately 40% of the overall power conversion losses occur i n the
secondary rectification.
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Comparison of Rectifier
Stresses
Example: 3.3V output, 35-80V input
Topology
Forward
Push-Pull
Cascaded PP
Topology
Forward
Push-Pull
Cascaded PP
Rectifier Voltage
Stresses
Vin x (Ns/Np)
Vin x (Ns/Np) x 2
Vout x 2
Voltage Stresses
for Example
Conditions
20V
26.7V
6.6V
Example: Assumptions
High Line with XFR Ratio 4:1
High Line with XFR Ratio 6:1
All Line conditions XFR Ratio 6:1
Current Ratios for
Example
Conditions
Example: Assumptions
Iout x D and Iout x (1-D)
16 / 84%
Ratio at High Line
50% x Iout
50%
All line conditions
50% x Iout
50%
All line conditions
Rectifier Current
Ratios
29
© 2003 National Semiconductor Corporation
This chart compares secondary rectifier stresses for three of the
topologies we have talked about so far. The comparison example is a
3.3 Volt output with a 35 to 80 Volt input.
On the top chart voltage stresses are compared. As you can see for the
Forward and the Push-Pull the voltage stresses are proportional to the
input voltage. At high line the calculated stresses are mush higher then
the Cascaded topology whose rectifier stresses are only proportional to
Vout.
All of the compared topologies have two secondary rectifiers. The lower
chart compares the ratio of ON times for each topology. The Pus h-Pull
and the Cascade have balanced loading on the two secondary rectifiers.
The loading ratio on the rectifiers for a Forward topology vary in
proportion to the input voltage.
Optimized and reliable designs are more readily accomplished with
balanced loading.
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Sync Rectifier Waveforms
Ch 1
Sync1 VDS
Ch 2
Sync2 VDS
Vin = 48V
Vout =2.5V
Iout = 20A
30
© 2003 National Semiconductor Corporation
This scope plot shows the drain voltage waveforms the two
synchronous rectifiers in a 2.5 Volt output. Excluding the switching
spike, the voltage stress is as expected 5 volts.
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7/10/2003
LM5041 Cascaded PWM
Controller
Features:
• Internal 100V Capable Start-up Bias Regulator
• Programmable Line Under Voltage Lockout with
Adjustable Hysteresis
• Current Mode Control
• Internal Error Amplifier with Reference
• Dual Mode Over-Current Protection
• Internal Push-Pull Gate Drivers with Programmable
Overlap or Deadtime
• Programmable Soft-Start
• Programmable Oscillator with Sync Capability
• Precision Reference
• Thermal Shutdown (165°C)
Packages: TSSOP16 and LLP16 (5 x 5 mm)
31
© 2003 National Semiconductor Corporation
National Semiconductor has developed a controller designed
specifically for Cascaded topologies.
The LM5041 controller has many innovative features.
<Read Features>
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7/10/2003
LM5041 Block Diagram
ENABLE
Vin
Vcc
9V REG
UVLO
2.5V
Vcc
UVLO
Vref
5V REF
LOGIC
45uA
0
SLOPECOMP
RAMP
5V
GENERATOR
COMP
UVLO
HYSTERESIS
(20uA)
OFF TIME
GENERATOR
LM5041-1 ONLY
CLK
5K
0.75V
PWM
HD
100K
FB
1.4V
50K
LD
LOGIC
SS
S
Q
R
Q
CS
2K
0.5V
CLK + LEB
PUSH
OSC
0.6V
DRIVER
CLK
10uA
SS
SS
OSCILLATOR
DIVIDE
BY 2
DEADTIME
OR
OVERLAP
CONTROL
SHUTDOWN
COMPARATOR
Vcc
PULL
ENABLE
0.45V
Vcc
DRIVER
Rt / SYNC
TIME
32
© 2003 National Semiconductor Corporation
Shown here is the block diagram for the LM5041 cascaded controller.
Note on the right are the 4 switch control outputs. Gate drivers are
included within the device for the Push and Pull outputs. A resistor
connected to the TIME pin is used to set either overlap or deadtime of
the Push-Pull outputs. Connecting the resistor to ground sets overlap
time. Connecting the resistor to REF sets deadtime.
The Buck stage outputs are logic level controls which work with
National’s new LM5100 family of Buck Stage Gate drivers.
The bias, control and protection circuits used in this controller are very
similar to the LM5030 controller, which is current mode control.
A unique LM5041 feature is a line under voltage lockout (UVLO) with
adjustable hysteresis.
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7/10/2003
LM5041 Current Fed Push-Pull
Demo Board
Performance:
Input Range: 36 to 75V
Output Voltage: 2.5V
Output Current: 0 to 50A
Board Size: 2.3 x 3.0 x 0.5
Load Regulation: 1%
Line Regulation: 0.1%
Line UVLO, Current Limit
Measured Efficiency:
89% @ 50A
91% @20A
33
© 2003 National Semiconductor Corporation
Cascaded Converter Evaluation Board.
• 125W, 90% Efficient, 40 mV pp Ripple Noise
Input range
-36 to -75 V
Output
+2.5V @ 50 A
4-layer Board
2.3" x 3" x 0.5".
Components mounted on a single side of the board.
Planar magnetic
(Coilcraft standard product).
100V Chipset
LM5041 Cascaded Controller &
LM5101
Synchronous Buck Driver
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7/10/2003
LM5041 / LM5100 Demo Board
2.5V @ 50A Cascaded DC-DC Converter
34
© 2003 National Semiconductor Corporation
Shown here is the schematic for the LM5041 demo board.
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7/10/2003
Cascaded Half-Bridge
Concept
Half-Bridge
Stage
Vout
T1
Buck
Stage
Vin
33 - 76V
L1
VDD
VDD
Vcc
Vin
HD
T1
LD
LM5041
LM5102
LM5100
PUSH
PULL
FB
FEED
BACK
35
© 2003 National Semiconductor Corporation
The Cascaded approach can be extended to many other configurations.
Here a Buck stage is cascaded with a half bridge stage. In this case the
Half-Bridge is said to be voltage fed, since the splitter capacitors are
necessary for proper operation.
This approach offers the benefit of further reduced voltage stresses on
the primary side switches, of (Vout X N) where N is the turns ratio
and a single primary winding.
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7/10/2003
Cascaded Half-Bridge
Characteristics
• A Cascaded Half-Bridge Converter is a Buck type
converter consisting of a Buck Regulation stage
followed by (cascaded by) a Half-Bridge Isolation
Stage.
• The isolation stage is Voltage-Fed.
• Voltage splitter capacitors and a small output stage
inductor are required.
• Dead time is required for Half-Bridge switches
• The Half-Bridge Stage FET stresses are reduced, to
Vout x N. (2x less than the Push-Pull)
36
© 2003 National Semiconductor Corporation
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7/10/2003
Cascaded Full-Bridge Concept
Vout
Full -Bridge
Stage
T1
Buck
Stage
L1
Vin
33 - 76V
VDD
VDD
VDD
Vcc
Vin HD
T1
LD
LM5041
LM5102
LM5100
LM5100
PUSH
PULL
COMP
FEED
BACK
37
© 2003 National Semiconductor Corporation
Another cascaded approach is a Buck Stage cascaded with a FullBridge Stage.
The benefit here is:
Reduced primary FET voltage stress of (Vout X N)
Reduced switch current relative to the half-bridge
and a single primary winding.
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7/10/2003
Cascaded Full-Bridge
Characteristics
• A Cascaded Full-Bridge Converter is a Buck type
converter consisting of a Buck Regulation stage
followed by (cascaded by) a Full-Bridge Isolation
Stage
• The isolation stage is Current-Fed
• No voltage splitter capacitors or output stage
inductor are required as in the Cascaded Half-Bridge
• Overlap time is required for Isolation Stage switches
• The Full-Bridge Stage voltage stresses are Vout x N,
similar to the half-bridge
• Full-Bridge Stage current levels are half that of a
Half-Bridge.
38
© 2003 National Semiconductor Corporation
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7/10/2003
High Side Gate Driver Operation
VIN
Vcc
HI
Q2
LEVEL
SHIFT
VIN
Vcc
HI
Vcc
Q2
LEVEL
SHIFT
Vcc
Q1
LI
• Initially Q1 is activated by Low Side control
• Cboot is charged from Vcc through D1, Q1
• Cboot is charged to (Vcc-Vdiode)
Q1
LI
• Floating Vcc, referenced to Q2 source, is
available for upper gate driver
• Q2 Gate drive voltage is provided by Cboot
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© 2003 National Semiconductor Corporation
High side gate drivers are necessary to drive the Gate of the Buck
Switch.
An effective way to do this is with a “Bootstrapping” technique.
On the left illustration, when a low side switch is ON, charge flows from
Vcc to charge up a high side bootstrap capacitor. The charge on this
capacitor is now available to drive the high side gate as shown on the
right illustration.
National Semiconductor has developed a family of dual gate drivers with
level shifter designed specifically for Buck and Bridge configurations.
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7/10/2003
LM5100, LM5101 High Voltage
Buck Stage Gate Driver
Features
Typical Applications
• 2-Amp Driver for High and Low Side
N- Channel MOSFETs
• Independent inputs (TTL-LM5101,
CMOS-LM5100)
• Bootstraps supply voltage to 116VDC
• Short Propagation Delay (45ns)
• Fast Rise, Fall times (10ns into 1nF)
• Unaffected by supply glitching, HS
ringing
• VDD Supply under-voltage lock-out
(6.7V)
• Low power consumption (1.5mA @
0.5MHz)
• Pin for pin compatible with HIP2100 /
2101
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Package: SOIC-8, LLP-10 (4x4mm)
Cascaded Power Converters
Half Bridge Power Converters
Full Bridge Power Converters
Two Switch Forward Power Converters
Active Clamp Forward Power Converters
HB
UVLO
LEVEL
SHIFT
HO
HS
HI
Vcc
UVLO
LO
LI
Vss
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© 2003 National Semiconductor Corporation
The first two devices I would like to introduce are the LM5100 and the
LM5101.
The devices independently control both a high side and a low side gate.
The LM5100 has CMOS level inputs, while the LM5101 has TTL level
input thresholds.
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7/10/2003
LM5102 Driver with Adjustable
Leading Edge Delay
Features
Typical Applications
• 2-Amp Driver for High and Low Side
MOSFETs
• Independently Adjustable Leading Edge
Delays
• Bootstraps drive high side gate to
116VDC
• Short Propagation Delay (45ns)
• Fast Rise and Fall times (10ns into 1nF)
• VDD Supply under-voltage lock-out (6.7V)
• Low power consumption (1.5mA @
0.5MHz)
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Packages: MSOP-10, LLP-10 (4 x 4mm)
Cascaded Power Converters
Half and Full Bridge Power Converters
Two Switch Forward Power Converters
Active Clamp Forward Power Converters
VDD
HB
HI
HO
HS
DLY
Logic
LI
LO
DLY
Logic
RT1
RT2
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© 2003 National Semiconductor Corporation
The next device is similar to the LM5101 with the addition of
independently adjustable delays for each output.
We will see on the next chart the effect of the added delays.
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7/10/2003
LM5102 Timing Diagram
HI
LM5102
K x RT1
HO
Adjustable Leading
Edge Delay
LI
K x RT2
LO
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© 2003 National Semiconductor Corporation
For the LM5102 each output has independently adjustable leading edge
delays set by resistors R1 and R2. The delays have the effect o n the
outputs to create dead-time. This feature is very useful to prevent
excessive shoot-through currents on switching transitions.
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7/10/2003
LM5104 Driver with Adaptive
Deadtime, Programmable Delay
Typical Applications
Features
• 2Amp Driver for Complementary High and
Low Side FETs
• Adaptive Deadtime with programmable
additional delay
• Single TTL-Level logic input
• Bootstraps drive high side gate to 116VDC
• Short propagation delay (45ns)
• Fast rise and fall times (10ns into 1nF)
• V DD supply under-voltage lock-out (6.7V)
• Low power consumption (1.5mA @ 0.5MHz)
Packages: SOIC-8, LLP-10
• Cascaded Power Converters
• High Voltage Buck Regulators
• Active Clamp Forward Power Converters
VDD
LM5104
HB
Adapt
Logic
IN
Adapt
Logic
IN
K x RT
HO
TPROP
DLY
Logic
HO
HS
DLY
Logic
LO
RT
TPROP
K x RT
LO
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© 2003 National Semiconductor Corporation
The last device in the LM5100 family is the LM5104.
This device has a single input to control both the high and low gates.
This device features an adaptive deadtime feature, whereby a gate is
not enabled until the opposite gate has been turned off. Additional
turn-on delay can be added at each transition set by RT.
This device allows minimal deadtimes while maintaining a robust gate
drive scheme for Buck Stage drive applications with a single input.
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7/10/2003
Summary:
New 100V controllers and drivers enable
higher performance power converters with a
minimum of external components:
LM5030 Push Pull Controller
LM5041 Cascade Controller
LM510X Gate Drivers
Questions or Comments?
http://www.national.com/appinfo/power/hv.html
http://power.national.com
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This concludes my presentation.
All of the devices described today are available for immediate sampling.
At this time we have time for a couple of questions.
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