Analog Circuit Design in
Nanoscale CMOS Technologies
Opportunities and Challenges
Trond Ytterdal
Circuits and Systems Group
Department of Electronics and Telecommunication
Norwegian University of Science and Technology
(NTNU)
2006-2007: Sabbatical at UofT
Room: BA5106
trond@eecg.toronto.edu
October 11, 2006
1
Trond Ytterdal, Department of Electronics and Telecommunication
Outline
• Introduction
• Transistor performance
– How does transistor performance change as
technology is scaled down to nanoscale*
nanoscale dimensions
• Analog circuit performance
– How does analog circuit performance change as
technology is scaled down
*The
2
term nanoscale is used for dimensions less than 100nm
Trond Ytterdal, Department of Electronics and Telecommunication
CMOS technology downscaling
Printed gate length
P
h [μ m]
10
3μm
2μm
Data from INTEL
ITRS Roadmap
1.5μm
1
08
0.8μm
0.5μm
0.35μm
0.18μm
90nm
0.1
45nm
32
32nm
18nm
0.01
1970
1975
1980
1985
1990
1995
2000
2005
2010
2015
2005
2010
2015
Year
Vdd [V]
10
1
0.1
1970
1975
1980
1985
1990
1995
2000
Year
Gate length divided by two approximately every 5 years
3
Trond Ytterdal, Department of Electronics and Telecommunication
Transistor performance
• Transistor performance metrics for analog and RF
design:
–
–
–
–
–
–
–
–
–
4
Transconductance
Intrinsic gain (gm/gds)
Capacitances
Maximum operating
p
g frequency
q
y
Efficiency (gm/Id)
Linearity
Noise
Mismatch
Gate leakage
Trond Ytterdal, Department of Electronics and Telecommunication
Transconductance and intrinsic gain
1.E-03
1.E
03
•
65 nm
1.E-04
90 nm
0.13 um
0.18 um
Transconductance is, for
f all practical
purposes, independent of the
technology node
gm [S]
1.E-05
F a velocity
For
l it saturated
t
t d channel:
h
l
1.E-06
I d = WcoxVeff vs
1.E-07
⇒ g m = Wcox vs
Minimum gate length, same W /L
V ds = 1/2V DD
1.E-08
1
L
⇒ g m does
d
nott scale
l
W ∝ L; cox ∝
1.E-09
1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03
Drain current [A]
70
60
Minimum gate length, same W /L
V ds = 1/2V DD
65 nm
90 nm
0.13 um
0.18 um
gm /gds
50
40
30
20
•
Intrinsic gain is reduced as
technologies are scaled down
down. At the
65nm node the maximum intrinsic
gain is reduced by more than 80%
compared to the g
gain at the 0.18μm
μ
node.
10
0
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
Drain current [A]
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Trond Ytterdal, Department of Electronics and Telecommunication
Transistor capacitances
Capacitancee [fF]
1.1
1.0
0.9
0.8
0.7
Cgs
Cdb
Minimum gate length, same W /L ; V ds = 0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
90nm
0.13um
0.18um
Capacitances extracted from NMOS having minimum
drain and source areas for the given W/L (~3).
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Trond Ytterdal, Department of Electronics and Telecommunication
Maximum operating frequency
• The maximum speed of an amplifier is limited by the
ratio of the transconductance and the capacitance
of a transistor:
fT =
gm
2π(C gs + C gd + Cdb )
2.5E-04
1.0E+12
Minimum
Mi
i
gate length,
l
h same W /L
/
V ds = 1/2V DD
65 nm
1.0E+11
90 nm
2.0E-04
0.18 um
1 5E-04
1.5E
04
1.0E+09
Id [A]
gm /(Cgs +Cdb )/2π [Hz]
0.13 um
1.0E+10
1.0E+08
1.0E-04
1.0E+07
1.0E+06
1.0E+05
1.E-10
5.0E-05
Minimum gate length, same W /L
Vds = 1/2V DD
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
D i currentt [A]
Drain
7
(1)
1.E-04
1.E-03
0.0E+00
1.E+06
90nm
130nm
180nm
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
f T [Hz]
Trond Ytterdal, Department of Electronics and Telecommunication
Potential speed improvement
Potential speeed improvem
ment of scaling
6.0
65 nm
90 nm
0 13 um
0.13
• By scaling down a
potential improvement
in speed can be
obtained compared to
realization in a 0.18μm
technology
0 18 um
0.18
5.0
4.0
3.0
20
2.0
1.0
Minimum gate length, same W /L ; V ds = 1/2V DD
Speed potential normalized to the 0.18μm node
0.0
0
0
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
Drain current [A]
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Trond Ytterdal, Department of Electronics and Telecommunication
Transistor efficiency (gm/ID)
35
90nm
0.13um
Minimum gate length; W /L = 5; V ds = 1V
30
0.18um
0.25um
gm /ID [[1/V]
25
20
15
10
5
0
1.0E-12
1.0E-10
1.0E-08
1.0E-06
1.0E-04
1.0E-02
Drain current [A]
• The transistor is most efficient (maximum bang for
the buck) in weak inversion
• Maximum value is nearly independent of technology
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Trond Ytterdal, Department of Electronics and Telecommunication
Linearity (1)
The Taylor expansion of the small signal drain current of a MOS transistor
can be written as:
2
id = g m v gs + a 2 g m v gs
+ a3 g m v 3gs + L
2
3
+ g ds vds + a 2 g ds vds
+ a3 g ds vds
+L
2
3
+ g mbb vbs
b + a 2 g mb vbs
b + a3 g mb vbs
b +L
2
2
+ a 2 g m g ds v gs vds + a32 g m g ds v gs
vds + a3 g m 2 g ds v gs vds
+L
2
2
+ a 2 g m g mb v gs vbs + a32 g m g mb v gs
+L
vbs + a3 g m 2 g mb v gs vbs
2
2
+ a 2 g ds g mb vds vbs + a32 g ds g mb vds
vbs + a3 g ds 2 g mb vds vbs
+L
+ a3 g m g ds g mb v gs vds vbs + L
Here, the coefficients are the higher order derivatives of the total drain
current with respect to one or more of the control voltages.
voltages For example:
1 ∂2Id
a2 g m =
2
2 ∂Vgs
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Trond Ytterdal, Department of Electronics and Telecommunication
Linearity (2)
1.0E-03
1.0E-05
|a 2gds| [S/V
V]
Second order
nonlinearity in
channel
conductance (gds)
increases as
t h l
technology
iis
scaled down.
90nm
0.13um
0.18um
1.0E-04
1 0E 06
1.0E-06
1.0E-07
1.0E-08
1.0E-09
1.0E-10
1.0E-11
1.0E-12
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
Id [A]
1.0E-02
a 2ggm [S/V]
1 0E 03
1.0E-03
Second order
nonlinearity
li
it iin
transconductance
almost
independent of
technology
90nm
0 13um
0.13um
0.18um
1.0E-04
1 0E 05
1.0E-05
1.0E-06
1.0E-07
1
0E 07
1.0E-10
1.0E-09
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
Id [A]
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Trond Ytterdal, Department of Electronics and Telecommunication
Noise
•
Equivalent noise PSD (power spectral density) referred to
the gate of a transistor connected in a common-source
configuration*:
⎛ γ
K
2
= 4k BT ⎜⎜
+
Vng
⎝ g m WLcox f
⎞
⎟⎟ ; K process dependent
⎠
Si-SiO2 interface noise
Channel noise
– Increases at low current
– Minimum in weak inversion for given current
Traditionally [1], the following expression is used for γ:
⎧2n / 3 in strong inversion
γ=⎨
⎩n / 2 in weak inversion
*Transform
12
valid up to a frequency ω ~ gm/Cgd
Trond Ytterdal, Department of Electronics and Telecommunication
Potential SNR (1)
Thermal noise
I d2
• D
Decreases att llow
current
• Minimum in weak
inversion for a given
current
13
120
65nm
90nm
100
10log((10-6Id 2/Ind 2) [[dB]
1
=
2
γ gm
I nd
4 k BT
Id Id
0.13um
0.18um
80
60
40
20
Minimum gate length, same W /L ; V ds = 1V
0
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
Drain current [A]
Trond Ytterdal, Department of Electronics and Telecommunication
Potential SNR (2)
Flicker noise
2
I nd
=
WLf
⎛g ⎞
4k BTK ⎜⎜ m ⎟⎟
⎝ Id ⎠
80
65nm
2
• D
Decreases att llow
current
• Minimum in weak
inversion for a given
current
14
10log(Id 2/(Ind 2Agate )) [dB]
I d2
90nm (L = 0.1um)
75
0.13um
0.18um
70
65
60
55
Minimum gate length, same W /L ; V ds = V DD /2
50
1.E-11
1.E-09
1.E-07
1.E-05
1.E-03
Drain current [A]
Trond Ytterdal, Department of Electronics and Telecommunication
Mismatch (1)
•
Mismatch of two matched transistors identical by design
can be characterized by:
ΔVT = VT 1 − VT 2 with σVT = σ(ΔVT ) = AVT / WL
Δβ /β = 2(β1 − β 2 ) /((β1 + β 2 ) with σβ = σ(Δβ /β) = Aβ / WL
AVT and Aβ depends on process, layout and more …
•
Based on the quadratic MOS model, one can derive the
following well known formulas:
Same gate voltage:
⎛Δ
ΔII
σ⎜⎜ d
⎝ Id
15
⎞
⎛g
⎞
⎟⎟ = σβ2 + ⎜⎜ m σVT ⎟⎟
⎝ Id
⎠
⎠
Same drain current:
2
⎛I
⎞
2
σ(ΔVG ) = σVT
+ ⎜⎜ d σβ ⎟⎟
⎝ gm
⎠
2
Trond Ytterdal, Department of Electronics and Telecommunication
Mismatch (2)
• Mismatch per unit area decreases as technologies
are scaled down
From theory and ideal scaling:
Gate area required for any given σ(ΔVT)
normalized to the Lmin = 70nm
AVT ∝ tox ∝ Lmin
1000
Relative gate area
IIn reality
lit AVT does
d
nott scale
l as
fast as Lmin
AVT [mV
Vμm]
100
100
10
10
1
0.01
0.1
1
10
Minimum ggate length
g [μ m]]
1
0.01
0.1
1
10
Minimum gate length [μm]
Experimental Data from [2]
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Trond Ytterdal, Department of Electronics and Telecommunication
Gate leakage current (1)
Gate current can NOT be neglected in scaled down
technologies.
Dominated by tunneling current => Relatively
insensitive to device temperature.
1.E-04
Minimum gate length,
gate width = 100μm
1.E-05
90nm (simulated)
0.13um
0.13um (simulated)
0.18um
1.E-06
IG
VG
Gate current [A]
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
1.E-13
1.E-14
0
0.5
1
1.5
2
Gate voltage [V]
g-flavor technologies
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Trond Ytterdal, Department of Electronics and Telecommunication
Gate leakage current (2)
vg
VG
IG
Small signal equivalent
circuit assuming low to
moderate frequencies
and strong inversion
ig
ic
Cox
itunnel
gtunnel
At a given frequency the impedance of the two branches have the
same magnitude
g
and the currents ic and itunnel will be equal
q
in
magnitude. This frequency is given by
ω gateCox = gtunnel
1 gtunnel
⇒ f gate =
2π Cox
Above this frequency,
frequency the total gate current is dominated by ic as in
the traditional case.
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Trond Ytterdal, Department of Electronics and Telecommunication
fgate versus technology
fgate is almost gate area
i d
independent
d t and
d an approximate
i t
expression is given in [3] as:
104
102
101
t (V gs −13.6)
Here, tox is the oxide thickness in
nm and Kfg is 1
1.5⋅10
5⋅1016 for NMOS
and 0.5⋅1016 for PMOS.
100
fgate [Hz]
2 ox
f gate
t ≅ K fg
f Vgs e
90nm
0.13μm
0.18μm
103
10-1
10-2
10-3
10-44
10-5
10-6
A plot of this expression is
shown to the right for three
different technologies.
19
10-7
10-8
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Veff [V]
Trond Ytterdal, Department of Electronics and Telecommunication
Analog circuit performance
• Analog and RF circuit performance metrics:
– Accuracy (Dynamic range)
– Speed
– Power consumption
Accuracy
20
Trond Ytterdal, Department of Electronics and Telecommunication
FOM definition
• One commonly used Figure-of-merit (FOM)
definition:
FOM =
P
DR 2 ⋅ f
Here, P is the power consumption, DR is the
dynamic range and f is the highest signal frequency
that can be processed by the circuit
• Small is GOOD.
21
Trond Ytterdal, Department of Electronics and Telecommunication
Dynamic range (1)
• Here, we define the dynamic range (DR) as the ratio
of the largest to the smallest possible signal
amplitudes.*
• If we assume that DR is limited by noise on the
lower side and the power supply voltage on the
upper side, we can write
DR =
V pp / 2
Vn _ rms
=
ηvVDD
2Vn _ rms
(2)
where, Vpp is the maximum peak-to-peak value of the
signal, Vn_rms is the RMS noise voltage, ηv is the
voltage
l
efficiency
ffi i
defined
d fi d by
b Vpp/VDD.
*The
22
ratio of squared amplitudes is also a common definition
Trond Ytterdal, Department of Electronics and Telecommunication
Dynamic range (2)
• If we assume that matching limits DR on the lower
side we can write
side,
DR =
V pp / 2
κσ(Vos )
=
ηvVDD
2 κσ(Vos )
(3)
• where κ is a yield parameter and σ(Vos) is the
standard deviation of a critical offset voltage in the
circuit.
• We observe for both ((2)) and (3)
( ) that DR scales with
VDD and ηv
For the rest of the talk we assume that DR
is limited by noise on the lower side
23
Trond Ytterdal, Department of Electronics and Telecommunication
Signal-to-noise ratio (SNR)
• SNR is defined as the ratio of the signal power to
the noise power
power. For a sinusoidal signal,
signal the
maximum SNR given by
SNR =
2
V pp
8Vn2_ rms
=
(ηvVDD ) 2
8Vn2_ rms
(4)
• If we compare (4) with (2), we see that
DR = 2 ⋅ SNR
24
(5)
Trond Ytterdal, Department of Electronics and Telecommunication
SNR versus power
VDD
Vpp
IDD
vout
i(t)
Gm
vout
C
vin
VSS
1/f
1
1
1 1
2
fΔq = VDD
fV pp C =
fV pp
C
ηi
ηi
ηv ηi
Here, ηi is the current efficiency of the transconductor and Δq/ηi is the charge
transferred from the power supply in one period and.
and We have assumed that VSS = 0
Power: P = VDD I DD = VDD
SNR:
SNR =
2
V pp
/8
k T
2
⇔ V pp
= 8 B SNR
k BT / C
C
Only thermal noise is considered.
Combining the two equations we get the power required per pole versus SNR:
P=
Based on [1] and [4]
25
8k BT ⋅ f ⋅ SNR
ηi ηv
(6)
Trond Ytterdal, Department of Electronics and Telecommunication
Theoretical FOM
• Rewriting (6) in terms of FOM:
P
8k BT
P
4 k BT
=
⇒
=
2
f ⋅ SNR ηi ηv
ηi ηv
f ⋅ DR
4k T
⇒ FOM = B
ηi ηv
• Ideal world (ηv = ηi = 1):
FOM i = 4k BT
(7)
• Hence,
H
one iimportant question
i becomes:
b
How does ηi and ηv depend on technology?
26
Trond Ytterdal, Department of Electronics and Telecommunication
FOMs based on measurements
• FOMs calculated based on measured performance
of CMOS circuits are always larger than values
obtained using (7) due to one or more of the
following:
DR limited by distortion
Additional noise sources (e.g. flicker noise)
Clock power in switched-capacitor circuits
Poor current efficiency of MOS transistors (it is even
bi dependent)
bias
d
d t)
– Parasitic capacitances
– Matching requirements
–
–
–
–
• Smaller mismatch => larger dimensions => larger
parasitic capacitors
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Trond Ytterdal, Department of Electronics and Telecommunication
Reported FOMs for ADCs
1.0E+14
2 EN O B Fs
FM =
Pdiss
1997
1998
1999
2000
2001
2002
2003
2004
Selection from Walden
Fig
gure of meritt FM [Convers
sions/J]
Philips ISSCC04
1.0E+13
State-of-the-art 2004
Balmelli ISSCC04
Moyal ISSCC03
Miyazaki ISSCC02
Gaggl, ISSCC04
This design(03)
Bjørnsen ESSCIRC05[5]
Kwak (97)
1.0E+12
Kelly, ISSCC01
nAD12110-18(03)
AD9245(03)
Philips ISSCC03
Kulhalli ISSCC02
H
Hernes
ISSCC04
nAD10120-13(03)
1.0E+11
Siragusa ISSCC04
1.0E+10
1 MHz
100 MHz
10 MHz
Conversion Rate [Sample/s]
1 GHz
From [5]
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Trond Ytterdal, Department of Electronics and Telecommunication
Voltage efficiency (ηv)
0.30
• Assume that
65nm
V pp = VDD − 2Vdsat
d t
90nm
0.13um
0.20
Vdsatt [V]
where Vdsat is the
saturation voltage of our
transistors
• To keep ηv unchanged
when we scale down
technology, Vdsat must be
scaled down at the same
rate as VDD.
0.25
0.15
0.10
0.05
0.00
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Veff [V]
Not possible to scale
Vdsat much lower than
75mV
ηv expected to decrease
→ FOM degrades
29
Trond Ytterdal, Department of Electronics and Telecommunication
Current efficiency (ηi)
Assuming CMOS implementation:
The gain bandwidth (GBW) product of a single stage OTA is given by
GBW =
gm
2πC
(8)
Here gm is the transconductance of the input transistor and C is the load
capacitance.
Writing the square of the noise RMS voltages as:
k T
Vn2_ rms = B ,
C
Inserting this equation in (2),
(2) solving for C and inserting in (8) yields
GBW =
g m (ηvVDD ) 2
8πk BT ⋅ DR
2
(9)
Hence, if DR and gm is kept constant, the speed of the circuit decreases
with the square of the supply voltage.
30
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Scenario 1: Dividing VDD by 2
while keeping GBW and DR:
To keep it simple, assume that ηv does not change. From (9)
we note that to keep GBW when supply voltage is reduced by
a factor of 2, gm has to be increased by a factor of 4.
It is common to change the W/L ratio and the drain current by
th same relative
the
l ti amountt in
i order
d to
t keep
k
Veff unchanged
h
d
(adding devices in parallel). Hence, to increase gm by a factor
of 4,, bias current and W/L are increased by
y a factor of 4. If we
assume that all stages of the amplifier are scaled in the same
way, the current consumption will be increased by a factor of
four.
four
→ Power consumption doubles
→ ηi decreases → FOM degrades
Downscaling will not help
31
Trond Ytterdal, Department of Electronics and Telecommunication
Scenario 2: Increasing speed (1)
35
90nm
Minimum gate length; W /L = 5; V ds = 1V
while keeping DR and VDD:
0.13um
30
0.18um
0.25um
25
gm /ID [1/V]
Assume that the frequency of
the first non-dominant pole is
given by (1) and that phase
margin requirements forces a
fixed ratio between fT and
GBW .
20
15
10
5
0
1.0E-12
1.0E-10
1.0E-08
1.0E-06
1.0E-04
1.0E-02
Drain current [A]
2.5E-04
Minimum gate length, same W /L
V ds = 1/2V DD
2.0E-04
1.5E-04
Id [A]
Assume that the required
speed
eed is
i suchh that
th t wee have
h e to
t
push the transistor deep into
strongg inversion.
1.0E-04
5.0E-05
→ηi decreases
→ FOM degrades
g
Downscaling will probably help
0.0E+00
1.E+06
32
90nm
130nm
180nm
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
f T [Hz]
fTmax@90nm
Trond Ytterdal, Department of Electronics and Telecommunication
Scenario 2: Increasing speed (2)
• Watch out for gain
degradation when
increasing speed
70
60
Minimum gate length,
length same W /L
V ds = 1/2V DD
65 nm
90 nm
0.13 um
0.18 um
• If speed increase is
y increasing
g
obtained by
Veff, gain will decrease
gm /gds
50
40
30
20
10
0
1.E-10
→ηi decreases
→ FOM degrades
Downscaling will not help
33
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
Drain current [A]
Trond Ytterdal, Department of Electronics and Telecommunication
Maximizing FOM
Some guidelines for maximizing FOM in nanoscale
CMOS circuits:
• Circuit level:
– Maximize ηv by using as low Veffff as possible
– Identify fTmax in your technology. Stay well below this
frequency to maximize ηi *
– Use
U as hi
high
h supply
l voltage
lt
as possible
ibl (maybe
(
b even
higher than allowed by the foundry)
• Architecture level:
– Avoid high gain requirements (use, for example, gain
calibration))
– Go to interleaved architectures if speed requirements
cause you to move dangerously close to fTmax*
*or
34
switch to a finer technology
Trond Ytterdal, Department of Electronics and Telecommunication
Summary
• Back to near constant voltage scaling (at least for a
while) ☺
• Back to near constant voltage scaling
– Reliability issues: Have to verify circuits versus age
•
•
•
•
•
Speed of transistors ☺
SNR/DR
Mismatch ☺
Linearity
Potential for FOM improvement in some circuits by
scaling down technology* ☺
*One
example is ADCs where transistors are biased in
regions of low current efficiency
35
Trond Ytterdal, Department of Electronics and Telecommunication
List of symbols
Parameter
Parameter
Description
Agate
Gate area
μ
Mobility
β
μcoxW/L
n
Subthreshold ideality factor
Cgs
Gate-source capacitance
T
Absolute temperature
Cgd
Gate-drain capacitance
tox
Oxide thickness
Cdb
Drain-bulk capacitance
VDD
Supply voltage
cox
Oxide capacitance per gate area
Vds
Drain-source voltage
Cox
O id capacitance
Oxide
it
Veff
Vgs – VT
Frequency
Vgs
Gate-source voltage
gm
Transconductance
vs
Saturation velocity
gds
Channel conductance
VT
Threshold voltage
Id
Drain current
W
Gate width
kB
Boltzmann’s
l
’ constant
L
Gate length
f
Lmin
37
Description
Minimum ggate length
g
Trond Ytterdal, Department of Electronics and Telecommunication
References
[1] E.A. Vittoz, “Low Power Design: Ways to Approach the Limits”, SolidState Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC,
pp 14
pp.
14-18,
18 Feb
Feb. 1994.
1994
[2] K. Bult, “Analog Design in Deep Sub-Micron CMOS,” in Proc. ESSCIRC
2000, pp. 11-17.
[3] A. Annema et al., “Analog Circuits in Ultra-Deep-Submicron CMOS,”
IEEE J. of Solid-State Circuits, vol. 40, no. 1, Jan. 2005.
[4] E.A.
E A Vittoz,
Vittoz “Low
Low-power
power Low
Low-Voltage
Voltage Limitations and Prospects in
Analog Design”, in Analog Circuit Design, Editors R.S. van de Plaasche,
W.M.C. Sansen, and J.H. Huijsing, Kluwer Academic Publishers, 1994.
[5] J. Bjørnsen, Ø. Moldsvor, T. Sæther, T. Ytterdal, “A 220mW 14b 40MSPS
Gain Calibrated Pipelined ADC,” in Proc. European Solid-State Circuits
Conference
f
(ESSCIRC)
(
) 2005, Grenoble, Sept.
p 12-14, pp
pp. 165-168, 2005.
38
Trond Ytterdal, Department of Electronics and Telecommunication