Passive Components in CMOS
Technology
Valentino Liberali
Università degli Studi di Pavia
Dipartimento di Elettronica
Via Ferrata 1, 27100 Pavia, Italy
Phone: +39-0382-505226; Fax: +39-0382-505677
e-mail: v.liberali@ele.unipv.it
Contents:
Integrated resistors
Integrated capacitors
EUROPRACTICE Training Course on
Analog CMOS Design with Low-Voltage Issues
Integrated resistors
,,,,
A resistor is made with a given resistive layer.
Insulator
W
L
R = 2 Rcont + R WL
R
(1)
is the sheet resistance measured in ohm per square (
=
I
)
I
t
W
L
For a homogeneous layer :
L = R L
R = Wt
W
The sheet resistance is:
R = t
(2)
(3)
where
= resistivity; t = thickness of the material (fixed by technology)
W = width; L = length of the resistor (chosen by the designer)
INTEGRATED RESISTORS
1
For a non homogeneous layer :
R = G1 = R t 1 = R t 1 W = R WL
0 dG
0 (z ) L dz
(4)
R = Rt 1
0 (z )dz
(5)
where
= conductivity (function of z)
INTEGRATED RESISTORS
2
Resistive layers
Diffused (or implanted) resistors: n and p doped (n+ or p+
source/drain regions).
Nonlinearity effects due to depletion layer modulation are small.
Polysilicon resistors (first poly): n doped.
Shielding from substrate possible by means of well.
With some processes, high-resistivity (i.e. low-doped) poly is
available (1 few k
= ).
Well resistors (n or p, depending on technology).
Nonlinearity effects due to depletion layer modulation.
Pinched well regions (diffused region on the top of the well
increases sheet resistance).
Nonlinearity effects due to depletion layer modulation.
When available:
Second polysilicon resistors (n doped).
Shielding possible.
Isolation resistors (n and/or p doped).
Regions doped with field implantation over an opposite-polarity
substrate.
INTEGRATED RESISTORS
3
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Diffused resistances
n+
p-substrate
n+
p+
p-well
P-well (or N-well) resistance
p+
p+
p-well
n-substrate
Pinched P-well (or N-well) resistance
p+
n+
p+
p-well
n-substrate
INTEGRATED RESISTORS
4
First poly resistance
,
,,,
,
,
,
,,,
,
,,,
,
,
,
,,,
polysilicon
n-substrate
polysilicon
p+
p-well
n-substrate
Second poly resistance
polysilicon
n-substrate
polysilicon
p+
p-well
n-substrate
INTEGRATED RESISTORS
5
Properties of integrated resistors
Value of R :
from few tens = (diffused and polysilicon) to a few k
= (well,
isolation, low-doped poly).
Absolute accuracy:
from 25 to 50 %.
Voltage coefficient (VC):
polysilicon: linear resistors (VC from a few tens to few hundreds ppm/V);
diffused: fairly linear (slighltly worse than poly);
well and isolation: non linear (VC many thousands ppm/V).
Temperature coefficient (TC):
from several hundreds ppm/C (diffused, poly) to several thousands ppm/C (well, isolation).
INTEGRATED RESISTORS
6
,,
,,,,
,
,
For small resistors and for matched resistors: attention to terminal contacts.
A
METAL
B
METAL
R = R WL + 2 Rcont
(6)
For resistor with large L/W: “serpentine layout”.
A
B
INTEGRATED RESISTORS
7
Accuracy
R = t WL
(7)
Standard deviation of the resistance:
2
2
2
2
2
R
t
L
W
(R)2 = R = + t + L + W =
= ()2 + (t)2 + (L)2 + (W )2
(8)
Accuracy is affected by:
process (doping, physical structure, defects)
enviroment (stress, temperature)
t process (doping, diffusivity, deposition rate)
electrical (bias for diffused, well, iso resistors)
L litography (mask making, etching)
design (choice of L)
W litography (mask making, etching)
design (choice of W )
generally W L, therefore W L.
Absolute accuracy is poor.
INTEGRATED RESISTORS
8
Relative accuracy
To obtain good matching:
use identical structures (including end contacts)
place matched elements very close
place matched elements with the same orientation
make resistors of value nR matched to a resistor of value R
(“unity resistor”) by connecting n resistors of value R in series
R1 = R
R2 = 4R
R
R
R
R
avoid small width (and length)
use interdigitized structures (structures made by a number of
“fingers” interleaved to one another)
use common-centroid structures (structures having the same
“gravity” center)
pay attention to boundary effects (use of “dummy” structures
around the array)
pay attention to physical effects such as:
stress (piezoresistance is minimum at 45 in <100> silicon)
temperature (especially in power devices).
Best resistors for good matching: poly and diffused.
Matching within few parts per thousand can be achieved.
INTEGRATED RESISTORS
9
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,,
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,
Side diffusion effect
W
xj
W'
Contribution of endings
1
0.5
0
,
,,
,
,
,,
,
,
,,
,,
,
,,
,
,
,
Interdigitized structure
R2
Dummy strip
Dummy strip
R1
R1
R2
INTEGRATED RESISTORS
10
Typical resistor properties
Layer
R
=
Accuracy
%
n+
2050 2550
p+
50150 2550
poly (no silicide) 30100 2550
high- poly
1kfew k 2550
n-well
1k3k 2550
p-well
2k8k 2550
pinched well
> well 3050
n-iso
2k6k 2550
p-iso
2k8k 2550
TC
ppm/C
2001.5k
2001.5k
2001.5k
2001.5k
several k
several k
several k
several k
several k
VC
ppm/V
50300
50300
20200
20200
several k
several k
several k
several k
several k
Actual values depend on the specific technology.
INTEGRATED RESISTORS
11
Integrated capacitors
A capacitor is made with two conductive layers (electrodes) insulated by means of a dielectric layer.
Different kinds of capacitors are available in CMOS technology:
poly 1 to poly 2 (dielectric is thin silicon dioxide or other, e.g.
thin sandwich of silicon dioxide, silicon nitride, silicon dioxide);
poly to implanted region (high-dose implantation under poly;
dielectric is thin silicon dioxide);
poly to metal 1 (dielectric is intermediated CVD oxide);
metal 1 to diffused active area (dielectric is intermediated CVD
oxide);
metal 1 to metal 2 (dielectric is the intermetal insulator).
Additional (not good) capacitors:
MOS capacitor (i.e.
gate-to-channel MOS capacitance; dielectric is the gate oxide)
, nonlinearities;
reverse-biased junction (dielectric is the depletion region)
, high nonlinearities.
INTEGRATED CAPACITORS
12
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Exmples of integrated capacitors
polysilicon
p+ or n+ diffusion
polysilicon I
polysilicon II
shielding well
INTEGRATED CAPACITORS
13
For parallel-plate capacitors:
C = "r"t0A
(9)
where
A is the electrode area;
t is the dielectric thickness;
"0 is the permittivity of free space;
"r is the relative permittivity of the dielectric.
The capacitance per unit area
CS = "rt"0
(10)
depends on the dielectric properties and thickness.
INTEGRATED CAPACITORS
14
Properties of integrated capacitors
Value of CS :
from few hundredths to 2 fF/m2.
Absolute accuracy:
from 10 to 20 %.
Voltage coefficient:
in the range of few tens to few hundreds ppm/V (much higher
for MOS and junction capacitors).
Temperature coefficient:
in the range of a few tens ppm/C.
INTEGRATED CAPACITORS
15
Accuracy
C = "r"t0A = "r "0tWL
(11)
Standard deviation of the capacitance:
2
2
2
2
2
C
"
t
W
L
r
(C )2 = C = " + t + W + L =
r
= (" )2 + (t)2 + (W )2 + (L)2
r
(12)
Accuracy is affected by:
"
r
process (oxide quality)
enviroment (stress, temperature)
operating point (voltage bias; hysteresis can be present with
some kinds of dielectric)
t process
(growth or deposition conditions; bottom-electrode
structure)
W ,
L litography (mask making, etching)
design (choice of W and L)
Absolute accuracy is better than for resistors.
INTEGRATED CAPACITORS
16
Relative accuracy
To obtain good matching guidelines similar as for resistors (and
transistors) should be followed:
use identical structures (including terminals)
place matched elements very close
place matched elements with the same geometrical orientation
make capacitors of value nC matched to a capacitor of value
C (“unity capacitor”) by connecting n capacitors of value C in
parallel;
for non-unity capacitors, keep the same perimeter-to-area ratio as the unity capacitor (to reduce effects due to overetching
or underetching)
avoid small width or length (use square capacitors)
use suitable shape for unity capacitor
use common-centroid structures
use interleaved structures made by a number of unity capacitors placed in parallel
pay
attention to boundary effects (use “dummy” structures
around the matched array).
Best capacitors for good matching: poly 1 to poly 2 or poly to
implanted region.
Matching better than one part per thousand can be achieved.
INTEGRATED CAPACITORS
17
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Layout example for common-centroid structures
C1
C2
1
C3
1
C4
2
C5
4
8
Unity capacitor
C5
INTEGRATED CAPACITORS
C4
C1 C3
C2
18
Parasitic capacitances
When using capacitors, attention must be paid to parasitic (i.e.
undesired) capacitances of the electrodes.
,,,
,,,,,
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CONNECTION
TOP
C P,T
C
BOTTOM
C P,B
SUBSTRATE
Equivalent circuit
C
TOP
C P,T
BOTTOM
C P,B
SUBSTRATE
Bottom-plate parasitic capacitance CP;B is a non negligible fraction of the desired capacitance C .
From this point of view, the best capacitor is poly 1 to poly 2,
followed by poly to implanted region.
The top plate parasitic capacitance CP;T is smaller.
Connect top plate to parasitic-sensitive nodes.
Pay attention also to stray capacitances due to connections.
INTEGRATED CAPACITORS
19