Power Integrity and EMC Design for High-speed
Circuits Packages
Tzong-Lin Wu, Ph. D.
Professor
Department of Electrical Engineering
Graduate Institute of Communication Engineering
National Taiwan University
Taipei, Taiwan, ROC
1
EMC DL 2008
Outline
•
Power Distribution Network (PDN)
•
Mechanism of Power Noise
•
Issues and Quantification of Power Noise
•
Solutions of Suppressing Power Noise
–
•
2
Decoupling Capacitors
•
Power/ground planes (PKG, PCB)
•
Surface mounted capacitor (PCB, PKG)
•
Embedded capacitor (PKG)
•
On-chip capacitor (Chip)
–
Isolation slots
–
EBG structures
•
Electromagnetic Bandgap (EBG) Power Planes
•
Photonic Crystal Power Layer (PCPL)
Conclusion
EMC DL 2008
Trends for high-performance Electronics
*Source: The International Technology Roadmap for Semiconductor (ITRS), 2007
Year
Feature
Vdd
Chip Freq.
Power
2007
68nm
1.1V
4.70GHz
189W
2010
45nm
1.0V
5.88GHz
198W
2013
32nm
0.9V
7.34GHz
198W
2016
22nm
0.8V
9.18GHz
198W
2019
16nm
0.7V
11.48GHz
198W
Low voltage
3
(http://public.itrs.net)
EMC DL 2008
High speed
Power Distribution Network (PDN)
An Electronic System
Wire bonding
Decoupling capacitor
on Package
Decoupling
capacitor on PCB
Flip chip
Chip
Chip
Ball Bonding
VRM
Ground
Power
4
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Power Distribution Network (PDN)
Chip Level
Wire bonding
Decoupling capacitor
on Package
Decoupling
capacitor on PCB
Flip chip
Chip
Chip
Ball Bonding
VRM
Ground
Power
On-chip capacitor
P/G Grids
Interconnects
Pads
5
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5
Power Distribution Network (PDN)
interconnects for Chip-PKG-PCB
Decoupling
capacitor on PCB
Fine pitch: 50-100um
Line length: 100-200 mil
Wire bonding
Decoupling capacitor
on Package
Flip chip
Chip
Chip
Ball Bonding
VRM
Ground
Power
Bump pitch: 100–300um
BGA Ball pitch: 0.5mm – 1mm
6
EMC DL 2008
Power Distribution Network (PDN)
decoupling capacitors
Wire bonding
Decoupling capacitor
on Package
Flip chip
Chip
Decoupling
capacitor on PCB
Chip
Ball Bonding
VRM
Ground
Power
External electrode
Ceramics
Internal electrode
Impedance (Ω)
Equivalent capacitor circuit
capacitance
ESR
ESL
Impedance = jω ESL +
7
1
+ ESR
jωC
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EMC DL 2008
1/ωC
ωL
Frequency (Hz)
Power Distribution Network (PDN)
PWR/GND Planes
Wire bonding
Decoupling capacitor
on Package
Decoupling
capacitor on PCB
Flip chip
Chip
Chip
Ball Bonding
VRM
Ground
Power
GND
8
EMC DL 2008
Power
Power Distribution Network (PDN)
Equivalent Model
Wire bonding
Decoupling capacitor
on Package
Flip chip
Chip
Decoupling
capacitor on PCB
Chip
Ball Bonding
VRM
Ground
Power
VRM
PCB
P/G Network
Ball
Bonding
PKG P/G
Network
wire
Bonding
Chip
Bulk Capacitor
near VRM
9
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SMT C
on PCB
SMT C
on PKG
On-chip C
Mechanism of the Power Noise : low-speed view
P/G noise arises whenever a changing current
flow through the total inductance of the return
path
VCC Lead
CHIP
VCC
Output
lead
Q1
From
input stage
I cut
I cut C L
Q2
C
I cut
dV
= C L 1− 0
dt
Chip
groud
+
VOUT
RL
VOUT
I OUT
Ground
lead
VGB
switching voltage
transient current
Δ − I noise
b
10
g
EMC DL 2008
Board
inductance
VGB
-
Mechanism of the GBN : high-speed view
Package
Decoupling
capacitance
Pull-Low
loaded
capacitance
Chip
Vcc
GND
Print circuit board
to
p
GND
VCC
bottom
11
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Signal in
A 4-layer PCB
Via
12
Layer 1
Layer 3
Layer 2
Layer 4
EMC DL 2008
P/GBN Coupling through Via Transition (S21)
0
1.5cm
-10
port2(1.5cm,6cm)
-20
port1(4cm,4cm)
via
8cm
-30
S21(dB)
2cm
-40
2cm
via
perfect plane
FDTD modeling
measurement
-50
port3(3cm,1cm)
10cm
SIG1
-60
PWR
-70
GND
-80
0
0.5
1
SIG2
via
trace
power
d=20mils
port2
ground
trace
port1
noise
source
d=40mils
d=20mils
50ohm
13
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1.5
2
2.5
Frequency(GHz)
Freq(GH
z)
0.72
0.906
1.44
1.706
2.31
mnmode
1,0
0,1
2,0
2,1
2,2
Issues caused by power noise
Signal Integrity Issues
Jitter, Skew
Crosstalk
Eye width/height
SSN
Noise current to RF transceiver
EMI Issue
RFI Issues
70
RF sensitivity
Case 1
Case 2
60
EMI
dBμV
50
20 dB
40
30
20
1
2
3
4
5
6
7
Frequency(GHz)
14
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Example of signal integrity issues
Out
OCD
Input
Package
P/N network
Decoupling C
on chip
Out-VSS (V)
VDD
VSS
InputOCD
Package
P/N network
15
Remove
Decoupling C
on chip
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Out
VSS
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Out-VSS (V)
VDD
Example of EMI Issues
7m
absorber
radiation of reference board
tested board
80
TM20
TM02
70
|Ez| at 3m(dBuV/m)
TM10
60
TM21
3m
TM12
TM11
1.2m
TM01
wooden turntable
50
40
3m
30
Spectrum Analyzer
Signal generator
20
10
0
0.2
simulation
measurement
excitation amplitude: 20mV
excitation location: (6cm, 6cm)
30MHz~2GHz
preamp
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Frequency(GHz)
PC Control
16
Cable feed
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Example of RFI Issues
Ideal VCO
VCO’s performance is affected by power noise
17
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Quantification of Power Noise:
Z parameter
I2
PCB
P/G Network
package
Ball
Bonding P/G Network
wire
Bonding
I1
+
V1
V2
VRM
Bulk Capacitor
near VRM
Decoupling C
on PCB
⎡V1 ⎤ ⎡ Z11 Z12 ⎤ ⎡I1 ⎤
⎢V2 ⎥ = ⎢ Z21 Z22 ⎥ × ⎢I2 ⎥
⎣ ⎦ ⎣
⎦ ⎣ ⎦
V1
Z11 =
(Port 2 open)
I1
V2
Z21 =
(Port 2 open)
I1
18
+
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Decoupling C
on package
Decoupling C
on chip
PDN Design:
Lower Z11 (Target impedance)
Lower Z21
-
Measurement of PDN Impedance
Z-parameter and S-parameters
HP 8510C
Transfer impedance
Z 21 = Z 0
2S 21
(1 − S11 )(1 − S 22 ) − S12 S 21
Assume
S11 ≈ S 22 −1 (Low impedance PDN)
Floppy drive
Coaxial Probes
SMA Connector
S12 ⋅ S 21 0, Z0 = 50Ω
port2(4cm,8cm
)
Y
Z 21 ≈ 25 ⋅ S 21
(0,0)
X
Self impedance: (two probes are very close)
Z 0 S 21
Z11 =
2 1 − S 21
19
EMC DL 2008
port1(5cm,4cm
)
1.6mm
10cm
Z11 ≈ 25 ⋅ S 21 (assume S 21 1)
10cm
PCB
P/G Network
[2]
[1]
VRM
10
wire
Bonding
Ball
package
Bonding P/G Network
Bulk Capacitor
near VRM
Decoupling C
on PCB
Capacitance
Given by VRM
Decoupling C
on package
Mag (Z(1,1))
Decoupling C
on chip
Decoupling capacitor
of package
Target impedanceAntiresonance
Antiresonance
on-chip
Capacitance
1
[1]
[2]
[3]
[4]
0.1
10
Resonance
Resonance
Inductance by
•ESL of discrete capacitor
•Power/ground trace
06
10
07
Inductance by
•Power/Ground Plane
•Package via
10
Frequency (Hz)
20
[4] Chip
[3]
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08
10
09
Power/Ground Planes
A Test Sample
port1
4cm
PCB
Die
4cm
8cm
package
Decoupling capacitor
10cm
21
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port2
Power/Ground Planes
Measurement setup
VNA
Power ring
Power via
probe
signal
probe
ground
Ground ring
0.4 mm
package
PCB
10 cm
22
EMC DL 2008
8 cm
Power/Ground Planes
Coupling between PKG and PCB
Measurement Results
0
-10
The SSN could be magnified by the interaction
of these two cavities and degrades the
power integrity of the packaged
integrated circuits.
circuits
S21(dB)
-20
-30
-40
-50
The PDS behavior of combining the package
and PCB is similar to that of considering
only the package.
Bare pkg
Bare PCB
pkg+PCB
-60
-70
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
frequency(GHz)
Sin-Ting Chen, Ting-Kuang Wang, Chi-Wei Tsai, Sung-Moa Wu, James L. Drewniak, Tzong-Lin Wu, “Modeling Noise Coupling
Between Package and PCB Power/Ground Planes with an Efficient 2D-FDTD/Lumped Element Method”, IEEE Transaction on
Advanced Packaging, Vol. 30, No. 4, pp. 864 – pp. 871, Nov. 2007.
23
EMC DL 2008
Power/Ground Planes
Cavity resonance
900 MHz
TM10
24
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1.1GHz
TM11
SMT Capacitors
Decoupling capacitor
on Package
Decoupling
capacitor on PCB
Chip
Ball Bonding
Bulk
capacitor
VRM
Ground
Power
Design Question?
• Locations?
• Numbers?
• Values?
25
EMC DL 2008
SMT Decoupling Capacitors
Capacitors placed either on Package or PCB
package
Testing port
Decoupling capacitor
on Package
Decoupling
capacitor on PCB
Chip
Ball Bonding
Bulk
capacitor
VRM
Ground
Power
Decoupling capacitors
z52 capacitors on package
z63 capacitors on PCB
zCapacitance : 100 nF
zESR : 0.04ohm ESL :0.63nH
26
PCB
EMC DL 2008
SMT Decoupling Capacitors for Suppressing the P/GBN
Capacitors placed either on Package or PCB
-10
The additional resonance peak
worsens the PDN performance.
-20
-30
S21(db)
-40
Decoupling capacitors placed on
package have better performance.
-50
-60
-70
pkg+PCB
pkg+(PCB+cap)
(pkg+cap)+PCB
(pkg+cap)+(PCB+cap)
-80
-90
0
0.5
1
1.5
2
2.5
frequency(GHz)
27
EMC DL 2008
3
3.5
4
4.5
5
The behavior of the PDN is similar
to that with the caps mounted on
the package.
SMT Decoupling Capacitors
Decoupling capacitor
on Package
Capacitors Number Effect
Chip
Decoupling
capacitor on PCB
Ball Bonding
Bulk
capacitor
VRM
Ground
Power
-10
With increasing the
number of decoupling
capacitors, the peaks move
to higher frequency and
their magnitude become
smaller.
-20
-30
S21(db)
-40
-50
-60
-70
C:100nF (on Package)
(pkg+PCB)_no cap
4 cap
8 cap
12 cap
22 cap
52 cap
-80
-90
ESR:0.04ohm
ESL:0.63nH
-100
0
0.2
0.4
0.6
0.8
1
1.2
frequency(GHz)
28
EMC DL 2008
1.4
1.6
1.8
2
SMT Decoupling Capacitors
Capacitance value Effect
100nF capacitors have better performance to reduce noise at low frequency.
-10
-20
S21(dB)
-30
-40
-50
-60
(pkg+PCB)_no cap
12cap_100n
12cap_100p
-70
-80
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
frequency(GHz)
100pF capacitors have better performance at higher frequency. At low frequency, the
capacitors can reduce noise about 8 dB.
29
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Embedded Capacitor
L1
L2
L3
L4
L5
AP5
20um
3~7um
Embedded C
Embedded Capacitor Properties:
AP6
L6
L7
L8
L9
L10
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Dk (10kHz): 3000
Capacitance Density: 1.0 nF/mm2
thickness: 20- 30 um
Cu Electrode thickness: 5~7um
Caps location
7
8
1
2
4
31
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3
2008/8/16
Impedance measurement
Good capacitor is seen below SRF.
SRF is in the several MHz range
due to large ESL of the connecting vias.
The bandwidth could be enhanced by
designing the capacitor closer to the
surface of the package.
Cap4
32
32
Cap (nF)
ESL (pH)
SRF (MHz)
8.87
214
115.6
EMC DL 2008
Isolation by etched slot with bridges
Top layer (1'st layer)
IC
GND plnae
(2nd layer)
Bridged connection
signal traces
Etched slit (Moat)
Vcc plane
(3rd layer)
Substrate
Bottom layer (4th layer)
Z
Y
X
33
Schematic diagram of the Isolated and Bridged
Power Planes in Four Layers PCB Circuits
EMC DL 2008
Isolation slots with bridge
0
reference board
-10
-20
|S12| (dB)
-30
-40
-50
moat-bridged board
-60
-70
Dotted line: measurement
Solid line: 3D-FDTD
excited location: port 2
-80
0
0.5
1
1.5
Frequency(GHz)
33
34
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2
2.5
3
Isolation by etched slot with bridge
(P/G Noise of the bridged board)
leff
TM10 -like
leff
TM10
J. N. Hwang and T. L. Wu,"The Bridging Effect of the Isolation Moat on the EMI Caused by Ground Bounce Noise between Power/Ground planes of
PCB,"2001 IEEE EMC Symposium, Montreal, Canada, Vol. 1, pp. 471 -474, Aug. 2001.
T. L. Wu, J. N. Huang, C. C. Kuo, Y. H. Lin,"Numerical and Experimental Investigation of Radiation Caused by the Switching Noise on the
Partitioned DC Reference Planes of High Speed Digital PCB,” IEEE Transactions on Electromagnetic Compatibility, Feb. 2004.
35
EMC DL 2008
Fundamentals for EBG Structure
circuit view
2Port
1Port
2L
DGS
2L
DGS
2L
DGS
In
⎡A B⎤
⎢C D ⎥
⎣
⎦
Unit Cell
+
Vn
−
I n +1
⎡A B⎤
⎢C D ⎥
⎣
⎦
⎡A B⎤
⎢C D ⎥
⎣
⎦
+
Vn+1
−
d
θ
⎡
⎢ cos 2
⎡A B⎤
=⎢
⎢
⎥
⎣C D ⎦ unit cell ⎢ jY sin θ
⎢⎣ 0
2
θ⎤
jZ 0 sin ⎥
2 ⎡1
⎥
θ ⎥ ⎣⎢0
cos
2 ⎥⎦
X
cos θ − Y0 sin θ
2
θ
⎡
cos
jX ⎤ ⎢
2
⎢
⎥
θ
1 ⎦⎢
jY sin
⎢⎣ 0
2
⎡
⎢
=⎢
⎢ Y0 sin θ (1 + j ) − jXY 2 sin 2 θ
0
⎢⎣ 2
2
36
θ⎤
jZ 0 sin ⎥
2
⎥
θ ⎥
cos
2 ⎥⎦
θ
⎤
⎥
2
⎥
X
cos θ − Y0 sin θ ⎥
⎥⎦
2
jX cos 2
Fundamentals for EBG Structure
circuit view
•
5
Case 1 : (Pass Band)
α = 0 β ≠ 0, π
cos β d = cos θ −
2
3
βd(rad)
αd(Np)
4
2
cos θ −
X
Z 0 sin θ
2
X
Z 0 sin θ ≤ 1
2
1
•
0
Case 2 : (Stop Band)
0
0
2
4
6
Frequency(GHz)
8
α ≠ 0 β =0,π
cosh α d = cos θ −
37
X
Z 0 sin θ ≥ 1
2
Fundamentals for EBG/PBG Structure
wave view
1D
3D
38
2D
Fundamentals for EBG/PBG Structure
wave view
1D example (no DK contrast)
39
39
Fundamentals for EBG/PBG Structure
wave view
Photonic Bandgap
Photonic Bandgap
40
40
Fundamentals for EBG/PBG Structure
wave view
E-field for mode at top of band I
Local power in E-field , top of band I
High-DK
Low-DK
E-field for mode at bottom of band II
Local power in E-field, bottom of band II
41
High-DK
Low-DK
41
High-impedance Surface (mush-room)
concept
Z0 , β
Cp
LV
Z0 , β
f start =
1
μ h⎤
⎡
2π C p ⎢ Lv + 0 ⎥
4 ⎦
⎣
Shawn D. Rogers, “Electromagnetic-Bandgap Layers for Broad-Band Suppression of TEM Modes in Power Planes”, IEEE Trans. Microwave
Theory and Tech., Vol.53, No. 8, pp.2495-2505, Aug. 2005
42
High-impedance Surface (mush-room)
bandwidth enhancement
Cascaded HIS: to improve the bandwidth
Shahrooz Shahparnia and Omar M. Ramahi, “Electromagnetic Interference (EMI) Reduction From Printed Circuit Boards (PCB) Using Electromagnetic
Bandgap Structures”, IEEE Trans. Electromagntic Compatibility, Vol.46, No.4, Nov. 2004.
43
High-impedance Surface (mush-room)
bandwidth enhancement
(c) Double-Stacked HIS
(d) Spiral HIS
Jongbae Park, Albert Chee W. Lu, Kai M. Chua, Lai L. Wai, Junho Lee, and Joungho Kim, “Double-Stacked EBG Structure for Wideband Suppression of
Simultaneous Switching Noise in LTCC-Based SiP Applications”, IEEE Microwave and Wireless Components Letters, vol. 15, No.8, pp. 505-507, Aug.
2005.
Chien-Lin Wang, Guang-Hwa Shiue, and Ruey-Beei Wu, “EBG-Enhanced Split Power Planes for Wideband
Noise Suppression”, Proc. IEEE 14th Topical Meeting Elect. Performance Electron. Package., 2005, pp.61-64.
44
Electromagnetic Bandgap (EBG) Power Planes
• Broadband suppression of the P/GBN
• Low EMI caused by the P/GBN
• Isotropically elimination of the P/GBN
• Very low cost
Power Plane
Ground Plane
Tzong-Lin Wu, Yen-Hui Lin, and Sin-Ting Chen, “A Novel Power Planes With Low Radiation and Broadband Suppression of Ground
Bounce Noise Using Photonic Bandgap Structures,” IEEE Microwave and Wireless Components Letters, Vol. 14, No. 7, pp. 337-339, Jul. 2004
45
EMC DL 2008
1D-equivalent circuit model
d
l
p1
ε r = 4.3
Cg
Lp
i2 n −2
Cp
i2 n−1
Lb
p2
w
Lp
i2n
Cb
2n − 2 2 n − 1
Q2 n−2 Q 2 n −1
40
46
Cg
EMC DL 2008
Cp
i2 n+1
2n
Q2n
Cg
Lp
Lb
i2 n +2
Cb
2n + 1
Q 2 n +1
Cp
Lp
i2 n +3 L b
Cb
2n + 2 2n + 3
Q2 n + 2 Q2n+3
P/GBN suppression— Frequency domain
Power plane
z
90mm
y
h = 0.4mm
x
(0,0)
GND plane
90mm
Reference board
-10
|S21| (dB)
-30
-50
-70
9-cell LPC-EBG board
-90 excited location: (45mm, 45mm)
Solid line: 2D-FDTD
Dotted line: measurement
received location: (15mm, 75mm)
-110
0
44
47
1
2
3
Frequency(GHz)
EMC DL 2008
4
5
6
P/GBN suppression— Time domain (3D-FDTD)
Power plane
z
90mm
y
0.5
h = 0.4mm
x
(0,0)
GND plane
90mm
excited source: 20mV Gaussian pulse
0.4
excited location: (45mm, 45mm)
Voltage(mV)
0.3
received location: (15mm, 75mm)
0.2
0.1
0
-0.1
-0.2
Reference board
9-cell LPC-EBG board
-0.3
-0.4
0
5
10
15
20
25
30
Time(ns)
There is over 35% of the GBN suppression
rate by LPC-EBG power plane design.
46
48
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P/GBN suppression — Time domain (measurement)
Excitation source(2.25GHz clock with
amplitude of ±125mV)
Excited port (45mm, 45mm)
received port (15mm, 75mm)
47
49
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9cell-EBG board (peak to peak 7mV)
EMI elimination
— LPC-EBG structure
7m
Absorber
Horn Antenna
Test Board
3m
3m
70
Wooden
Table
Reference board
60
20mV
Signal generator
Spectrum Analyzer
E_max(dBuV/m)
PreAmp
50
40
30
9-cell LPC-EBG board
20
10
excited amplitude: 20mV
excited location: (45mm, 45mm)
EMI at 3m
Solid line: 3D-FDTD
Dotted line: measurement
0
0
0.5
1
1.5
2
2.5
Frequency(GHz)
48
50
EMC DL 2008
3
3.5
4
Impact on SI — Traces referring to EBG planes
w=0.5mm
w=0.75mm
0.4mm
30mm
Port2
Port1
0.4mm
0.4mm
0.4mm
0.4mm
10mm
(45mm, 49mm)
ε r = 4.3
0.4mm
Port1
30mm
10mm
Port4
Port2
Port3
(45mm, 49mm)
εr = 4.3
s=0.25mm
20mm
20mm
MEO=363mV MEW=370ps
MEO=471mV MEW=389ps
Reference board (with solid power/ground planes)
MEO=440mV MEW=388ps
Tzong-Lin Wu, Yen-Hui Lin, Ting-Kuang Wang, Chien-Chung Wang, and Sin-Ting Chen, “Electromagnetic Bandgap Power/Ground Planes for
Wideband Suppression of Ground Bounce Noise and Radiated Emission in High-speed Circuits,” IEEE Transactions on Microwave Theory and
Techniques, vol. 53, No. 9, pp. 2935 - 2942, Sept. 2005
49
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EMC DL 2008
L-bridged EBG Power Plane
a = 9 cm
Power plane
b = 9 cm
h = 0.4 mm
Ground
plane
a = 9 cm
Substrate
Reference
board
Power plane
b=9
cm
h = 0.4 mm
Ground
plane
Substrate
L-bridged EBG
board
Tzong Lin Wu, Yen-Hui Lin and Ting-Kuang Wang, “A Novel Power Plane with super-Wideband Elimination of Ground Bounce Noise on High
Speed Circuits,” IEEE Microwave and Wireless Components Letters, Vol. 15, No. 3, pp. 174-176, Mar. 2005
52
EMC DL 2008
L-bridged EBG geometrical parameters
Power plane
port2
90 mm
port1
a
Ground plane
a = 30 mm
w
90 mm
w = 6.65 mm
90mm x 90mm x 0.4mm
g1 = 0.1 mm
l
g2 = 0.2 mm
g2
g3
Unit Cell
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EMC DL 2008
g3 = 0.75 mm
l = 15.2 mm
Wideband suppression
0
reference
S21(dB)
-20
-40
-60
L-bridged
-80
FDTD
FEM
Measurement
-100
0
1
2
3
Frequency(GHz)
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EMC DL 2008
4
5
6
EMI performance
50
45
Ez at 3m (dBuv/m)
40
35
30
25
20
15
Measurement
reference
L-bridged
10
5
0.05
0.55
1.05
1.55
2.05
Frequency (GHz)
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EMC DL 2008
2.55
EMS measurement setup
¾ According to IEC61000-4-3
z
Modulation：CW
z
Frequency Range：80 MHz ~ 3 GHz
z
Dwell time：1 sec
z
Frequency step：2%
z
Electric field intensity：3 V/m
Hung-Chun Kuo Sin-Ting Chen Tzong-Lin Wu , “Improving the Radiated Immunity of the Strip-Lines Using a Novel Hybrid EBG Structure“,
IEEE 15th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), Scottsdale, AZ, USA, 2006
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EMC DL 2008
EMS frequency-domain response
14
solid line: simulation
dash line: measurement
12
10
Reference board
EBG board
mV
8
6
4
2
0
0
0.5
1
1.5
Frequency(GHz)
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EMC DL 2008
2
2.5
3
Photonic Crystal Power Layer (PCPL)
Multilayer PCB substrate
Tzong-Lin Wu and Sin-Ting Chen, “An Electromagnetic Crystal Power Substrate with Efficient Suppression of Power/Ground Plane Noise on
High-speed Circuits,” IEEE Microwave and Wireless Components Letters, VOL. 16, NO. 7, Page(s):413 - 415, Jun. 2006
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EMC DL 2008
The geometry of the PCPL
High-DK material
Square lattice
High-DK material
εr =110
Q=1003 (f = 7GHz)
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EMC DL 2008
Dispersion diagram for the PCPL
9
8
Frequency (GHz)
7
6
5
4
3
2
1
0
Γ
X
M
Γ
The dots -- FDTD method
The solid lines -- MIT photonic band tool
SL-PCPL
In this diagram, the bandgap is represented by frequency range in which there is no
propagating mode for any propagation vectors.
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EMC DL 2008
P/GBN suppression – Frequency domain
Bandgaps
0
reference board
-20
S21(dB)
-40
-60
Ceff
-80
simulation
measurement
SL-PCPL
-100
-120
0
1
2
3
4
5
6
7
Frequency(GHz)
ε eff = Ar ε r1 + (1 − Ar )ε r 0
ε eff = 10.348
Ceff = 716pF
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EMC DL 2008
8
P/GBN suppression – Time domain
200
150
The waveform of the excitation source
10Gbps and amplitude ±125 mV
100
50
mv 0
Square lattice
-50
200
-100
-150
150
Reference board
SL-PCPL
100
50
-200
0
mv 0
-50
-100
171.2 mV
-200
0
0.2
0.4
0.6
0.8
Time (ns)
SSN can be reduced about 91%
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EMC DL 2008
0.4
0.6
Time (ns)
16.1 mV
-150
0.2
1
0.8
1
Signal Integrity Performance
W = 1 .1 8 3 m m
P ort 1
P ort 2
0 .4 m m
0 .8 m m
ε r = 2 .3 3
0 .4 m m
S q u a r e la ttice o r
tria n g u la r la ttice
Input signal :
29-1 pseudo random bit sequence (PRBS), nonreturn to zero (NRZ), coded at 10GHz.
Bit rate : 10 Gbps
Amplitude : 500 mv
Edge rate : 35 ps
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EMC DL 2008
Eye Pattern Simulation (TL-PCPL)
MEO = 245 mV, MEW = 72 ps
MEO = 292 mV, MEW = 85 ps
Ref brd
PCPL
MEO Æ Maximum Eye Open
MEW Æ Maximum Eye Width
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EMC DL 2008
EMI elimination — PCPL structure
Bandgap
110
100
reference board
EMI (dBuv/m)
90
80
70
60
measurement
simulation
50
SL-PCPL
40
1
2
3
4
5
6
7
8
Frequency (GHz)
At the frequency range of the bandgap, the radiation resulted from the SSN is significantly
suppressed with over 30dB reduction.
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EMC DL 2008
Gap map for PCPL structure
Area of maximum bandwidth for the first bandgap
0.4
Frequency (£sa/2£kC)
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
r/a
The substrate almost filled with high-DK rods
For the application, we need the broad stopband at low frequency. Therefore, there is
design tradeoff between the bandwidth and the center frequency for the PCPL structure.
Tzong-Lin Wu, Sin-Ting Chen, “A photonic crystal power/ground layer for eliminating simultaneously switching noise in high-speed circuit,”
IEEE Transactions on Microwave Theory and Techniques, VOL. 54, NO. 8, pp. 3398 - 3406, Sept. 2006
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EMC DL 2008
Gap map of the PCPL structure for different dielectric
constant
0.4
K=150
Frequency (£sa/2£kC)
0.35
K=110
K=50
0.3
0.25
0.2
0.15
0.1
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
r/a
67
•
The bandgap appears at smaller r/a for larger dielectric constant.
•
The center frequency of the band at the same r/a is higher for the
smaller dielectric constant.
EMC DL 2008
Conclusion
• P/GBN is one of the key issues for designing high-speed digital circuit with
good signal integrity (SI) and EMC performance.
• Several approaches to eliminate the P/GBN on the power delivery systems
are investigated by both numerical simulations and experimental measurement.
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EMC DL 2008