Predicting and Controlling
Common Mode Noise from
High Speed Differential Signals
Bruce Archambeault, Ph.D.
IEEE Fellow, iNARTE Certified Master EMC Design
Engineer, Missouri University of Science & Technology
Adjunct Professor
bruce@brucearch.com
May 2014
Why Control Common Mode Noise
in Differential Pairs?
• Common Mode Noise is inevitable in
differential pairs
– Skew
– Rise/fall time mismatch
– Asymmetry in channel
• Common mode noise is a big problem in
EMC!
• Common mode noise can increase
differential crosstalk
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Common-Mode Noise on PCB
Differential
microstrip pair
Differential
driver
Noise
(crosstalk)
Common-mode
current
Noise
(emissions)
Noise (emissions)
Multilayer PCB
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Common Mode Noise Due to Skew
• Small amounts of skew create significant
common mode nose
• As little as 1% of bit width for skew can
have significant EMI effects
• As little as 10% of bit width skew creates
CM signal of equivalent amplitude as initial
signals
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Individual Channels of Differential Signal with Skew
2 Gb/s with 50 ps Rise and Fall Time (+/- 1.0 volts)
0.6
0.4
Voltage
0.2
0
Channel 1
No Skew
10 ps
20 ps
50 ps
100 ps
150 ps
200 ps
-0.2
-0.4
-0.6
5.0E-10
1.0E-09
1.5E-09
2.0E-09
2.5E-09
3.0E-09
Time (seconds)
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Common Mode Voltage on Differential Pair Due to In-Pair Skew
2 Gb/s with 50 ps Rise and Fall Time (+/- 1.0 volts)
0.6
0.4
Amplitude (volts)
0.2
0.0
10 ps
20 ps
50 ps
100 ps
150 ps
200 ps
-0.2
-0.4
-0.6
5.0E-10
1.0E-09
1.5E-09
2.0E-09
2.5E-09
3.0E-09
3.5E-09
4.0E-09
4.5E-09
5.0E-09
Time (seconds)
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Common Mode Voltage on Differential Pair Due to In-Pair Skew
2 Gb/s with 50 ps Rise and Fall Time (+/- 1.0 volts)
110
10 ps
20 ps
50 ps
100 ps
150 ps
200 ps
105
100
Level (dBuV)
95
90
85
80
75
70
65
60
0.0E+00
1.0E+09
2.0E+09
3.0E+09
4.0E+09
5.0E+09
6.0E+09
7.0E+09
8.0E+09
9.0E+09
1.0E+10
Frequency (Hz)
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Common Mode from Rise/Fall Time
Mismatch
• Small amounts of mismatch create
significant CM noise
• Not as significant as skew, but harder to
control!
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Example of Effect for Differential Signal with Rise/Fall Time Mismatch
2 Gb/s Square Wave (Rise/Fall = 50 & 100 ps)
0.6
Channel 1
0.4
Channel 2
T/R=50/100ps
Voltage
0.2
0
-0.2
-0.4
-0.6
0.0E+00
2.0E-10
4.0E-10
6.0E-10
8.0E-10
1.0E-09
1.2E-09
1.4E-09
1.6E-09
1.8E-09
2.0E-09
Time (Seconds)
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Common Mode Voltage on Differential Pair Due to Rise/Fall Time Mismatch
2 Gb/s with Differential Signal +/- 1.0 Volts
0.2
T/R=50/100ps
T/R=50/150ps
T/R=50/200ps
0.15
0.1
Level (volts)
0.05
0
-0.05
-0.1
-0.15
-0.2
0
5E-10
1E-09
1.5E-09
2E-09
2.5E-09
3E-09
3.5E-09
4E-09
4.5E-09
5E-09
Time (seconds)
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Common Mode Voltage on Differential Pair Due to Rise/Fall Time Mismatch
2 Gb/s with Differential Signal +/- 1.0 Volts
100
95
T/R=50/55ps
T/R=50/100ps
T/R=50/150ps
T/R=50/200ps
90
Level (dBuV)
85
80
75
70
65
60
55
50
0.0E+00
2.0E+09
4.0E+09
6.0E+09
8.0E+09
1.0E+10
Frequency (Hz)
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Common Mode from Amplitude
Mismatch
• Small amounts of mismatch create
significant CM noise
• Harmonics are additive with other sources
of CM noise
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Common Mode Voltage on Differential Pair Due to Amplitude Mismatch
Clock 2 Gb/s with (100 ps Rise/Fall Time) Nominal Differential Signal +/- 1.0 V
0.06
0.04
Amplitude (volts)
0.02
0.00
-0.02
10 mV Mismatch
25 mV Mismatch
50 mV Mismatch
100 mV Mismatch
150 mV Mismatch
-0.04
-0.06
0.0E+00
5.0E-10
1.0E-09
1.5E-09
2.0E-09
2.5E-09
3.0E-09
3.5E-09
4.0E-09
4.5E-09
5.0E-09
Time (Seconds)
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Bruce Archambeault, PhD
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Common Mode Voltage on Differential Pair Due to Amplitude Mismatch
Clock 2 Gb/s with (100 ps Rise/Fall Time)
Nominal Differential Signal +/- 1.0 Volts
90
80
10 mV Mismatch
25 mV Mismatch
50 mV Mismatch
100 mV Mismatch
150 mV Mismatch
Level (dBuV)
70
60
50
40
30
20
0.0E+00
1.0E+09
2.0E+09
3.0E+09
4.0E+09
5.0E+09
6.0E+09
7.0E+09
8.0E+09
9.0E+09
1.0E+10
Frequency (Hz)
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Mode Conversion Example For High Speed Connector
(Simulation Data)
0
-10
Scd21 (dB)
-20
-30
-40
-50
Uncompensated Port3,Port1
Uncompensated Port4,Port2
Compensated Port3,Port1
Compensated Port4,Port2
-60
-70
0
5
10
15
20
25
Frequency (MHz)
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Compensation
• Added extra trace length before connector
to compensate for connector pin mismatch
• End-to-end SI sees the improvement
• EMC does not see the improvement
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Via Symmetry Effect on Common Mode
Conversion
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Cable Shielding Important
• Different cables have different amounts of
shielding
• Likely to vary with frequency
• May vary from vendor to vendor
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Measured Shielding Effectiveness for
Various USB Cables
Courtesy of Dana Bergey, FCI
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How Much is Too Much?
• Start with source
amplitude
– Near end will have full
amplitude
– 5 Gb/s
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How Much is Too Much Skew?
• Most of skew comes from PCB differential
trace pair mismatch
• Can be caught during PCB EMC rule
checking
– For example, BoardCheck rule requires
differential pair length to match
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Based on TUHH formula
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Example I/O Cable @ 10 Gb/s
•
•
•
•
•
Fundamental Harmonic at 5 GHz
Source = 97 dBuV
Scd21 = -16 dB (from plot for 10% skew/bit-width)
Assume cable shielding 15 dB
CM noise on external cable = 71 dBuV
• Rule-of-thumb limit > 1 GHz = 1 mV (60 dBuV)
• CM over limit by 6 dB!
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Options
• Fix skew on PCB
– May not be possible due to routing constraints
• Improve shielding
– Costly?
• Add filter before I/O connector
– Discrete filters expensive and may distort
intentional signal
– Use Electromagnetic Band gap (EBG) filter?
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EBG Filter Larger Bandwidth Design
Three EBG are designed to resonate around the central
design frequency of 8 GHz
Port 1
Port 3
Port 2
g
g
g
w
w
w
a1
a2
a3
g
g
g
g
f0-df
Port 4
f0
f0+df
fres = fTM10 + 10 %
Courtesy of Prof Orlandi, Univ L’Aquila
fres = fTM10 = 8 GHz
fres = fTM10 - 10 %
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Example EBG Filter Results
(Measure and Simulation Comparison)
Scc21
Grade = 2 , Spread = 2
Sdd21
Courtesy of Prof Orlandi, Univ L’Aquila
Grade = 2 , Spread = 2
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Example EBG Near Field Results
Fullwave Simulation in Microwave Studio with Different
EBG Filter Locations
Traces
Traces
P1
P2
P3
P4
P1
P2
No Radiation
P3
P4
EBG
Traces
Traces
P1
No Radiation
P3
P2
P4
No Radiation
P1
P2
P3
P4
EBG
EBG
Courtesy of Prof Orlandi, Univ L’Aquila
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SI Concerns for CM
• Some devices require CM to be below a
specified amount
– Often given in time domain
– Beware of out-of-band CM
• Sdc21 can convert external common mode
to differential mode noise
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Summary
• Many asymmetries can cause common
mode noise
• When specifying the amount of CM
conversion that is allowable – must include
source amplitude and expected shielding
• While EMC is primary concern, SI
immunity can be a consideration
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