Switched-Capacitor Circuits
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Basic Building Blocks
Opamps
• Ideal opamps usually assumed.
• Important non-idealities
— dc gain: sets the accuracy of charge transfer,
hence, transfer-function accuracy.
— unity-gain freq, phase margin & slew-rate: sets
the max clocking frequency. A general rule is that
unity-gain freq should be 5 times (or more) higher
than the clock-freq.
— dc offset: Can create dc offset at output. Circuit
techniques to combat this which also reduce 1/f
noise.
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Basic Building Blocks
Double-Poly Capacitors
C1
metal
metal
poly1
C p1
thin oxide
C p2
poly2
C1
bottom plate
thick oxide
C p1
C p2
(substrate - ac ground)
equivalent circuit
cross-section view
• Substantial parasitics with large bottom plate
capacitance (20 percent of C 1 )
• Also, metal-metal capacitors are used but have even
larger parasitic capacitances.
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Basic Building Blocks
Switches
φ
φ
Symbol
n-channel
v1
v1
v1
v2
φ
φ
φ
p-channel
v2
transmission
gate
v2
v1
v2
φ
• Mosfet switches are good switches.
— off-resistance near GΩ range
— on-resistance in 100Ω to 5kΩ range (depends on
transistor sizing)
• However, have non-linear parasitic capacitances.
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Basic Building Blocks
Non-Overlapping Clocks
V on
V off
V on
V off
φ1
T
n–2 n–1
φ
n
n+1
t⁄T
φ2
n – 3 ⁄ 2n – 1 ⁄ 2 n + 1 ⁄ 2
φ1
1
f s ≡ --T
delay
delay
φ2
t⁄T
• Non-overlapping clocks — both clocks are never on
at same time
• Needed to ensure charge is not inadvertently lost.
• Integer values occur at end of φ 1 .
• End of φ 2 is 1/2 off integer value.
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Switched-Capacitor Resistor Equivalent
φ1
V1
φ2
C1
V1
V2
∆Q = C 1 ( V 1 – V 2 ) every clock period
Qx = Cx Vx
R eq
V2
T
R eq = -----C1
(1)
• C 1 charged to V 1 and then V 2 during each clk period.
∆Q 1 = C 1 ( V 1 – V 2 )
(2)
• Find equivalent average current
C1 ( V1 – V2 )
I avg = ----------------------------T
(3)
where T is the clk period.
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Switched-Capacitor Resistor Equivalent
• For equivalent resistor circuit
V1 – V2
I eq = ----------------R eq
(4)
• Equating two, we have
T
1
R eq = ----- = ---------C1
C1 fs
(5)
• This equivalence is useful when looking at low-freq
portion of a SC-circuit.
• For higher frequencies, discrete-time analysis is
used.
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Resistor Equivalence Example
• What is the equivalent resistance of a 5pF
capacitance sampled at a clock frequency of 100kHz .
• Using (5), we have
1
R eq = -------------------------------------------------------- = 2MΩ
– 12
3
( 5 × 10 ) ( 100 × 10 )
• Note that a very large equivalent resistance of 2MΩ
can be realized.
• Requires only 2 transistors, a clock and a relatively
small capacitance.
• In a typical CMOS process, such a large resistor
would normally require a huge amount of silicon
area.
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Parasitic-Sensitive Integrator
v c2(nT)
φ1
v ci(t)
v cx(t)
v c1(t)
φ2
C2
v co(t)
φ1
C1
v o(n) = v co(nT)
v i(n) = v ci(nT)
• Start by looking at an integrator which IS affected by
parasitic capacitances
• Want to find output voltage at end of φ 1 in relation to
input sampled at end of φ 1 .
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Parasitic-Sensitive Integrator
C2
C2
v ci(nT – T)
v ci(nT – T ⁄ 2)
C1
v co(nT – T)
φ 1 on
C1
v co(nT – T ⁄ 2)
φ 2 on
• At end of φ 2
C 2 v co(nT – T ⁄ 2) = C 2 v co(nT – T) – C 1 v ci(nT – T)
(6)
• But would like to know the output at end of φ 1
C 2 v co(nT) = C 2 v co(nT – T ⁄ 2)
(7)
C 2 v co(nT) = C 2 v co(nT – T) – C 1 v ci(nT – T)
(8)
• leading to
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Parasitic-Sensitive Integrator
• Modify above to write
C1
v o(n) = v o(n – 1) – ------ v i(n – 1)
C
(9)
2
and taking z-transform and re-arranging, leads to
V o(z)
 C 1 1
H(z) ≡ ------------ = –  ------ ----------V i(z)
 C 2 z – 1
(10)
• Note that gain-coefficient is determined by a ratio of
two capacitance values.
• Ratios of capacitors can be set VERY accurately on
an integrated circuit (within 0.1 percent)
• Leads to very accurate transfer-functions.
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Typical Waveforms
φ1
t
φ2
t
v ci(t)
t
v cx(t)
t
v co(t)
t
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Low Frequency Behavior
• Equation (10) can be re-written as
 C 1
z –1 / 2
H(z) = –  ------ --------------------------- C 2 z 1 / 2 – z – 1 / 2
(11)
• To find freq response, recall
z = e jωT = cos ( ωT ) + j sin ( ωT )
ωT
ωT
z 1 / 2 = cos  ------- + j sin  -------
 2
 2
ωT
ωT
z – 1 / 2 = cos  ------- – j sin  -------
 2
 2
ωT
ωT
cos  ------- – j sin  -------
 2
 2
 C 1
jωT
H(e ) = –  ------ --------------------------------------------------ωT
 C 2
j2 sin  -------
 2
(12)
(13)
(14)
(15)
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Low Frequency Behavior
• Above is exact but when ωT « 1 (i.e., at low freq)
H(e
jωT
 C 1 1
) ≅ –  ------ -------- C 2 jωT
(16)
• Thus, the transfer function is same as a continuoustime integrator having a gain constant of
C1 1
K I ≅ ------ --C2 T
(17)
which is a function of the integrator capacitor ratio
and clock frequency only.
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Parasitic Capacitance Effects
C p3
φ1
C p4
C2
φ2
φ1
v i(n)
v o(n)
C1
C p1
C p2
• Accounting for parasitic capacitances, we have
 C 1 + C p1 1
H(z) = –  ---------------------- ---------- C2  z – 1
(18)
• Thus, gain coefficient is not well controlled and
partially non-linear (due to C p1 being non-linear).
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Parasitic-Insensitive Integrators
C2
φ1
C1
φ2
v ci(t)
v co(t)
φ2
v i(n) = v ci(nT)
φ1
φ1
v o(n) = v co(nT)
• By using 2 extra switches, integrator can be made
insensitive to parasitic capacitances
— more accurate transfer-functions
— better linearity (since non-linear capacitances
unimportant)
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Parasitic-Insensitive Integrators
C2
C2
v ci(nT – T ⁄ 2)
v ci(nT – T)
+
-
-
C1
v co(nT – T)
+
φ 1 on
C1
v co(nT – T ⁄ 2)
φ 2 on
• Same analysis as before except that C 1 is switched
in polarity before discharging into C 2 .
V o(z)
 C 1 1
H(z) ≡ ------------ =  ------ ----------V i(z)
 C 2 z – 1
(19)
• A positive integrator (rather than negative as before)
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Parasitic-Insensitive Integrators
C p3
φ1
v i(n)
C1
φ2
φ2
φ1
C p1
C p4
C2
φ1
v o(n)
C p2
• C p3 has little effect since it is connected to virtual gnd
• C p4 has little effect since it is driven by output
• C p2 has little effect since it is either connected to
virtual gnd or physical gnd.
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Parasitic-Insensitive Integrators
• C p1 is continuously being charged to v i(n) and
discharged to ground.
• φ 1 on — the fact that C p1 is also charged to v i(n – 1)
does not affect C 1 charge.
• φ 2 on — C p1 is discharged through the φ 2 switch
attached to its node and does not affect the charge
accumulating on C 2 .
• While the parasitic capacitances may slow down
settling time behavior, they do not affect the
discrete-time difference equation
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Parasitic-Insensitive Inverting Integrator
φ1
C1
φ1
C2
v i(n)
V i(z)
φ2
φ2
φ1
v o(n)
V o(z)
C 2 v co(nT – T ⁄ 2) = C 2 v co(nT – T)
C 2 v co(nT) = C 2 v co(nT – T ⁄ 2) – C 1 v ci(nT)
(20)
(21)
• Present output depends on present input(delay-free)
V o(z)
 C 1 z
H(z) ≡ ------------ = –  ------ ----------V i(z)
 C 2 z – 1
(22)
• Delay-free integrator has negative gain while
delaying integrator has positive gain.
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Signal-Flow-Graph Analysis
C1
V 1(z)
V 2(z)
φ1
φ2
φ2
φ1
V 3(z)
C2
φ1
C3
V o(z)
φ1
φ2
V 1(z)
CA
φ1
φ2
–C1 ( 1 – z –1 )
V 2(z)
V 3(z)
C2 z –1
1
1- -------------- ----- C A 1 – z –1
V o(z)
–C3
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First-Order Filter
V in(s)
V out(s)
• Start with an active-RC structure and replace
resistors with SC equivalents.
• Analyze using discrete-time analysis.
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First-Order Filter
φ1
C2
φ2
φ1
φ2
φ1
φ1
C3
φ2
φ2
CA
φ1
C1
V i(z)
V o(z)
–C3
V i(z)
–C2
1 1
 ------ --------------- C A 1 – z – 1
V o(z)
–C1 ( 1 – z –1 )
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First-Order Filter
C A ( 1 – z – 1 )V o(z) = – C 3 V o(z) – C 2 V i(z) – C 1 ( 1 – z – 1 )V i(z) (23)
 C1
 C2
–
1
-----1
z
+
(
–
)
 
 -------
 C A
 C A
– -----------------------------------------------------V o(z)
C
H(z) ≡ ------------ =
1 – z – 1 + ------3V i(z)
CA
(24)
C1
 C 1 + C 2
 ------------------- z – ------CA
 CA 
= – ----------------------------------------C3

 1 + ------- z – 1
C A

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First-Order Filter
• The pole of (24) is found by equating the
denominator to zero
CA
z p = ------------------CA + C3
(25)
• For positive capacitance values, this pole is
restricted to the real axis between 0 and 1
— circuit is always stable.
• The zero of (24) is found to be given by
C1
z z = -----------------C1 + C2
(26)
• Also restricted to real axis between 0 and 1.
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First-Order Filter
The dc gain is found by setting z = 1 which results in
–C
H(1) = ---------2
C3
(27)
• Note that in a fully-differential implementation,
effective negative capacitances for C 1 , C 2 and C 3 can
be achieved by simply interchanging the input wires.
• In this way, a zero at z = – 1 could be realized by
setting
C 1 = – 0.5C 2
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First-Order Example
• Find the capacitance values needed for a first-order
SC-circuit such that its 3dB point is at 10kHz when a
clock frequency of 100kHz is used.
• It is also desired that the filter have zero gain at
50kHz (i.e. z = – 1 ) and the dc gain be unity.
• Assume C A = 10pF .
Solution
• Making use of the bilinear transform
p = ( z – 1 ) ⁄ ( z + 1 ) the zero at – 1 is mapped to
Ω = ∞.
• The frequency warping maps the -3dB frequency of
10kHz (or 0.2π rad/sample ) to
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First-Order Example
0.2π
Ω = tan  ----------- = 0.3249
 2 
(29)
• in the continuous-time domain leading to the
continuous-time pole, p p , required being
p p = – 0.3249
(30)
• This pole is mapped back to z p given by
1+p
z p = --------------p- = 0.5095
1 – pp
(31)
• Therefore, H(z) is given by
k(z + 1)
H(z) = -----------------------z – 0.5095
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First-Order Example
• where k is determined by setting the dc gain to one
(i.e. H(1) = 1 ) resulting
0.24525 ( z + 1 )
H(z) = -----------------------------------z – 0.5095
(33)
• or equivalently,
0.4814z + 0.4814
H(z) = -----------------------------------------1.9627z – 1
(34)
• Equating these coefficients with those of (24) (and
assuming C A = 10pF ) results in
C 1 = 4.814pF
(35)
(36)
(37)
C 2 = – 9.628 pF
C 3 = 9.628pF
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Switch Sharing
C3
φ2
C1
φ1
C2
φ1
CA
φ1
)
φ2
V o(z)
φ2
• Share switches that are always connected to the
same potentials.
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Fully-Differential Filters
• Most modern SC filters are fully-differential
• Difference between two voltages represents signal
(also balanced around a common-mode voltage).
• Common-mode noise is rejected.
• Even order distortion terms cancel
2
v1
nonlinear
element
–v1
nonlinear
element
3
4
v p1 = k 1 v 1 + k 2 v 1 + k 3 v 1 + k 4 v 1 + …
3
5
v diff = 2k 1 v 1 + 2k 3 v 1 + 2k 5 v 1 + …
+
-
2
3
4
v n1 = – k 1 v 1 + k 2 v 1 – k 3 v 1 + k 4 v 1 + …
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Fully-Differential Filters
C1
C3
φ2
+
V i(z)
-
φ1
φ1
CA φ2
φ2
C2
φ1
+
V (z)
- o
φ1
C2
φ2
φ1
CA φ
φ2
C3
2
φ1
C1
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Fully-Differential Filters
• Negative continuous-time input
— equivalent to a negative C 1
C1
φ2
+
V i(z)
-
φ1
φ1
C3
CA φ2
φ2
C2
φ1
+
V (z)
- o
φ1
C2
φ2
φ1
CA φ
φ2
C3
2
φ1
C1
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Fully-Differential Filters
• Note that fully-differential version is essentially two
copies of single-ended version, however ... area
penalty not twice.
• Only one opamp needed (though common-mode
circuit also needed)
• Input and output signal swings have been doubled
so that same dynamic range can be achieved with
half capacitor sizes (from kT ⁄ C analysis)
• Switches can be reduced in size since small caps
used.
• However, there is more wiring in fully-differ version
but better noise and distortion performance.
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Low-Q Biquad Filter
2
V out(s)
k2 s + k1 s + ko
H a(s) ≡ ----------------- = – --------------------------------------V in(s)
ωo
2
2
s +  ------ s + ω o
 Q
(38)
1 ⁄ ωo
Q ⁄ ωo
C A = 1 V c1(s)
CB = 1
ωo ⁄ ko
–1 ⁄ ωo
V in(s)
1 ⁄ k1
V out(s)
k2
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Low-Q Biquad Filter
φ1 K C φ1
4 1
φ2
V 1(z)
φ1 K C φ2
5 2
φ1 K C φ1
1 1
φ2
φ1 K C φ1
6 2
φ2
C1
V i(z)
φ2
φ2
φ2
φ1
φ2
C2
V o(z)
φ1
φ1 K C φ1
2 2
φ2
φ2
K3 C2
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Low-Q Biquad Filter
–K4
–K6
V 1(z)
V i(z)
–K1
1
---------------1 – z –1
K 5 z –1
1
---------------1 – z –1
V o(z)
–K2
–K3 ( 1 – z –1 )
2
V o(z)
( K 2 + K 3 )z + ( K 1 K 5 – K 2 – 2K 3 )z + K 3
H(z) ≡ ------------ = – -------------------------------------------------------------------------------------------------2
V i(z)
( 1 + K 6 )z + ( K 4 K 5 – K 6 – 2 )z + 1
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Low-Q Biquad Filter Design
2
a2 z + a1 z + a0
H(z) = – ------------------------------------2
b2 z + b1 z + 1
(40)
• we can equate the individual coefficients of “z” in
(39) and (40), resulting in:
K3 = a0
K2 = a2 – a0
(41)
(42)
(43)
(44)
(45)
K1 K5 = a0 + a1 + a2
K6 = b2 – 1
K4 K5 = b1 + b2 + 1
• A degree of freedom is available here in setting
internal V 1(z) output
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Low-Q Biquad Filter Design
• Can do proper dynamic range scaling
• Or let the time-constants of 2 integrators be equal by
K4 = K5 =
b1 + b2 + 1
(46)
Low-Q Biquad Capacitance Ratio
• Comparing resistor circuit to SC circuit, we have
K4 ≈ K5 ≈ ωo T
(47)
ωo T
K 6 ≈ ---------Q
(48)
• However, the sampling-rate, 1 ⁄ T , is typically much
larger that the approximated pole-frequency, ω o ,
ωo T « 1
(49)
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Low-Q Biquad Capacitance Ratio
• Thus, the largest capacitors determining pole
positions are the integrating capacitors, C 1 and C 2 .
• If Q < 1 , the smallest capacitors are K 4 C 1 and K 5 C 2
resulting in an approximate capacitance spread of
1 ⁄ ( ωo T ) .
• If Q > 1 , then from (48) the smallest capacitor would
be K 6 C 2 resulting in an approximate capacitance
spread of Q ⁄ ( ω o T ) — can be quite large for Q » 1
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High-Q Biquad Filter
• Use a high-Q biquad filter circuit when Q » 1
• Q-damping done with a cap around both integrators
• Active-RC prototype filter
1 ⁄ ωo
1⁄Q
C1 = 1
ωo ⁄ ko
V in(s)
–1 ⁄ ωo
C2 = 1
V out(s)
k1 ⁄ ωo
k2
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High-Q Biquad Filter
φ1 K C φ1
4 1
φ2
C1
V i(z)
φ1 K C φ1
1 1
φ2
φ2
K6 C1
V 1(z)
φ1 K C φ2
5 2
φ2
φ2
φ1
C2
V o(z)
φ1
K2 C1
K3 C2
• Q-damping now performed by K 6 C 1
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High-Q Biquad Filter
• Input K 1 C 1 : major path for lowpass
• Input K 2 C 1 : major path for band-pass filters
• Input K 3 C 2 : major path for high-pass filters
• General transfer-function is:
2
V o(z)
K 3 z + ( K 1 K 5 + K 2 K 5 – 2K 3 )z + ( K 3 – K 2 K 5 )
H(z) ≡ ------------ = – ---------------------------------------------------------------------------------------------------------------- (50)
2
V i(z)
z + ( K 4 K 5 + K 5 K 6 – 2 )z + ( 1 – K 5 K 6 )
• If matched to the following general form
2
a2 z + a1 z + a0
H(z) = – ------------------------------------2
z + b1 z + b0
(51)
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High-Q Biquad Filter
K1 K5 = a0 + a1 + a2
K2 K5 = a2 – a0
(52)
K3 = a2
K4 K5 = 1 + b0 + b1
(54)
K5 K6 = 1 – b0
(56)
(53)
(55)
• And, as in lowpass case, can set
K4 = K5 =
1 + b0 + b1
(57)
• As before, K 4 and K 5 approx ω o T « 1 but K 6 ≅ 1 ⁄ Q
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Charge Injection
• To reduce charge injection (thereby improving
distortion) , turn off certain switches first.
φ1
C3
Q5
C1
φ1
V i(z)
C2
Q1
φ2
Q 2Q 3
φ 1a
Q6
φ2
CA
Q4
φ 2a
V o(z)
φ1
• Advance φ 1a and φ 2a so that only their charge
injection affect circuit (result is a dc offset)
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Charge Injection
• Note: φ 2a connected to ground while φ 1a connected
to virtual ground, therefore ...
— can use single n-channel transistors
— charge injection NOT signal dependent
Q CH = – W LC ox V eff = – W LC ox ( V GS – V t )
(58)
• Charge related to V GS and V t and V t related to
substrate-source voltage.
• Source of Q 3 and Q 4 remains at 0 volts — amount of
charge injected by Q 3, Q 4 is not signal dependent
and can be considered as a dc offset.
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Charge Injection Example
• Estimate dc offset due to channel-charge injection
when C 1 = 0 and C 2 = C A = 10C 3 = 10pF .
• Assume switches Q 3, Q 4 have V tn = 0.8V , W = 30µm ,
L = 0.8µm , C ox = 1.9 × 10
supplies are ± 2.5V .
–3
2
pF ⁄ µm , and power
• Channel-charge of Q 3, Q 4 (when on) is
Q CH3 = Q CH4 = – ( 30 ) ( 0.8 ) ( 0.0019 ) ( 2.5 – 0.8 )
= – 77.5 × 10
–3
(59)
pC
• dc feedback keeps virtual opamp input at zero volts.
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Charge Injection Example
• Charge transfer into C 3 given by
Q C = – C 3 v out
3
(60)
• We estimate half channel-charges of Q 3 , Q 4 are
injected to the virtual ground leading to
1
--- ( Q CH3 + Q CH4 ) = Q C
3
2
(61)
which leads to
–3
77.5 × 10 pC
v out = ------------------------------------- = 78 mV
1pF
(62)
• dc offset affected by the capacitor sizes, switch sizes
and power supply voltage.
University of Toronto
48 of 48
© D. Johns, K. Martin, 1997