EE 367 – Logic Design
Lecture #2
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Agenda
1. Logic Design Tools
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Announcements (Friday, 1/18)
1. No Class Monday (1/21), MLK Holiday
EE 367 – Logic Design
Spring 2008
Lecture #2
Page 1
Logic Design Tools
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MS Visio
- a generic drawing program.
- industry is converging on this program for documentation.
- has built in shape libraries, including analog/digital logic.
- we’ll use it for this class to create clean schematics.
EE 367 – Logic Design
Spring 2008
Lecture #2
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Logic Design Tools
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MS Visio
Predefined
Shapes
EE 367 – Logic Design
Spring 2008
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Logic Design Tools
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ModelSim (by Mentor Graphics)
- an HDL Simulation (VHDL and Verilog)
- widely used in industry
- has color-coded text editing for keywords
- has console for verification reporting
- we’ll use for homework & before FPGA synthesis.
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Spring 2008
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Logic Design Tools
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ModelSim
Simulation Waveform
Project
Navigator
Console
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Spring 2008
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Logic Design Tools
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ModelSim
Text Editor
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Spring 2008
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Logic Design Tools
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Xilinx ISE
- Integrated Software Environment (ISE)
- Implementation tool
- compile / simulate
- synthesis
- technology mapping
- place and route
- back annotation for post-route simulation and timing verification
- can do similar simulation as in ModelSim
- this is where we :
- select FPGA to target
- assign signal pins
- set timing constraints
- set placement constraints
- set routing constraints
- generate programming file
- download file to FPGA, EEprom, or CPLD using the JTAG interface.
EE 367 – Logic Design
Spring 2008
Lecture #2
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Logic Design Tools
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Xilinx ISE
Sources
Window
Edit/View
Window
Processes
Window
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Spring 2008
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Logic Design Tools
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Xilinx ISE
Resource
Usage
Package
View
Pin
Assignments
EE 367 – Logic Design
Spring 2008
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Logic Design Tools
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Xilinx ISE
Routing
Editor
HDL or
Schematic
Entry
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Lecture #2
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