2288
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002
Direct-Tunneling Gate Leakage Current in
Double-Gate and Ultrathin Body MOSFETs
Leland Chang, Student Member, IEEE, Kevin J. Yang, Member, IEEE, Yee-Chia Yeo, Member, IEEE,
Igor Polishchuk, Member, IEEE, Tsu-Jae King, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE
Abstract—The impact of energy quantization on gate tunneling
current is studied for double-gate and ultrathin body MOSFETs.
Reduced vertical electric field and quantum confinement in the
channel of these thin-body devices causes a decrease in gate
leakage by as much as an order of magnitude. The effects of
body thickness scaling and channel crystallographic orientation
are studied. The impact of threshold voltage control solutions,
including doped channel and asymmetric double-gate structures
is also investigated. Future gate dielectric thickness scaling and
the use of high- gate dielectrics are discussed.
Index Terms—Direct tunneling, double-gate MOSFET, energy
quantization, gate leakage current, high- dielectrics, threshold
voltage control, ultrathin body MOSFET, wavefunction penetration.
I. INTRODUCTION
A
S BULK MOSFETs are scaled to below 50 nm in gate
length, traditional methods of scaling begin to approach
physical fundamental limitations [1]. Continued scaling may
require the adoption of novel device structures [2] such as
the double-gate (DG) or ultrathin body (UTB) MOSFET [3]
(Fig. 1). Such devices rely on the thickness of the silicon
channel to control short-channel effects by eliminating any
leakage paths far from the gate electrode. This may relax
requirements on gate oxide thickness scaling, shallow junction
formation, and channel engineering, thus allowing for gate
length scaling beyond the limitations of the standard bulk
MOSFET design. Based on estimates of off-state drain leakage
current, these advanced device structures could be scalable
down to an ultimate limit of 10 nm in gate length [4]. While
continued gate length scaling may be the primary benefit of
thin-body device structures, additional advantages may be
apparent.
Manuscript received March 12, 2002; revised November 1, 2002. This
work was supported by the MARCO Focused Research Center on Materials,
Structures, and Devices, via the Massachusetts Institute of Technology, in
part by MARCO under Contract 2001-MT-887, and DARPA under Grant
MDA972-01-1-0035. The review of this paper was arranged by Editor C.-Y. Lu.
L. Chang, K. J. Yang, T.-J. King, and C. Hu are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley,
CA 94720 USA (e-mail: leland@eecs.berkeley.edu).
K. J. Yang was with the Department of Electrical Engineering and Computer
Sciences, University of California, Berkeley, CA 94720 USA. He is now with
T-RAM, Inc., San Jose, CA 95134 USA (e-mail: leland@eecs.berkeley.edu).
Y.-C. Yeo was with the Department of Electrical Engineering and Computer
Sciences, University of California, Berkeley, CA 94720 USA. He is now with
Taiwan Semiconductor Manufacturing Corporation, Hsinchu, Taiwan. R.O.C.
I. Polishchuk was with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA. He is now
with Cypress Semiconductor Corporation, San Jose, CA 95134 USA.
Digital Object Identifier 10.1109/TED.2002.807446
Fig. 1. (a) Bulk, (b) double-gate (DG), and (c) ultrathin-body (UTB) MOSFET
structure cross-sections and energy band diagrams. The bulk substrate doping
is 4 10 cm . The channel is assumed to be undoped for DG and UTB
devices. A broader inversion charge distribution and reduced electric field away
from the dielectric interface reduces gate leakage current.
2
In double-gate and ultrathin body devices, control of short
channel effects and threshold voltage is ideally achieved without
the use of channel dopants. This eliminates statistical dopant
fluctuation concerns and minimizes impurity scattering. In addition, depletion charge cannot exist because there are no impurities in the channel. From [5], the average vertical electric field
in the channel inversion layer is
where
and
are the inversion and depletion charge
is the dielectric constant for silicon, and is an
densities,
, carexperimentally derived fitting parameter. Since
riers in the inversion layer thus encounter a smaller average vertical electric field in thin-body devices than in standard bulk de-
0018-9383/02$17.00 © 2002 IEEE
CHANG et al.: DIRECT-TUNNELING GATE LEAKAGE CURRENT
Fig. 2. For DG and UTB, carriers are confined by a square well for a gate
biases V below V . Above V , a triangular well forms.
vices with heavy channel doping. This can be seen in Fig. 1, in
which the slope of the potential in the silicon channel is dramatically reduced, particularly at points further away from the
silicon/dielectric interface. This reduction in vertical field is expected to improve carrier mobility, especially as gate dielectric
thicknesses are scaled and surface scattering mechanisms become dominant. Additional benefits may be apparent in gate
tunneling current [6] and device reliability.
In this work, the impact of this reduced vertical field on gate
tunneling current is studied for thin-body SOI MOSFETs. The
effect of energy quantization due to carrier confinement in the
thin body of these devices is first examined using a coupled
Schrödinger–Poisson solver [7], [8]. Reduction of the effective
directly results in a lowering of
vertical electric field
due to reduced carrier confinethe ground state energy
ment. These effects are applied to explain the reduction of direct-tunneling gate leakage current in thin-body devices. The
impacts of body thickness, channel crystallographic orientation,
channel doping concentration, asymmetric dual-gate work functions, and gate dielectric material are then investigated. Results
for NMOS devices at room temperature are presented. Gate current in PMOS devices will be different due primarily to changes
in the carrier effective mass and tunneling barrier height; however, a similar decrease in the gate tunneling current is expected
in thin-body PMOSFETs as the vertical electric field should
similarly be reduced.
II. IMPACT OF ENERGY QUANTIZATION
The behavior of the ground state energy at low and high gate
bias (referenced to the quasi-Fermi level of the conduction band
in the source and drain [9]) is depicted in Figs. 2 and 3. Below
threshold, band bending is negligible, and the structure can be
approximated as a square well. As expected, the ground state
energy increases as the body is thinned due to increased confinement from the smaller width potential well. This effectively
increases the device threshold voltage [10] as carriers must now
populate a higher energy subband. In strong inversion, however,
the inversion charge induces a semi-triangular potential well.
As the body is initially thinned, the confining electric field and
the depth of the potential well are reduced (Fig. 2) as the in-
2289
Fig. 3. Below threshold, thinning T
reduces the width of the square
potential well, which further confines carriers and raises the eigenenergies. In
inversion, the triangular well becomes shallower, thus pushing the energies
downward. This effect is more significant in the DG case due to merging of the
two inversion layers. Energies are referenced to the quasi-Fermi level of the
conduction band in the source and drain.
version charge becomes distributed throughout the entire body
thickness. Because the resultant potential well decreases carrier
confinement, the energies of the eigenstates in the well are lowered. This effect is more pronounced in the double-gate case
because merging of the two inversion layers more dramatically
decreases the depth of the potential well. When the body thickness becomes very small (below 3 nm), the depth of the potential well drops below the ground state energy of the four-fold
valley. This subband is no longer bound by the semi-triangular
well created by the inversion layer and is instead confined by
the square well determined by the body thickness. Thus, the
four-fold valley ground state energy reaches a minimum and begins to increase with additional body thickness reduction, further splitting the twofold and four-fold valleys.
In finding the self-consistent Schrödinger–Poisson solution
to the potential profile, an approximate boundary condition
that is commonly used is that the electron wavefunction
falls to zero at the silicon–dielectric interface. Inclusion of
wavefunction penetration into the gate dielectric, however, can
lower the eigenenergies because carriers are no longer perfectly
contained inside the potential well. The eigenenergy difference
obtained with and without consideration of wavefunction
penetration can amount to as much as 10–20 mV (Fig. 4). This
difference increases with gate bias as the subband energies
move closer to the conduction band edge in the dielectric,
thus pushing more of the wavefunction into the insulator.
The amount of wavefunction penetration is influenced by the
silicon–dielectric barrier height and carrier effective mass in
the dielectric. Reduction of the barrier height allows for more
of the electron wavefunction to exist in the dielectric region,
which further depresses the eigenenergies. However, due to the
imposed boundary conditions at the interface (continuity of the
wavefunction, , and the slope of wavefunction divided by the
), less wavefunction penetration is observed when
mass,
the effective mass in the dielectric is lowered. These boundary
conditions follow directly from the well-known form of the
kinetic energy operator [11]. Thus, the actual eigenenergies
are dependent upon the choice of the gate dielectric material
(Fig. 5), which determines both the barrier height and effective
mass.
2290
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002
Fig. 4. Electron wavefunction penetration into the gate dielectric is important
as it reduces carrier confinement and lowers the eigenenergies. The difference
in energy between cases with and without consideration of wavefunction
penetration grows as gate bias is increased.
Fig. 6. Gate current in an ultrathin body device can be reduced by up to 3
compared with the standard bulk structure.
2 as
carrier eigenenergies,
. The imaginary part of
the eigenenergy, , is related to the lifetime of the quasibound
state by Planck’s constant
This can then be translated to gate tunneling current
Fig. 5. Inclusion of wavefunction penetration into the gate dielectric pushes
the eigenenergies downward because of broadening of the wavefunction profile.
Due to a difference in barrier height and effective mass, changing the dielectric
material can change the magnitude of this effect. Material parameters used are
taken from [21] and [22] and adjusted slightly for SiO to match experimental
data [13]: m
= 0:42, = 3:1 eV, m
= 0:50, =
2:1 eV, and m
= 0:11, = 1:5 eV.
III. REDUCED GATE TUNNELING CURRENT
Previous experimental results have shown that the gate
leakage current in SOI devices is affected by the electric
field distribution in the body [12]. Gate current was observed
to decrease when a large positive voltage was applied to
the substrate—essentially biasing the backside of the SOI
in inversion and reducing the vertical electric field in the
channel. Using potential profiles from a Schrödinger–Poisson
solver [7], [8], the transverse resonance method [13], [14]
was used to investigate the physical mechanisms for this same
effect in double-gate and ultrathin body devices. By using a
transmission line analogy, matching of the impedances seen
by a carrier in the potential well yields complex values of the
where
is the carrier population in the quasibound state.
Summation of the current components over each carrier
subband and valley yields the total gate current. Because this
method considers the entire domain of the device structure,
wavefunction penetration into the gate dielectric is allowed.
The Schrödinger–Poisson solvers used to generate the potential profile used in calculation of the gate tunneling current,
however, do not consider this effect. Nevertheless, this inconsistency is expected to have but a minor impact on the potential
distribution [15] as it is only a small perturbation, thereby
upholding the validity of this method.
In double-gate and ultrathin body MOSFETs, gate current can
be suppressed due to the reduced vertical electric field. In particular, the electric field near the bottom of the inversion layer
is dramatically reduced, as can be seen in Fig. 1. This reduces
the depth of the potential well, which lowers the bound state
energy and broadens the inversion charge distribution, thus resulting in a lower tunneling probability and an increased lifetime
of each quasibound state. This effectively reduces the both the
tunneling probability and the impingement frequency at which
electrons are directed toward the silicon–dielectric interface.
Depending on device dimensions, gate current in an ultrathin
body MOSFET can be reduced by up to 3 when compared
with that of a bulk device at a constant inversion charge density
(Fig. 6). Gate current in a double-gate MOSFET can be reduced
by up to 4 (Fig. 7). Results for a constant inversion charge
density are summarized in Fig. 8. The improvement is enhanced
in the double-gate device because the inherent symmetry of the
two gate electrodes further decreases the effective vertical electric field. In both thin-body device structures, the improvement
CHANG et al.: DIRECT-TUNNELING GATE LEAKAGE CURRENT
2291
2
Fig. 7. Gate current in a double-gate device can be reduced by up to 4 as
compared with the standard bulk structure. Gate current and inversion charge
density are divided by a factor of two in the double-gate device to account for
both conducting channels.
Q
Fig. 9. By artificially shifting the bulk curve from Figs. 6 and 7 by
, the
impact of the reduced electric field is, to the first order, removed. This shifted
bulk curve closely approximates the gate tunneling current for a UTB device.
For a DG device, however, an additional decrease in gate current is observed.
This is due to the symmetric nature of the device structure, which flattens the
,
bottom of the potential well, thus reducing quantum confinement. At low
the curves intersect, which is likely an artifact of the horizontal shift applied to
the bulk curve.
Q
Fig. 8. The factor by which gate current is reduced for DG and UTB devices
decreases when the dielectric is thinned. Values are taken at a constant inversion
charge density (2 10 cm ).
2
is less pronounced at thinner physical dielectric thicknesses because the quasibound state lifetime is more strongly affected by
thin dielectric barrier than the shape of the potential well. Using
an analytical gate current expression derived using the WKB
approximation [16], this phenomenon can be explained by comparing the tunneling current ratio for thin-body and bulk MOSFETs at constant inversion charge density and oxide voltage
drop
-
-
-
where and are lumped constants incorporating experimentally derived values from [16]. This ratio approaches unity as
the dielectric thickness is reduced.
For UTB devices, the reduction in gate tunneling current is
caused primarily by the decreased electric field. Fig. 9 shows
that a bulk curve artificially shifted by the amount of deplecan closely approximate the tunneling curtion charge
rent for the UTB case. A noticeable difference, however, is observed between the artificially shifted bulk curve and the DG
case. This means that simple consideration of the electric field
is not enough to explain the change in gate tunneling current for
double-gate devices. The additional shift is caused by the symmetric nature of the device, which imposes a strict boundary
condition such that no electric field exists in the center of the
silicon body. This flattens out the center of the potential well
[as in Fig. 1(b)]. The change is subtle, but results in a lowering
of all the energy eigenstates in the DG case, especially those
energy levels situated right around the bottom of the well. This
effect is important even when the body thickness is large since
it is the depth of the potential well that is affected.
Initial scaling of the body thickness can somewhat decrease
the gate leakage current because the potential well becomes
shallower, as is seen in the UTB case (Fig. 10). However, excessive scaling increases the gate current because the width of
the potential well is reduced, thus forcing the inversion charge
closer to the gate oxide interface, increasing energy eigenstates
due to carrier confinement, and decreasing carrier lifetime. The
gate current dependence on the body thickness emphasizes the
importance of considering not only the simple concept of the
average vertical electric field, but also the exact bound state energy, which is determined both by this field and by the width of
the potential well (the body thickness). This is because adjustment of the body thickness does not, to the first order, impact
as earlier defined. However, quantum confinement can be
affected, which changes the bound-state energies and, as shown
in Fig. 10, can significantly affect gate leakage current. This effect is enhanced in the double-gate structure due to merging of
the two inversion layers. Below approximately 5 nm in body
thickness, gate current is seen to increase noticeably in both DG
2292
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002
Fig. 10. Dependence of gate current on body thickness for DG and UTB
devices. Excessive thinning of the body (below a body thickness of 5 nm)
increases confinement of carriers toward the gate oxide interface, and the gate
current approaches that of bulk.
Fig. 11. Crystallographic orientation of the thin-body does not dramatically
affect gate tunneling current. Only a minor difference is observed between the
(100), (110), and (111) directions.
and UTB devices. However, this value is close to the practical
limit of body thickness scaling [17], so this effect may not be of
concern in actual device technologies.
Because of difficulties in the fabrication of planar double-gate
MOSFETs with self-aligned gate electrodes, device structures
that lie outside of the standard (100) crystallographic plane have
been proposed. For example, depending on rotation of the device layout on the wafer, the silicon channel in a FinFET [18],
[19] may lie in the (110) plane. A change in the crystalline orientation of the channel alters the carrier effective mass in the
silicon for both tunneling and density of states calculation [20].
Although this affects the inversion charge distribution and centroid, Fig. 11 shows that there should be no significant difference in gate tunneling current between devices oriented in the
(100), (110), and (111) planes, which is in agreement with [21].
IV. IMPACT OF THRESHOLD VOLTAGE CONTROL
Because threshold voltage control by adjustment of the gate
work function remains a challenge, double-gate and ultrathin
body devices may need to depend on channel dopants to
Fig. 12. If channel doping is used to control V , the electric field in the body
is altered. For an NMOSFET, a p-type body raises the electric field due to
formation of a depletion region, thus increasing gate current. An n-type body
can change the potential distribution and reduce the gate current at very high
doping concentrations.
achieve appropriate values of the device threshold voltage
[4]. Depending on the doping concentration, the electric field
distribution in the body can be affected as a significant amount
of depletion charge can be formed when the channel doping
is large. This, in turn, impacts the gate current (Fig. 12). With
a p-type body (as needed to raise the threshold voltage for an
NMOS device with an N poly-silicon gate), a nonnegligible
depletion region forms beyond 10 cm , thus raising the
electric field and increasing gate current. This threshold doping
level is increased with a smaller body thickness because there
is physically less space available to form a depletion region. It
should be noted, however, that a higher doping concentration
is necessary for small body thicknesses in order to achieve
the appropriate threshold voltage. An n-type body (as needed
to lower the threshold voltage for an NMOS device with a
mid-gap work function gate), however, can reduce the gate
current when the doping concentration is extremely high. This
occurs because the depth of the potential well is reduced, thus
reducing the effective vertical electric field.
An alternate method of controlling the threshold voltage in
double-gate MOSFETs is to use the asymmetric double-gate
structure, in which the two gates are of different work functions
(e.g., N and P poly-silicon) [4]. By choosing the dielectric
and body thicknesses, the threshold voltage can be adjusted to
the appropriate value. The difference in the gate work functions,
however, creates a built-in vertical electric field in the channel,
which can increase the gate tunneling current over symmetric
double-gate MOSFETs (Fig. 13). Thus, the advantage of the
double-gate device structure in gate tunneling current will be
diminished if an asymmetric structure is used.
V. GATE DIELECTRIC SCALING
In future technologies, high- materials may be used as the
gate dielectric [2] to allow for an increased physical thickness to
reduce gate tunneling current. Gate leakage in the double-gate
device structure with alternative gate dielectrics was investigated by the use of suitable values for the dielectric constant,
dielectric–silicon barrier height, and effective mass in the dielectric [22], [23] (Fig. 14). The increased physical thickness of
the gate dielectric barrier makes the quasibound state lifetime
CHANG et al.: DIRECT-TUNNELING GATE LEAKAGE CURRENT
Fig. 13. If the asymmetric double-gate structure is used to control V ,
a built-in vertical electric field is created in the body. This additional field
increases the gate tunneling current and can counteract the advantage of the
double-gate structure. Gate current and inversion charge density are divided
by a factor of two in both asymmetric and symmetric double-gate devices to
account for the two conducting channels.
2293
Fig. 15. The reduction in gate current in DG and UTB devices means that
the equivalent oxide thickness (EOT) of the gate dielectric can be thinner than
for a bulk MOSFET. Si N is assumed as the dielectric material for 70 nm
gate-length technologies and below [21].
bulk design (Fig. 15). Assuming that Si N will be the dielectric
of choice for 25–70 nm gate length technologies [22], switching
to a double-gate MOSFET device structure can allow for up to
an additional 0.8 Å reduction in the effective oxide thickness.
This amount remains at approximately 5% of the total equivalent oxide thickness across future device technologies down to
25 nm gate lengths. With the advent of high- dielectrics, this
value will only be enhanced.
VI. SUMMARY
Fig. 14. With the projected shift to alternative gate dielectrics, the gate current
improvement from bulk to double-gate can be larger. The thicker physical
thickness of the dielectric makes the carrier lifetime a stronger function of the
electric field distribution, which is lower in DG and UTB.
more dependent upon the shape of the channel potential well.
Since
a larger physical
will increase this ratio and augment
the improvement in gate current observed in thin-body devices.
With a dielectric such as HfO , the reduction in gate current in
the double-gate structure as compared with a bulk device can
Å. It is thus preexceed an order of magnitude at T
dicted that the advantage of the DG and UTB structures is not
only maintained, but also enhanced as device technology migrates to higher- gate-dielectric materials.
A reduction in gate current means that the gate dielectric can
be more aggressively scaled with double-gate and ultrathin body
devices at a given technology node than would be possible with a
Gate tunneling currents in bulk, double-gate, and ultrathin
body MOSFETs have been compared. Lower gate current for
double-gate and ultrathin body devices is attributed to reduced
vertical electric field and quantum confinement effects. The
amount of improvement is affected by the body thickness,
the crystallographic orientation of the device, and the channel
doping concentration. The asymmetric double-gate structure
introduces an additional vertical electric field component,
which can counteract this effect. With the introduction of
high- dielectrics, the reduction in gate leakage current will be
enhanced. The gate dielectric can thus be more aggressively
scaled in ultrathin body and symmetric double-gate MOSFETs.
ACKNOWLEDGMENT
The authors would like to thank Y.-K. Choi for the experimental data used to validate simulated results.
REFERENCES
[1] P. Packan, “Pushing the limits,” Science, vol. 285, no. 5436, pp.
2079–2081, 1999.
[2] (2000) International Technology Roadmap for Semiconductors. [Online]. Available: http://public.itrs.net.
[3] H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI
MOSFETs at the 25nm channel length generation,” in IEDM Tech. Dig.,
Dec. 1998, pp. 407–410.
[4] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, “Gate-length scaling
and threshold voltage control of double-gate MOSFETs,” in IEDM Tech.
Dig., Dec. 2000, pp. 719–722.
2294
[5] A. G. Sabnis and J. T. Clemens, “Characterization of the electron mobility in the inverted <100> Si surface,” in IEDM Tech. Dig., Dec. 1979,
pp. 18–21.
[6] L. Chang, K. J. Yang, Y.-C. Yeo, Y.-K. Choi, T.-J. King, and C. Hu,
“Reduction of direct-tunneling gate leakage current in double-gate and
ultra-thin body MOSFETs,” in IEDM Tech. Dig., Dec. 2001, pp. 99–102.
[7] Schred 2.0. [Online]. Available: http://nanohub.purdue.edu/.
[8] [Online]. Available: http://www-device.eecs.berkeley.edu/qmcv.html.
[9] Y. Taur, “Analytic solutions of charge and capacitance in symmetric
and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices,
vol. 48, pp. 2861–2869, Dec. 2001.
[10] Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, “Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs,” IEEE
Electron Device Lett., vol. 14, pp. 569–571, Dec. 1993.
[11] D. J. BenDaniel and C. B. Duke, “Space-charge effects on electron tunneling,” Phys. Rev., vol. 152, pp. 683–692, 1966.
[12] L. T. Su, H. Fang, J. E. Chung, and D. A. Antoniadis, “Hot-carrier effects
in fully-depleted SOI nMOSFETs,” in IEDM Tech. Dig., Dec. 1992, pp.
349–352.
[13] A. N. Khondker, M. R. Khan, and A. F. M. Anwar, “Transmission line
analogy of resonance tunneling phenomena: The generalized impedance
concept,” J. Appl. Phys., vol. 63, pp. 5191–5193, 1988.
[14] S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-mechanical modeling of electron tunneling current from the inversion layer of
ultra-thin-oxide nMOSFETs,” IEEE Electron Device Lett., vol. 18, pp.
209–211, May 1997.
[15] H. Iwata, “Fully quantum-mechanical modeling of tunneling current in
ultrathin gate oxide metal–oxide-semiconductor devices,” Jpn. J. Appl.
Phys., vol. 40, pp. 4496–4500, 2001.
[16] K. F. Schuegraf and C. Hu, “Hole injection SiO breakdown model for
very low voltage lifetime extrapolation,” IEEE Trans. Electron Devices,
vol. 41, pp. 761–767, May 1994.
[17] D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo simulation
of a 30 nm dual-gate MOSFET: How short can Si go?,” in IEDM Tech.
Dig., 1992, pp. 553–556.
[18] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo,
E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned
double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, pp. 2320–2325, Dec. 2000.
[19] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski,
E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J.
King, J. Bokor, and C. Hu, “Sub 50 nm P-channel FinFET,” IEEE Trans.
Electron Devices, vol. 48, pp. 880–886, May 2001.
[20] F. Stern, “Self-consistent results for n-type Si inversion layers,” Phys.
Rev. B, vol. 5, pp. 4891–4899, 1972.
[21] H. S. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi, and
H. Iwai, “Study of wafer orientation dependence on performance and
reliability of CMOS with direct-tunneling gate oxide,” in Symp. VLSI
Tech., June 2001, pp. 77–78.
[22] Y. C. Yeo, Q. Lu, W.-C. Lee, T.-J. King, and C. Hu, “Direct tunneling
gate leakage current in transistors with ultrathin silicon nitride gate dielectric,” IEEE Electron Device Lett., vol. 21, pp. 540–542, 2000.
[23] Y. C. Yeo, T.-J. King, and C. Hu, “Direct tunneling gate leakage and
scalability of alternative gate dielectrics,” IEEE Electron Device Lett.,
submitted for publication.
Leland Chang (S’99) received the B.S. (highest
honors) and M.S. degrees in electrical engineering
and computer sciences in 1999 and 2001, respectively, from the University of California, Berkeley,
where he is currently pursuing the Ph.D. degree.
His research interests include the fabrication and
analysis of thin-body SOI MOSFETs, nonvolatile
memory devices, and RF MEMS resonators.
Mr. Chang received the National Defense Science
and Engineering Graduate (NDSEG) Fellowship
from the Department of Defense in 1999 and the
IBM Ph.D. Fellowship in 2002.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002
Kevin J. Yang (S’94–M’03) received the B.S. degree
(with highest honors) in electrical and computer engineering from the University of Illinois at UrbanaChampaign in 1997 and the M.S. and Ph.D. degrees
in electrical engineering and computer sciences from
the University of California, Berkeley, in 2000 and
2002, respectively.
His research interests include characterization and
modeling of MOS devices with alternative gate dielectrics and numerical simulation of carrier confinement effects in thin-body SOI MOSFETs. He is now
with T-RAM, Inc. in San Jose, CA.
Dr. Yang received the National Defense Science and Engineering Graduate
(NDSEG) Fellowship in 1997 and the Semiconductor Research Corporation
(SRC) Graduate Fellowship in 2000.
Yee-Chia Yeo (M’03) received the B.Eng (first class
honors) and M.Eng degrees from the National University of Singapore (NUS), and the M.S. and Ph.D.
degrees from the University of California, Berkeley,
all in electrical engineering.
He had worked on optoelectronic devices at the
British Telecommunications Laboratories, U.K., and
on electronic band structure calculations and strained
quantum well lasers at NUS, Singapore. At Berkeley,
his research involved sub-100 nm MOS transistor design and fabrication, strained channel MOS transistors, alternative gate dielectrics, and process integration of dual-metal gates for
CMOS technology. In 2001–2002, he was with Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, R.O.C., where he led a team of
engineers on strained-channel transistor research and development. He has authored or coauthored more than 35 journal and conference papers in the above
areas, and has written a book chapter on MOS transistor gate oxide reliability
with Chenming Hu.
Dr. Yeo was awarded the 1995 IEE Prize from the Institution of Electrical
Engineers, U.K. In 1996, he received the Lee Kuan Yew Gold Medal and the
Institution of Engineers, Singapore Gold Medal for being the best graduate in
Electrical Engineering at NUS. He is also the recipient of the 1997–2001 NUS
Overseas Graduate Scholarship Award and the 2001 IEEE Electron Device Society Graduate Student Fellowship Award.
Igor Polishchuk (M’03) received his B.S. degree in physics with honors from
the California Institute of Technology, Pasadena, in 1997 and the M.S. and Ph.D.
degrees in electrical engineering from the University of California, Berkeley, in
1999 and 2002, respectively. The topics of his doctoral research included reliability of ultrathin gate oxides and high- dielectrics, metal gate CMOS technology, and carrier transport modeling in MOS devices. he is currently a Senior
Technology Development Engineer at Cypress Semiconductor, San Jose, CA,
responsible for high-performance 90-nm CMOS transistor development.
Dr. Polishchuk has held the California Fellowship in Microelectronics in
1997, and the SRC/NIST Graduate Fellowship from 1999 to 2002. He is a
member of the MRS and Tau Beta Pi.
Tsu-Jae King (S’89–M’91–SM’01) received
the B.S., M.S., and Ph.D. degrees in electrical
engineering from Stanford University. At Stanford
University, her research involved the seminal study
of polycrystalline silicon–germanium films and
their applications in metal–oxide–semiconductor
technologies.
She joined the Xerox Palo Alto Research Center
as a Member of Research Staff in 1992, to research
and develop polycrystalline-silicon thin-film transistor technologies for high-performance flat-panel
display and imaging applications. In August 1996, she joined the faculty of the
University of California at Berkeley, where she is now an Associate Professor
of electrical engineering and computer sciences and the Director of the UC
Berkeley Microfabrication Laboratory. Her research activities are presently
in sub-50 nm Si devices and technology, and thin-film materials and devices
for integrated microsystems and large-area electronics. She has authored or
coauthored over 150 publications and holds six U.S. patents.
CHANG et al.: DIRECT-TUNNELING GATE LEAKAGE CURRENT
Chenming Hu (S’71–M’76–SM’83–F’90) received
the B.S. degree from the National Taiwan University,
Taipei, Taiwan, R.O.C., and the M.S. and Ph.D. degrees in electrical engineering from the University of
California, Berkeley.
He is the CTO of the Taiwan Semiconductor Manufacturing Corporation, on leave from UC Berkeley.
He has authored or coauthored five books and over
700 research papers. He is a member of the editorial
boards of the Journal of Semiconductor Science and
Technology and of the Journal of Microelectronics
Reliability.
Dr. Hu leads the development of the industry standard MOSFET model for
IC simulation, BSIM, and received the 2002 IEEE Solid State Circuits Award
for it. He also received the 1997 IEEE Jack A. Morton Award for contributions to the physics of MOSFET reliability. He is a member of the U.S. National Academy of Engineering, a fellow of the Institute of Physics, and a Life
Honorary Professor of the Chinese Academy of Science. He has received UC
Berkeley’s highest honor for teaching – the Distinguished Teaching Award, the
Monie A. Ferst Award of Sigma Xi, the W. Y. Pan Foundation Award, and
DARPA Most Significant Technological Accomplishment Award for co-developing the FinFET transistor structure.
2295