Overview
■
Why VLSI?
■
Why VLSI?
■ Moore’s Law.
■ The VLSI design process.
– lower parasitics = higher speed;
– lower power;
– physically smaller.
■
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Modern VLSI Design 3e: Chapter 1
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Integration improves the design:
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Integration reduces manufacturing cost:
(almost) no manual assembly.
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VLSI and you
■
Moore’s Law
■
Microprocessors:
– personal computers;
– microcontrollers.
■
DRAM/SRAM.
■ Special-purpose processors.
■ System-on-a-chip: all the above and analog
circuitry on one die.
Revised by SG: December 1, 2002
Modern VLSI Design 3e: Chapter 1
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Gordon Moore: co-founder of Intel.
■ Predicted that number of transistors per chip
would grow exponentially (double every 18
months).
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Moore’s Law plot
■
May be part of larger product design.
■ Major steps:
109
108
# transistors
The VLSI design process
107
–
–
–
–
–
integrated
circuit
invented
106
105
memory
CPU
104
103
102
101
100
1960
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1970
1980
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1990
2000
2010 year
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Revised by SG: December 1, 2002
Modern VLSI Design 3e: Chapter 1
The steps
■
Specification: function, cost, etc.
■ Architecture: large blocks.
■ Logic: gates + registers.
■ Circuits: transistor sizes for speed, power.
■ Layout: determines parasitics.
■ Test vectors for testing.
■ (Application software).
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specification;
architecture;
logic design;
circuit design;
layout.
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Challenges in VLSI design
■
Multiple levels of abstraction: transistors to
CPUs.
■ Multiple and conflicting constraints: low
cost and high performance are often at odds.
■ Short design time: Late products are often
irrelevant.
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Dealing with complexity
■
Divide-and-conquer: limit the number of
components you deal with at any one time.
■ Group several components into larger
components:
–
–
–
–
Hierarchical absraction
■
– components and wires that make it up.
■
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Exterior view of a component = type:
– body;
– pins.
transistors form gates;
gates form functional units;
functional units form processing elements;
etc.
Revised by SG: December 1, 2002
Modern VLSI Design 3e: Chapter 1
Interior view of a component:
a
Each instance is a separate copy of the type:
cout
Add1.a
a Add1(Full
adder)
Add2.a
sum
cin
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Signal abstraction
sum
Analog and time-continuous currents and
voltages become binary and time-discrete;
■ Bits become words;
■ Groups of words (e.g. address & data)
become a transaction (e.g. read action on a
bus).
b
b
cin
cin
Revised by SG: December 1, 2002
Modern VLSI Design 3e: Chapter 1
a Add2(Full
adder)
sum
■
Each instance has its own name:
– add1 (type full adder)
– add2 (type full adder).
■
Full
adder
b
Instantiating component types
■
cout
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Revised by SG: December 1, 2002
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Timing abstraction
■
At circuit level: clock is just an ordinary
signal;
■ At register-transfer level (RTL) : a clock
only connects to flipflops;
■ At algorithmic level: no explicit clock,
number of clock cycles not yet known.
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Modern VLSI Design 3e: Chapter 1
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Top-down vs. bottom-up design
■
Top-down design adds functional detail.
– Create lower levels of abstraction from upper
levels.
■
Bottom-up design creates abstractions from
low-level behavior; it reuses subblocks with
proven characteristics.
■ Good design needs both top-down and
bottom-up efforts.
Revised by SG: December 1, 2002
Modern VLSI Design 3e: Chapter 1
Design validation
■
Must check at every step that errors haven’t
been introduced–the longer an error
remains, the more expensive it becomes to
remove it.
■ Forward checking: compare results of lessand more-abstract stages.
■ Back annotation: copy performance
numbers to earlier stages.
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Manufacturing test
■
Not the same as design validation: just
because the design is right doesn’t mean
that every chip coming off the line will be
right.
■ Must quickly check whether manufacturing
defects destroy function of chip.
■ Must also speed-grade.
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The cost of fabrication
■
Current cost: about $2-3 billion.
■ Typical fab line occupies about 1 city block,
employs a few hundred people.
■ Most profitable period is first 18 months-2
years.
Cost factors in ICs
■
– silicon area (about 0.07
$/mm2)
– packaging (0.1 upto
several dollars)
– testing (about 0.05
$/sec)
■
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■
Recurrent costs:
– design time (about 100
$/hour)
– mask sets (in the order
of 100 k$ per set)
■
Typical IC: 10 to 100
mm2, 1 to 10 seconds
of test time.
Revised by SG: December 1, 2002
Modern VLSI Design 3e: Chapter 1
Non-recurrent costs:
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It often happens that
silicon is not “first
time right” → new
mask sets per
redesign.
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