Lecture Outline
ESE 570: Digital Integrated Circuits and
VLSI Fundamentals
!
Design Methodologies
!
Implementation Methodologies
!
Design Quality
!
Packaging
"
Lec 23: April 12, 2016
VLSI Design and Variation
"
"
Penn ESE 570 Spring 2016 – Khanna
Hierarchy, Modularity, Regularity, Locality
Custom, Semi-Custom (cell-based, array-based)
Variation
Penn ESE 570 Spring 2016 – Khanna
2
Y-Chart
Three Domain View of VLSI Design Flow at One Level
FUNCTIONAL DESIGN
Verilog/Spectre
Verilog/Spectre
Verilog/Cadence
SPICE
Spectre
(Spectre)
Extract Parasitic Elements
LAYOUT
VERIFICATION
1. Design Rule Check (DRC)
2. Layout Versus Schematic
(LVS) Check
3. Post layout simulation (PLS)
Cadence
(Virtuoso)
PLS
3
Metrics for Design Success:
"
Performance Specs
"
Time to Design
"
Ease of Test Generation and Testability
"
"
"
!
!
logical function, speed, power, area
Strategies common for complex hardware and
software projects
"
engineering cost and schedule
"
engineering cost, manufacturing cost, schedule
"
Design is a continuous tradeoff to achieve
performance specs with adequate results in the
other metrics
Penn ESE 570 Spring 2016 – Khanna
4
Kenneth R. Laker,
University of
Pennsylvania,
Structured Design Strategies
updated 6Apr15
Design Strategies
!
Penn ESE 570 Spring 2016 – Khanna
"
5
Hierarchy: Subdivide the design in several levels of submodules
Modularity: Define sub-modules unambiguously and well
defined interfaces
Regularity: Subdivide to max number of similar submodules at each level
Locality: Max local connections, keeping critical paths
within module boundaries
Penn ESE 570 Spring 2016 – Khanna
6
1
Modularity
!
!
!
!
Adds to the hierarchy and regularity Unambiguous functions
Well defined beahvioural, structural, and physical
interfaces
Enables modules to be individually designed and
evaluated
add4
c
add
add
add
sum
a[1]
b[0]
a[0]
(0,0)
s
sum
s
carry
co
i
n
v
nor
b[1]
nand
co3
a[2]
+
8
Floorplanning: Map Structural into Physical
(100,400)
s[3]
add1 Cell
(100,300)
b[2]
nor
a[3:0]
a[3]
add[3]
nand
b[3]
s[3:0]
nor
c0
+
+
add4
+
+
nand
Hierarchical & Modular Layout
b[3:0]
nor
nand
7
Penn ESE 570 Spring 2016 – Khanna
c
b
a
c
b
a
carry
carry
sum
carry
sum
sum
Eg. 4b Adder
c0
b
a
add
co
carry
!
Hierarchical & Modular 4-bit Adder
add[2] s[2]
(100,200)
(50,100)
(0,75)
b[i]
add[1] s[1]
(100,100)
add[0] s[1]
co3
(0,0)
a[i]
Unused die area ->
inefficient layout
c[i]
add[i]
(0,25)
(100,100)
s[i]
(100,50)
Structural Hierarchy
1 mapped poorly into
Physical Hierarchy.
co[i]
(50,0)
(100,0)
Better
mapping!
(0,100)
add4 Module
Miss-mappings between Structural and Physical Hierarchies usually avoided by using
automatic layout system.
Penn ESE 570 Spring 2016 – Khanna
9
Regularity
!
Penn ESE 570 Spring 2016 – Khanna
Locality (Physical)
Design the chip reusing identical modules, circuits,
devices.
!
TIME LOCALITY: modules are synchronized by
common clock.
"
!
Regularity can exist at all levels of the design
hierarchy
"
"
"
"
"
Circuit Level: Uniform transistor sizes rather than
manually optimizing each device
Logic Level: Identical gate structures rather than
customize every gate
Architecture Level: construct architectures that use a
number of identical sub-structures
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 6Apr15
10
"
"
11
Critical timing paths are kept within module boundaries
Place modules to minimize large or “global” inter-module
signal routes
Take care to realize robust clock generation and
distribution
Signal routes between modules with large physical
separation need sufficient time to traverse route
Replicate modules, if necessary, to alleviate delay issues
caused by long intermodule signal routes.
Penn ESE 570 Spring 2016 – Khanna
12
2
Implementation Methodologies
CMOS Chip Design Options
Digital Circuit Implementation Approaches
Custom
Cell-based
Standard Cells
Compiled Cells
Design Time and Cost
Decreasing (for a given
application)
Semicustom
Ma cro Cells
Array-based
Pre-diffused
(Gate Arrays)
Performance Increasing,
Die Area Decreasing,
Power Dissipation
Increasing (for a given
application)
Pre-wired
(FPGA's)
Penn ESE 570 Spring 2016 – Khanna
14
Penn ESE 570 Spring 2016 – Khanna
Prewired Arrays
Kenneth R. Laker,
University of
Pennsylvania,
Array-Based
Programmable Logic
updated 6Apr15
I5
Categories of prewired arrays (or field-programmable
devices):
!  Fuse-based (program-once)
!  Non-volatile EPROM based
!  RAM based
I4
I3
I2
I1
I0
Programmable
OR array
Programmable AND array
I3
I2
I1
I0
Programmable
OR array
Fixed AND array
I5
I4
I3
I2
I1
I0
Fixed OR array
Programmable AND array
O 3O 2 O 1 O 0
O 3O 2O 1O 0
PLA
PROM
O 3O 2O 1O 0
PAL
Indicates programmable connection
Indicates fixed connection
Penn ESE 570 Spring 2016 – Khanna
Programming a PROM
X2
X1
X0
FPGA Features
Configurable I/O
Configurable Logic
Programmable
Interconnect/routing
I/O Buffers
Program/Test/Diagnostics
I/O Buffers
Vertical routes
I/O Buffers
1
Field-Programmable Gate Arrays Fuse-based
Rows of logic modules
Routing channels
: programmed node
NA NA f 1 f 0
I/O Buffers
Penn ESE 570 Spring 2016 – Khanna
3
Standard-Cells Based Design
Field-Programmable Gate Arrays RAM-based
!
!
CLB
CLB
!
switching matrix
Horizontal
routing
channel
Predominant custom design style
Standardization is achieved at the logic or function
level
Specific designs for each gate are developed and
stored in a software database of cell library
"
Interconnect point
CLB
CLB
!
Vertical routing channel
Penn ESE 570 Spring 2016 – Khanna
Feedthrough Cell
nand, nor, xor, inv, buffers, latches, registers
"
20
Cell-based Design (or standard cells)
SSI logic
"
Logic Cell
each gate can have multiple implementations to provide proper drive for
different fan-outs, eg. standard size, 2x, 4x
MSI logic
"
decoders, encoders, adders, comparators
!
Datapath
!
Memories
!
System level
"
"
"
Rows of Cells
!
Layout is usually automatically placed and routed
using CAD software
Penn ESE 570 Spring 2016 – Khanna
Standard Cell Library Contents
!
Bahavioural, structural, and physical domain descriptions
per cell
ALUs, register files, shifters
RAM, ROM
Routing
Channel
Functional
Module
(RAM,
multiplier, …)
Routing channel
requirements are
reduced by presence
of more interconnect
layers
multipliers, microcontrollers
Penn ESE 570 Spring 2016 – Khanna
21
Standard Cell - Example
Penn ESE 570 Spring 2016 – Khanna
Automatic Cell Generation
3-input NAND cell
(from Mississippi State Library)
characterized for fanout of 4 and
for three different technologies
Penn ESE 570 Spring 2016 – Khanna
Random-logic layout
generated by CLEO
cell compiler (Digital)
Penn ESE 570 Spring 2016 – Khanna
4
Design Quality
!
!
!
Variation Types
Achieve specifications (static and dynamic)
Die Size
Power dissipation
!
!
Many reasons why variation occurs and shows up in
different ways
Scales of variation
"
!
!
!
!
Testability
Yield and Manufacturability
Reliability
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 6Apr15
!
Random dopant fluctuation
Local oxide variation
Line edge roughness
Etch and growth rates
!
Transistors differ from each other in random ways
!
27
Impact
!
Changes parameters
!
Change transistor behavior
"
"
"
"
26
Random Transistor-to-Transistor
!
Source: Noel Menezes, Intel ISPD2007
Systematic, spatial, random (uncorrelated)
Penn ESE 570 Spring 2016 - Khanna
!
Penn ESE 570 Spring 2016 - Khanna
Correlations of variation
"
25
Wafer-to-wafer, die-to-die, transistor-to-transistor
Penn ESE 570 Spring 2016 - Khanna
28
Vth Variability @ 65nm
W, L, tOX, Vth
W?
L?
tOX?
" W %)
V2 ,
IDS = µn COX $ '+(VGS − VT )VDS − DS .
# L &*
2 Penn ESE 570 Spring 2016 - Khanna
29
[Bernstein
Penn ESE 570 Spring 2016 - Khanna
et al, IBM JRD 2006]
30
€
5
Impact of Vth Variation?
!
Impact Performance
Higher Vth?
"
"
"
!
Penn ESE 570 Spring 2016 - Khanna
31
Impact of Vth Variation?
!
Penn ESE 570 Spring 2016 - Khanna
!
Not turn off as well # leaks more
See a range of parameters
"
"
# VGS −VT &
(
nkT / q '
#W & %
IDS = IS"% (e$
$L'
32
Variation
Lower Vth?
"
Vth # Ids # Delay (Ron * Cload)
Not drive as strongly
Id,vsat∝ (Vgs-Vth)
Performance?
L: Lmin – Lmax
Vth: Vth,min – Vth,max
# VDS & &
#
(
−%
%1 − e $ kT / q ' ((1+ λVDS )
$
'
Penn ESE 570 Spring 2016 - Khanna
33
Penn ESE 570 Spring 2016 - Khanna
34
€
Variation
!
!
Variation
Margin for expected variation
Must assume Vth can be any value in range
"
!
See a range of parameters
"
Speed # assume Vth slowest value
"
Ion,min=Ion(Vth,max)
!
Id,vsat∝ (Vgs-Vth)
Validate design at extremes
"
Probability Distribution
L: Lmin – Lmax
Vth: Vth,min – Vth,max
"
Work for both Vth,min and Vth,max ?
Design for worst-case scenario
VTH
Penn ESE 570 Spring 2016 - Khanna
35
Penn ESE 570 Spring 2016 - Khanna
36
6
Margining
!
Process Corners
Also margin for
!
Temperature
Voltage supply
"  Aging: end-of-life
!
"
!
"
Many effects independent
Many parameters
With N parameters,
"
"
!
Try to identify the {worst,best} set of parameters
!
Use corners to bracket behavior
"
Penn ESE 570 Spring 2016 - Khanna
37
Simple Corner Example
Look only at extreme ends (low, high)
How many cases?
Slow corner of design space, fast corner
Penn ESE 570 Spring 2016 - Khanna
Process Corners
!
What happens
at various
corners?
350mV
!
!
Many effects independent
Many parameters
Try to identify the {worst,best} set of parameters
"
Vthp
E.g. Lump together things that make slow
"
"
"
!
150mV
150mV
38
Vthn, Vthp, temperature, Voltage
Try to reduce number of unique corners
Slow corner of design space
Use corners to bracket behavior
350mV
Vthn
Penn ESE 570 Spring 2016 - Khanna
39
Range of Behavior
Still get range of performances
Any way to exploit the fact some are faster?
Probability Distribution
!
40
Speed Binning
Probability Distribution
!
Penn ESE 570 Spring 2016 - Khanna
Sell
Premium
Sell
nominal
Sell
cheap
Discard
Delay
Delay
Penn ESE 570 Spring 2016 - Khanna
41
Penn ESE 570 Spring 2016 - Khanna
42
7
Design Quality
!
Testability
"
"
!
generation of good test vectors
design of testable chip
Yield and Manufacturability
"
"
!
Packaging Technology
functional yield
parametric yield
Reliability
"
"
"
"
"
threshold variation
premature aging
power and ground bouncing
ESD/EOS -> can compensate in padframe
noise and crosstalk
Penn ESE 570 Spring 2016 - Khanna
43
44
Penn ESE 570 Spring 2016 - Khanna
Kenneth R. Laker,
University of
Pennsylvania,
Parasitics in an Electronic Package
updated 6Apr15
Package Bonding Techniques
Wire Bond
Package Body
PCB Transmission Line
Die
Paddle
PCB Ground Plane
PCB Vias
Penn ESE 570 Spring 2016 - Khanna
45
Kenneth R. Laker,
University of
Pennsylvania,
Summary of Package Types
updated 6Apr15
Penn ESE 570 Spring 2016 - Khanna
46
Kenneth R. Laker,
University of
Pennsylvania,
Admin
updated 6Apr15
!
!
!
HW 7 and 8 graded by Friday
EC graded by Monday
Final Project
"
Design memory (SRAM)
"
EC for best figure of merits (FOM = Area*Power*Delay2)
"
Can propose extra work for extra credit
"
"
Due 4/26 (last day of class)
"
"
47
# of points depends on teams reported
Everyone gets an extension until 5/6 (day of final exam)
Keep an eye on Piazza for useful information and updates
on project handout for clarity
Penn ESE 570 Spring 2016 – Khanna
48
8
Final Project Schedule
!
Posted now
April 11th – report teams to instructor
April 14th – extra credit proposals due to instructor
April 26th – final report due
!
May 6th – extension for reports (also day of final)
!
All deadline times are midnight that day
!
!
!
"
Must be submitted via Canvas
Penn ESE 570 Spring 2016 – Khanna
49
9