Lecture Outline
ESE 570: Digital Integrated Circuits and
VLSI Fundamentals
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!
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Lec 21: April 5, 2016
Memory Overview, Memory Core Cells
Memory Overview
ROM Memories
RAM Memory
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Penn ESE 570 Spring 2016 – Khanna
SRAM
DRAM
Penn ESE 570 Spring 2016 – Khanna
2
A Typical Computer System
Memory Overview
CPU
L1-D
L1-I
L2-Cache
Video
RAM
System bus
Ch 1
AGP
Memory
GPU bus
Controller Ch 2
USB bus
Disk
Adapter
Ethernet
Adapter
Penn ESE 570 Spring 2016 – Khanna
CPU Chip
L1 on-CPU
cache
!
1k to 64 k SRAM (register file)
L2
64k to 4M
L3
4M to 32M SRAM or DRAM
L4
!
Memory hierarchies exploit locality by cacheing (keeping
close to the processor) data likely to be used again
This is done because we can build
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≥ 8M
!
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Kenneth R. Laker,
University of
Pennsylvania,
updated 02Apr15
5
large, slow memories OR
small, fast memories BUT
we can’t build large, fast memories
If hierarchy works, we get the illusion of SRAM access time
with disk based memory capacity.
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Penn ESE 570 Spring 2016 – Khanna
4
Kenneth R. Laker,
University of
Pennsylvania,
Locality and Cacheing
updated 02Apr15
CPU Memory Hierarchy
off-chip
cache
memory
DRAM
DIMM
PCI bus
I/O
Controller
Other
buses
Penn ESE 570 Spring 2016 – Khanna
DRAM
DIMM
SRAM (static RAM) -- 5-20 ns access time, very expensive (on-CPU
faster)
DRAM (dynamic RAM) -- 60-100 ns, cheaper
Disk -- access time measured in milliseconds, very cheap
Penn ESE 570 Spring 2016 – Khanna
6
1
Semiconductor Memory Classification
Memory Architecture: Core
M bits
FIFO
SRAM
Word 0
S1
EPROM
Mask-Programmed
E2PROM
Programmable (PROM)
Word 1
S2
SN-2
Penn ESE 570 Spring 2016 – Khanna
M bits
SN-2
SN_ 1
Word 0
Word 2
Word N-2
Word N-1
Word N-1
Input-Output
(M bits)
Input-Output
(M bits)
Decoder reduces # of select signals
K = log2N
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
M bits
S0
Storage
Cell
Word N-2
Word N-1
Word 1
A1
Word 2
A K -1
Bit Line
2L-K
Storage Cell
Word 0
A0
Decoder
N Words
S2
Storage
Cell
Penn ESE 570 Spring 2016 – Khanna
Memory Architecture: Decoders
Word 1
Word 2
N words => N select signals
Too many select signals
CAM
S1
Word 1
A1
FLASH
Shift Register
S0
Word 0
A0
A K -1
Word N-2
SN_ 1
LIFO
DRAM
Storage
Cell
Word 2
Decoder
Non-Random
Access
M bits
S0
AK
Storage
Cell
AK+1
AL-1
Row Decoder
Random
Access
ROM
N Words
NVRWM
RWM
S0
Word Line
Word N-2
M.2K
Word N-1
Sense Amplifiers / Drivers
Input-Output
(M bits)
N words => N select signals
Too many select signals
Penn ESE 570 Spring 2016 – Khanna
Input-Output
(M bits)
A0
Column Decoder
AK -1
Decoder reduces # of select signals
K = log2N
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Input-Output
(M bits)
Penn ESE 570 Spring 2016 – Khanna
MOS NOR ROM
ROM Memories
VDD
Pull-up devices
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
BL[0]
Penn ESE 570 Spring 2016 – Khanna
BL[1]
BL[2] BL[3]
Penn ESE 570 Spring 2016 – Khanna
2
MOS NOR ROM
MOS NOR ROM
VDD
VDD
Pull-up devices
WL[0]
1
0
1
1
Pull-up devices
WL[0]
1
0
1
1
WL[1]
0
1
1
0
WL[2]
1
0
1
0
WL[3]
1
1
1
1
GND
WL[1]
WL[2]
GND
WL[3]
BL[0]
BL[1]
BL[2] BL[3]
BL[0]
Penn ESE 570 Spring 2016 – Khanna
BL[1]
GND
GND
BL[2] BL[3]
Penn ESE 570 Spring 2016 – Khanna
Non-Volatile Memory ROM
Contact-Mask Programmable ROM
PseudonMOS
NOR gate
Penn ESE 570 Spring 2016 – Khanna
15
Kenneth R. Laker,
University of
Pennsylvania,
Contact-Mask Programmable ROM
updated 02Apr15
16
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
MOS NAND ROM
updated 02Apr15
V DD
Pull-up devices
BL[0]
BL[1]
BL[2]
BL[3]
WL[0]
WL[1]
WL[2]
WL[3]
All word lines high by default with exception of selected row
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 02Apr15
17
Penn ESE 570 Spring 2016 – Khanna
3
MOS NAND ROM
MOS NAND ROM
V DD
V DD
Pull-up devices
BL[0]
WL[0]
0
BL[1]
1
BL[2]
0
Pull-up devices
BL[3]
BL[0]
0
WL[0]
WL[1]
WL[1]
WL[2]
WL[2]
WL[3]
WL[3]
All word lines high by default with exception of selected row
BL[1]
BL[2]
BL[3]
0
1
1
0
0
0
0
1
0
1
0
1
0
0
0
0
All word lines high by default with exception of selected row
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
Read-Write Memories (RAM)
RAM Memories
• STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
• DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
6T SRAM Cell
!
!
Cell size accounts for most of memory array size
6T SRAM Cell
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"
!
WL
VDD
Used in most commercial chips
Data stored in cross-coupled inverters
M2
"
Precharge BL, BL’
Raise WL
Write:
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"
M6
Q
BL
bit
M5
BL’
bit_b
word
WL
M1
Drive data onto BL, BL’
Raise WL
Penn ESE 570 Spring 2016 – Khanna
M4
Q
Read:
"
!
6-transistor CMOS SRAM Cell
BL
23
M3
BL
Penn ESE 570 Spring 2016 – Khanna
4
6-transistor CMOS SRAM Cell
6-transistor CMOS SRAM Cell
Assume 1 is stored
(Q=1)
WL
VDD
M2
M4
M6
M5
Read Operation
M1
M4
Q
M6
Q
M5
VDD
M1
M3
BL
BL
Penn ESE 570 Spring 2016 – Khanna
VDD
1
0
M3
BL
BL
Penn ESE 570 Spring 2016 – Khanna
CMOS SRAM Analysis (Read)
6-transistor CMOS SRAM Cell
WL
Assume 1 is stored
(Q=1)
VDD
M4
BL
Q= 0
VDD
M2
Write Operation
Q=1
M1
WL
BL
M6
M5
V DD
VDD
M2
Assume bitlines
precharged to Vdd
Q
Q
WL
Assume 1 is stored
V DD
(Q=1)
Cbit
V DD
C bit
M4
Q
M6
Q
Write 0 to cell
VDD
BL=GND, BL=VDD
M5
GND
1
0
M1
M3
BL
BL
2
kn, M5 ⎛ V
VDD V 2 ⎞
⎛ V D D⎞ ⎞
⎛
DD
DD
--------------- ⎝ ----------- – VTn ⎝ ------------⎠ ⎠ = kn, M1 ⎝ ( VD D – V Tn ) ------------ – ----------2
2
2
2
8 ⎠
(W/L)n,M5 ≤ 10 (W/L)n,M1
(supercedes read constraint)
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
CMOS SRAM Analysis (Write)
6T SRAM Cell
!
WL
"
M4
!
Q=0
Q=1
M5
Read:
"
VDD
M6
Precharge BL, BL’
Raise WL
Write:
"
"
bit
bit_b
BL
BL’
word
WL
Drive data onto BL, BL’
Raise WL
M1
VDD
BL = 1
BL = 0
!
Design Strategy?
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"
2
2
VDD VDD
VDD VDD
⎛
⎞
⎛
⎞
k n, M6 ⎝ ( VDD – VTn ) ----------- – ----------- ⎠ = k p, M4 ⎝( VDD – VTp ) ----------- – ----------- ⎠
2
2
8
8
2
kn, M5ESE
Penn
– Khanna
⎛ VDD570 Spring
⎛ VDD ⎞2016
⎞
⎛
2
V DD VDD
⎞
--------------⎝ ----------- – VTn ⎝ -----------⎠ ⎠ = kn , M1 ⎝ ( V DD – VTn )----------- – ----------2
2
2
2
8 ⎠
(W/L)n,M6 ≥ 0.33 (W/L)p,M4
(W/L)n,M5 ≥ 10 (W/L)n,M1
(1) data-read operation should
not destroy stored data
(2) data-write operation should
allow modification of stored data
Penn ESE 570 Spring 2016 – Khanna
30
5
CMOS SRAM Analysis (Read)
CMOS SRAM Analysis (Read)
Assume 0 is stored
(Q=0)
Assume 0 is stored
(Q=0)
V1 must not exceed VT,n so M2 stays OFF
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
SRAM Read
!
!
!
!
Precharge both bitlines high
Then turn on wordline, WL
One of the two bitlines will be pulled down by the
BL
cell
bit
word
WL
Ex: A = 0, A_b = 1
P1 P2
N2
"
"
!
CMOS SRAM Analysis (Read)
BL discharges, BL’ stays high
But A bumps up slightly
A
"
A must not flip
N1 >> N2
BL’
bit_b
N4
A_b
N1 N3
Read stability
"
Assume 0 is stored
(Q=0)
BL’
bit_b
A_b
1.5
1.0
bit
BL
word
WL
0.5
V1,max<VT,2
A
0.0
0
100
200
300
400
500
600
time (ps)
Penn ESE 570 Spring 2016 – Khanna
33
CMOS SRAM Analysis (Read)
Penn ESE 570 Spring 2016 – Khanna
CMOS SRAM Analysis (Read)
Assume 0 is stored
(Q=0)
Assume 0 is stored
(Q=0)
If VDD=5V,
VT,n=1V
=.778
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
6
CMOS SRAM Analysis (Read)
6T SRAM Cell
Assume 0 is stored
(Q=0)
!
Read:
"
"
!
Write:
"
"
!
If VDD=1V,
VT,n=0.2V
=.778
Penn ESE 570 Spring 2016 – Khanna
Precharge BL, BL’
Raise WL
bit
bit_b
BL
BL’
word
WL
Drive data onto BL, BL’
Raise WL
Design Strategy?
"
"
(1) data-read operation should
not destroy stored data
(2) data-write operation should
allow modification of stored data
Penn ESE 570 Spring 2016 – Khanna
CMOS SRAM Analysis (Write)
38
CMOS SRAM Analysis (Write)
Assume 1 is stored
(Q=1), Write 0
Assume 1 is stored
(Q=1), Write 0
V2 stays below VT,n, by Read design strategy
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
CMOS SRAM Analysis (Write)
CMOS SRAM Analysis (Write)
Assume 1 is stored
(Q=1), Write 0
V1 must reduce below VT,n so M2 turns OFF
Penn ESE 570 Spring 2016 – Khanna
Assume 1 is stored
(Q=1), Write 0
V1=VT,n
Penn ESE 570 Spring 2016 – Khanna
7
CMOS SRAM Analysis (Write)
CMOS SRAM Analysis (Write)
Assume 1 is stored
(Q=1), Write 0
Assume 1 is stored
(Q=1), Write 0
If VDD=5V,
VT,n=1V, µn/µp=2
If VDD=1V,
VT,n=0.2V, µn/µp=2
=.389
=.389
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
DRAM
!
!
3-Transistor DRAM Cell
Smaller than SRAM
Require data refresh to compensate for leakage
BL1
BL2
WWL
WWL
RWL
RWL
M3
X
M1
X
M2
VDD -VT
BL1
VDD
BL2
VDD -VT
CS
ΔV
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = VWWL -VTn
Penn ESE 570 Spring 2016 – Khanna
45
1-Transistor DRAM Cell
DRAM Cell Observations
1T DRAM requires a sense amplifier for each bit line, due to
charge redistribution read-out.
BL
WL
Write "1"
Read "1"
WL
M1
CS
X
DRAM memory cells are single ended in contrast to SRAM cells.
VDD −VT
GND
The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
VDD
BL
VDD/2
CBL
Penn ESE 570 Spring 2016 – Khanna
sensing
VDD /2
Write: CS is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
CS
ΔV = V – V
(
) ----------------------BL
PRE = V BIT – V PRE C + C
S
Unlike 3T cell, 1T cell requires presence of an extra capacitance
that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage is lost.
This charge loss can be circumvented by bootstrapping the
word lines to a higher value than VDD .
BL
Voltage swing is small; typically around 250 mV.
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
8
Ideas
!
Memory for compact state storage
Share circuitry across many bits
!
To keep area down aggressively use:
!
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"
"
Admin
!
HW 8 due 4/7
EC (from HW 7) due 4/11
!
Final Project
!
Minimize area per bit # maximize density
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Pass transistors, Ratioing
Precharge, Amplifiers
Teams of up to 3 people
"
"
"
Design memory (SRAM or DRAM)
"
"
"
49
OR propose your own project by 4/11
Posted before Thursday class
Due 4/26 (last day of class)
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Penn ESE 570 Spring 2016 – Khanna
Don’t work alone!
Report your teams to me by 4/11
Everyone gets an extension until 5/6 (day of final exam)
Penn ESE 570 Spring 2016 – Khanna
50
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