Lecture Outline
ESE 570: Digital Integrated Circuits and
VLSI Fundamentals
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Review: Sequential MOS Logic
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Lec 19: March 29, 2016
Timing Hazards and Dynamic Logic
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Timing Hazards
Dynamic Logic
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Charge Sharing Setup
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Penn ESE 570 Spring 2016 – Khanna
SR Latch
D-Latch
Domino Logic
Dynamic D-Latch
Penn ESE 570 Spring 2016 – Khanna
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Latch
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Review: Sequential MOS Logic
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Level-sensitive device
Positive Latch
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Negative Latch
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Penn ESE 570 Spring 2016 – Khanna
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Q = CLK ⋅ Q + CLK ⋅ In
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Two Phase Non-Overlapping Clocks
Edge-triggered storage
element
Positive edge-triggered
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Output follows input if
CLK low
Penn ESE 570 Spring 2016 – Khanna
Register
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Output follows input if
CLK high
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Build master-slave register from pair of latches
Control with non-overlapping clocks
Input sampled on
rising CLK edge
Negative edgetriggered
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Input sampled on
falling CLK edge
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
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1
CMOS SR Latch – NOR2
CMOS SR Latch – NAND2
“ACTIVE LOW”
“ACTIVE HIGH”
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*
*
*
*
*
Penn ESE 570 Spring 2016 – Khanna
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Static CMOS TG D-LATCH – 8 Transistors
Penn ESE 570 Spring 2016 – Khanna
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Static CMOS TG D-LATCH
8 Transistors
When CK = 1 output Q = D, and tracks D until CK = 0, the D-Latch is
referred to positive level triggered.
**Transistor level implementation using transmission gates requires
fewer transistors
Penn ESE 570 Spring 2016 – Khanna
When CK → 1 to 0, the Q = D is captured, held (or stored) in the Latch.
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Kenneth R. Laker,
University of
Pennsylvania,
D-LATCH Timing Requirements
updated 25Mar15
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
D-Latch Metastability and Synchronization Failures
updated 25Mar15
latch,
case)
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
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2
Latch Timing Issues
Timing Hazards
Penn ESE 570 Spring 2016 – Khanna
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Latch Timing Issues
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Register from Latch
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Latch Timing Issues
tsu=time data (D) must be valid before CLK edge
tplogic=worst case propagation delay of logic
tc-p=worst case propagation delay of latch
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
thold=time data (D) must stay valid after CLK edge
tcdregister=minimum propagation delay of latch
tcdlogic=minimum propagation delay of logic
Penn ESE 570 Spring 2016 – Khanna
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Register from Latch
Build master-slave register from pair of latches
Control with non-overlapping clocks
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Build master-slave register from pair of latches
Control with non-overlapping clocks
Pos
Latch
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
Neg
Latch
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3
Register from Latch
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Register from Latch
Build master-slave register from pair of latches
Control with non-overlapping clocks
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Build master-slave register from pair of latches
Control with non-overlapping clocks
Negative edge-triggered
Register
Pos
Latch
Positive edge-triggered
Register
Neg
Latch
Neg
Latch
Penn ESE 570 Spring 2016 – Khanna
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CMOS D Edge Triggered Flip-Flop
Penn ESE 570 Spring 2016 – Khanna
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Impact of Non-ideal Clock on D-Latch Operation
Negative D-Latch
CLK
non-ideal
ideal
CLK
NMOS
PMOS
Pos
Latch
CLK
t
CLK + τD
t
NMOS
PMOS
Positive D-Latch
CLK & CLK
Positive Edge Triggered D Flip-Flop = Negative D-Latch + Positive D-Latch
Negative Edge Triggered D Flip-Flop = Positive D-Latch + Negative D-Latch
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Penn ESE 570 Spring 2016 – Khanna
ϕ1
ϕ2
ϕ2
Penn ESE 570 Spring 2016 – Khanna
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Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
Two-Phase Clocked D-Latch (non-overlapping)
ϕ1
CLK & CLK + τD
Dynamic Logic
t
t
ϕ1
NMOS
PMOS
ϕ1
Penn ESE 570 Spring 2016 – Khanna
ϕ2
ϕ2
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Penn ESE 570 Spring 2016 – Khanna
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4
Logic Comparison Overview
Logic Comparison Overview
bit_b
bit
word
P1 P2
N2
A
N4
A_b
N1 N3
BL
DYNAMIC LOGIC GATES: valid logic level are not steady-state
op points and depend on temporary storage of charge on parasitic
node capacitances. Outputs are generated in response to input
voltage levels and a clock. Requires periodic updating or refresh.
WL
DYNAMIC LOGIC GATES: valid logic level are not steady-state
op points
and depend on temporary storage of charge on parasitic
V −V
nodeV capacitances. Outputs are generated in response to input
BL
V /2
V /2
voltage
levels
and a clock. Requires periodic updating or refresh.
Write "1"
Read "1"
WL
M1
CS
X
GND
DD
T
DD
CBL
DD
sensing
DD
Write: CS is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
CS
ΔV = V – V
(
) ----------------------BL
PRE = V BIT – V PRE C + C
S
BL
Voltage swing is small; typically around 250 mV.
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Penn ESE 570 Spring 2016 – Khanna
Comparison of Logic Implementations
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Penn ESE 570 Spring 2016 – Khanna
Comparison of Logic Implementations
Y
Y
Ratioed
Ratioed
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
Comparison of
Logic Implementations
updated 25Mar15
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
Comparison of
Logic Implementations
updated 25Mar15
Y
Y
Ratioed
Ratioed
VDD
1
more
robust
1
1
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
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Penn ESE 570 Spring 2016 – Khanna
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5
Dynamic CMOS Precharge
Dynamic CMOS Precharge
VDD
Mp
A
CK
Z
Z
Z
Me
of C is complete
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
Dynamic (Clocked) Logic: Example
updated 25Mar15
Penn ESE 570 Spring 2016 – Khanna
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Kenneth R. Laker,
University of
Pennsylvania,
Comparison of Static and Dynamic Logic
updated 25Mar15
ADVANTAGES ?
DISADVANTAGES ?
CK = 0 => Z = ?
CK = 1 => Z = ?
Penn ESE 570 Spring 2016 – Khanna
33
Kenneth R. Laker,
University of
Pennsylvania,
Comparison of Static and Dynamic Logic
updated 25Mar15
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
Penn ESE 570 Spring 2016 – Khanna
34
Kenneth R. Laker,
University of
Pennsylvania,
Comparison of Static and Dynamic Logic
updated 25Mar15
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
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6
Cascaded Dynamic Logic
Penn ESE 570 Spring 2016 – Khanna
Cascaded Dynamic Logic
37
Kenneth R. Laker,
University of
Pennsylvania,
Domino Logic
updated 25Mar15
Kenneth R. Laker,
University of
Pennsylvania,
Requirements
updated 25Mar15
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Single transition
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All inputs at 0 during precharge
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Once transitioned, it is done # like domino falling
‘Outputs’ pre-charged to 1 then inverted to 0
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Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
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Cascaded Domino CMOS Logic Gates
I.e. Inputs are pre-charge to 0
Non-inverting gates
Penn ESE 570 Spring 2016 – Khanna
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Cascaded Domino CMOS Logic Gates
propagating
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
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7
CMOS Dynamic D Latch
Charge Leakage Setup
D
Q
Cx is usually a
parasitic
capacitance
Positive
levelsensitive
NMOS
PMOS
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15Latch circuit:
Comparison CMOS Static & Dynamic D-Latch
NOTE: No crosscoupled inverters)
ϕ1
Data bit stored in
bistable-loop when
ϕ1 = 1 → 0
Static D-Latch
Flip-Flop
Latch
ϕ
1
NMOS
PMOS
Dynamic DLatch
Data bit stored on Cx
when CK = 1 → 0
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
Vy ≤ VT0n,M3 = 1.0 V;
Vy = VT0n = 1V
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
47
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
(VGD > VT0p)
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Vy ≤ VT0n,M3 = 1.0 V;
Vy = VT0n = 1V
Vy ≤ VT0n,M3 = 1.0 V;
Vy = VT0n = 1V
(VGD > VT0p)
(VGD > VT0p)
i.e. Vx can drop from Vx-max = VDD – VTMP to Vx-min = 2.55 V due to charge
leakage before VQ is effected (i.e. the output changes state).
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
Ideas
updated 25Mar15
Kenneth R. Laker,
University of
Pennsylvania,
Admin
updated 25Mar15
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Sequential Circuits lead to clocked circuit discipline
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Uses state holding element
Prevents
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Design 8 bit adder
Extra Credit: Modify design for optimized delay (Submit
online before 4/11)
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Get up to 10 points added to your Midterm grade
Dynamic/clocked logic
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HW 7 due 3/31
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Timing assumptions
(More) complex reasoning about all possible timings
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Only build/drive one pulldown network
Fast transition propagation
Domino Logic allows for cascading
Have to worry about charge sharing… next time
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
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