Lecture Outline
ESE 570: Digital Integrated Circuits and
VLSI Fundamentals
!
!
!
Lec 2: January 19, 2016
MOS Fabrication pt. 1: Physics and
Methodology
Penn ESE 570 Spring 2016 - Khanna
Digital CMOS Basics
VLSI Fundamentals
Fabrication Process
2
Penn ESE 570 Spring 2016 - Khanna
Classification of Digital CMOS Circuits
Digital CMOS Basics
!
Static Circuit
"
!
Dynamic Circuit
"
Penn ESE 570 Spring 2016 - Khanna
3
MOS Transistors
Penn ESE 570 Spring 2016 - Khanna
Penn ESE 570 Spring 2016 - Khanna
4
S
D
B
D
In steady-state the output is evaluated due to the presence or absence
of charge, respectively, stored on the output node capacitance.
MOS Transistors
S
G
In steady-state the output is evaluated via a low-impedance path
between the output and VDD or GND, respectively.
G
G
B
B
D
S
5
D
Penn ESE 570 Spring 2016 - Khanna
G
B
S
6
1
Ideal nMOS and pMOS Characteristics
High Impedance or
High Z
D
G
D
g=0
D
S
D
g=1
S
D
g=1
g
a
S
S
g
S
-g
g=1
B
S
gG
S
Complementary CMOS Switch
B
S
g=0
g=1
D
D
S
b
g=0
-g
g
g
a
D
Da
Sb
g
-g
g=0
D
Penn ESE 570 Spring 2016 - Khanna
7
Ideal CMOS Inverter
Inverter Truth Table
Penn ESE 570 Spring 2016 - Khanna
8
CMOS Gates
VDD
Inverter Symbol
A
B
C
D
PUN
Inputs
F = f(A,B,C,D)
A
B
C
D
PDN
PUN and PDN are Dual
Networks
Penn ESE 570 Spring 2016 - Khanna
9
CMOS Gates
When the PUN is conducting, the output
F will be “1”. Hence,the PUN is
determined by a Boolean expression for
the un-complemented output F in terms
of the complemented inputs (A,B,C,D).
Output
When the PDN is conducting, the output F
will be “0”. Hence,the PDN is determined
by a Boolean expression for the
complemented output F in terms of the
un-complemented inputs (A,B,C,D).
Penn ESE 570 Spring 2016 - Khanna
10
What gate is this?
a
b
!
f
Complementary Metal Oxide Semiconductor
Penn ESE 570 Spring 2016 - Khanna
11
Penn ESE 570 Spring 2016 - Khanna
12
2
Static CMOS Gate Structure
!
Drives rail-to-rail
"
"
!
!
!
Two-Input CMOS NOR Gate
NOR
Power rails are Vdd and
Gnd
output is Vdd or Gnd
A
Input connects to gates
# load is capacitive
Once output node is
charged doesn’t use
energy (no static current)
Output actively driven
Penn ESE 570 Spring 2016 - Khanna
F
B
13
!
Design gate to perform:
1
1
1
0
2.
3.
Z = High Impedance
(open circuit)
4.
Penn ESE 570 Spring 2016 - Khanna
15
Gate Design Example
!
Design gate to perform:
14
f = (a + b)⋅ c
Use static CMOS
structure
Design PMOS pullup
for f
Use DeMorgan’s Law
to determine f ’
Design NMOS
pulldown for f ’
Penn ESE 570 Spring 2016 - Khanna
16
Static CMOS Source/Drains
f = (a + b)⋅ c
!
With PMOS on top,
NMOS on bottom
"
"
"
a
c
b
0
Strategy:
1.
B
0
Gate Design Example
!
F
0
Penn ESE 570 Spring 2016 - Khanna
Two-Input CMOS NAND Gate
A
1
f
PMOS source always at top
(near Vdd)
NMOS source always at
bottom (near Gnd)
Why not use NMOS for
pullup network?
Convince yourself with a truth table.
Penn ESE 570 Spring 2016 - Khanna
17
Penn ESE 570 Spring 2016 - Khanna
18
3
F
Multiplexor (MUX)
F
Constructing Compound CMOS Gates
F = (A ⋅ B + C ⋅ D)
output = A ⋅ s + B ⋅ s
Penn ESE 570 Spring 2016 - Khanna
19
Penn ESE 570 Spring 2016 - Khanna
20
Oracle SPARC M7 Processor
VLSI Fundamentals
Penn ESE 570 Spring 2016 - Khanna
Penn ESE 570 Spring 2016 - Khanna
VLSI Hierarchical Representations
22
Y-Chart: Abstractions in 3 Domains
fabricated?
- Circuit
- Component
Penn ESE 570 Spring 2016 - Khanna
23
Penn ESE 570 Spring 2016 - Khanna
24
4
Y-Chart: Abstractions in 3 Domains
Goal of All VLSI Design Enterprises
System Level
!
Algorithmic Level
Behavioral Domain
Register-Transfer Level
Structural Domain
System Specification
CPU, ASIC
Logic Level
Algorithm
Processor, Sub-system
Register-Transfer Spec.
ALU, Register, MUX
Circuit Level
Boolean Expression
Gate/Flip-flop
Transistor symbols
Transistor Model Equation
!
Transistor Layout
Standard-cell/Sub-cell Layout
Convert system pecs into an IC design
in MINIMUM TIME and with MAXIMUM
LIKLIHOOD that the Design will PEFORM AS
SPECIFIED when fabricated.
MAX YIELD + MIN DEVELOPMENT TIME +
MIN DIE AREA=> MIN COST
Macro-cell/Module Layout
Block/Die Layout
Chip/SoC/Board
Physical Domain
Penn ESE 570 Spring 2016 - Khanna
25
Penn ESE 570 Spring 2016 - Khanna
26
Silicon Ingot and Wafer Manufacturing
Fabrication Details
Crystal Puller with
rotation
mechanism
Single-Crystal
Silicon
Quartz
Crucible
Crystal Seed
Molten
Polysilicon
Heat
Shield
Heating
Water
Element
Image from Quirk & SerdaJacket
Penn ESE 570 Spring 2016 - Khanna
Penn ESE 570 Spring 2016 - Khanna
Silicon Wafer Manufacturing
Silicon Lattice
Si Ingots
300 mm
(12 in.)
!
28
!
Forms into crystal lattice
Si Wafers
The ROI of 450mm wafers is compelling:
"
"
A 450mm fab with equal wafer capacity to a 300mm fab can produce
2x the amount of die.
A 14nm die from a 450mm wafer will cost 23% less than the same
die from a 300mm wafer.
Penn ESE 570 Spring 2016 - Khanna
29
Penn
570 Spring
2016–- Khanna
Khanna
PennESE
ESE370
Fall2015
30
5
Silicon Lattice
!
Doping
Cartoon two-dimensional view
!
Add impurities to Silicon Lattice
"
Penn ESE 570 Spring 2016 - Khanna
31
Doping Elements
Penn ESE 570 Spring 2016 - Khanna
32
Doping with P (N-type)
!
End up with extra electrons
!
Not tightly bound to atom
"
(periodic table)
!
Replace a Si atom at a lattice site with another
"
"
Donor electrons
Low energy to displace
Easy for these electrons
to move
http://chemistry.about.com/od/imagesclipartstructures/ig/Science-Pictures/Periodic-Table-of-the-Elements.htm
Penn ESE 570 Spring 2016 - Khanna
33
Doping with B (P-type)
!
End up with electron vacancies -- Holes
!
Easy for electrons to shift into these sites
"
"
"
Penn ESE 570 Spring 2016 - Khanna
34
IC Manufacturing Steps
Acceptor electron sites
Low energy to displace
Easy for the electrons to move
"
Movement of an electron best viewed as movement of hole
Penn ESE 570 Spring 2016 - Khanna
35
Penn ESE 570 Spring 2016 - Khanna
36
6
Fabrication
!
!
!
!
!
Photolithography
Start with Silicon wafer
Dope
Grow Oxide (SiO2)
Deposit Metal
Mask/Etch to define
where features go
http://www.youtube.com/watch?v=35jWSQXku74
Time Code: 2:00-4:30
Penn ESE 570 Spring 2016 - Khanna
37
CMOS Processing Technology
38
Penn ESE 570 Spring 2016 - Khanna
Fabricated n-MOS Transistor
Boron atoms
deposited on
surface
time = 0 s
time = 60 s
39
Penn ESE 570 Spring 2016 - Khanna
n-MOS Transistor Representations
Physical Structure
Layout
field
poly
metal 1 Representation
oxide
gate
Ldrawn
S
n
+
gate
oxide
D
n
+
Leffective
S
n+
40
Penn ESE 570 Spring 2016 - Khanna
nMOS Transistor from a 3D Perspective
Schematic
Representation
Ldrawn
G
D
n+
Wdrawn
Gate
Oxide
p substrate (bulk)
Field
Oxide
P-Type
Penn ESE 570 Spring 2016 - Khanna
41
Penn ESE 570 Spring 2016 - Khanna
Source/Drain
Regions
Field
Oxide
42
7
Fabrication Process
Typical N-Well CMOS Process
Grow field oxide. Create contact
window, deposit & pattern metal film.
Penn ESE 570 Spring 2016 - Khanna
43
Typical N-Well CMOS Process
Penn ESE 570 Spring 2016 - Khanna
Big Idea
!
!
Penn ESE 570 Spring 2016 - Khanna
44
45
Systematic construction of
any gate from transistors
with CMOS PUN and
PDN
Hierarchical design
process in three domains
(behavioural, structural,
and physical) allows for
complicated designs
motivated cost as a
function of performance,
yield and design time
Penn ESE 570 Spring 2016 - Khanna
46
Admin
!
Enroll in Piazza site
!
Homework 1 due Thursday
"
"
piazza.com/upenn/spring2016/ese570
Journal articles will come back in Journal Review
Thursdays
Penn ESE 570 Spring 2016 - Khanna
47
8