Lecture Outline
ESE 570: Digital Integrated Circuits and
VLSI Fundamentals
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Lec 3: January 21, 2016
MOS Fabrication pt. 2: Design Rules and
Layout
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Penn ESE 570 Spring 2016 – Khanna
Adapted from GATech ESE3060 Slides
Review: MOS IV Curves and Switch Model
MOS Device Layout
Inverter Layout
Gate Layout and Stick Diagrams
Design Rules
Standard Cells
Linear Elements
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MOSFET
MOSFET – IV Characteristics
VDS
VGS = VG - VS
VDS = VD - VS
IDS
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Metal Oxide Semiconductor Field Effect Transistor
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Primary active component for the term
Three terminal device
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Drain current [arbitrary unit]
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40
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0
Voltage at gate controls conduction between two other terminals
(source, drain)
0
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Gate to source voltage [V]
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MOSFET – IV Characteristics
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Define:
Vth = Threshold Voltage
VGS
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MOSFET – IV Characteristics
VDS <VGS -VTH
VGS -Vth
IDS
VGS -Vth
IDS
VDS ≥VGS -VTH
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VDS
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VDS
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MOSFET – Zeroeth Order Model
MOSFET – Zeroeth Order Model
IDS
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Ideal Switch
VGS > Vth # switch is closed, conducts
VGS < Vth # switch is open, does not conduct
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Gate draws no current from input
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Loads input capacitively (gate capacitance)
VGS
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MOSFET – N-Type, P-Type
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N – negative carriers
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Switch turned on
positive VGS
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Symmetry
P – positive carriers
electrons
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holes
NMOS:
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Switch turned on
negative VGS
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Vth,p < 0
VGS < Vth,p
to conduct
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Symmetry
Current flows from drain-tosource
Like a resistor, doesn’t know difference between two ends
Drain and source are defined by circuit connections
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MOSFET – N-Type, P-Type
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PMOS:
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N – negative carriers
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positively
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Holes flow from source#drain
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Holes are carriers
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From lowest voltage#highest
Drain is most positive terminal
Symmetric Device
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Vth,n > 0
VGS > Vth,n
to conduct
Electrons are carriers
Electrons flow from source-to-drain
Flow from highest voltage#lowest
Drain is most negative terminal
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electrons
P – positive carriers
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Switch turned on
positive VGS
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holes
Switch turned on
negative VGS
Current flows from source-todrain
Symmetric Device
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Like a resistor, doesn’t know difference between two ends
Drain and source are defined by circuit connections
Penn ESE 570 Spring 2016 - Khanna
Vth,n > 0
VGS > Vth,n
to conduct
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Vth,p < 0
VGS < Vth,p
to conduct
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Typical N-Well CMOS Process
Typical N-Well CMOS Process
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Interconnect Cross Section
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CMOS Layers
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“Standard” n-Well Process
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ITRS 2007
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NMOS vs PMOS
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Active (Diffusion) (Drain/Source regions)
Polysilicon (Gate Terminals)
Metal 1, Metal 2, Metal3
Poly Contact (connects metal 1 to polysilicon)
Active Contact (connects metal 1 to active)
Via (connects metal 2 to metal 1)
nWell (PMOS bulk region)
n Select (used with active to create n-type diffusion)
p Select (used with active to create p-type diffusion) Penn ESE 570 Spring 2016 - Khanna
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MOS Layout – Well, Active, Select
NMOS built on p substrate
PMOS built on n substrate
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Needs an N-well
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MOS Layout – Poly Gate
CMOS Layers
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“Standard” n-Well Process
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Wiring and Contact Layout
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Properties
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Poly Contact
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Layout Example: CMOS Inverter
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Layout Example: CMOS Inverter
Set Pitch (place well and power/ground busses)
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Set Well and Substrate Voltages to Vdd and Gnd
Prevent Forward Biasing and Latch-Up
Must Be at Least One per Well
Should Be Placed Regularly
Via (metal1-metal2)
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Substrate and Well Contacts
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Diffusion (Active) Contact
Active (Diffusion) (Drain/Source regions)
Polysilicon (Gate Terminals)
Metal 1, Metal 2, Metal3
Poly Contact (connects metal 1 to polysilicon)
Active Contact (connects metal 1 to active)
Via (connects metal 2 to metal 1)
nWell (PMOS bulk region)
n Select (used with active to create n-type diffusion)
p Select (used with active to create p-type diffusion) !
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Add Transistors (active, select and poly)
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Layout Example: CMOS Inverter
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Layout Example: CMOS Inverter
Make Connections (poly, metal, and contacts)
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Layout Example: CMOS Inverter
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Add Substrate and Well Contacts
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Example: Mystery Gate
Add External Wiring and Resize
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Example: NAND Gate
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Example: NAND Gate (Horizontal)
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Symbolic Layout
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Layout Design Rules
Stick diagrams capture spatial relationships,
but abstract away design rules (coming up next…)
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Physical Layer
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Purpose
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What gate is this?
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Design Rules
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Intralayer (all layers)
Interlayer (active to poly/well/select)
From Transistor
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Definition
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Design Rules Based on a Unitless Parameter (λ)
λ Scales with Process Feature Size
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Minimum Width (all layers) [B] Minimum Overlap [C]
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Scalable CMOS Rules
Minimum Separation [A]
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Explicit permission granted by the fabrication organization to the
design organization to violate certain design rules or to allow certain
design rule errors on a given design
How many NMOS? PMOS? D/S connections?
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Realize fabricated chips that are die area efficient and manufacturable by balancing the conflicting objectives to minimize die area and
maximize yield
Design Rule Waiver "
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Design Rules are a set of process-specific geometric rules for
preparing layout artwork to enable the layout to be manufacturable, i.e. preserve all of the circuit structures and feature geometries
intended by the chip designers
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Advantages
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Past Transistor (poly, active)
Around Contact Cut (all contacted layers)
Around Active (well, select)
λ = 0.5*Lmin
Example: λ = 0.6 in a 1.2mm Process
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Simplifies Design - Requires Learning Only One Set of
Design Rules
Facilitates Translating Designs between Processes
Exact Size (contact cuts) [D]
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Contact Design Rules
Width/Spacing Design Rules
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Potential Consequences of Design Rule Violations
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Potential Consequences of Design Rule Violations
Inter-Layer Design Rule Origins
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Inter-Layer Design Rule Origins
Contact and Via Masks
Intended
Transistor
Intended
Unrelated Poly &
Diffusion
Catastrophic Error –
Unintended
misalignment cause
Source-Drain short
circuit
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capture a textual hierarchical description of design at abstraction
ranging from gate or even transistor level up to a behavioral
description (eg. VHDL, Verilog)
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capture a structural, hierarchical graphical representation of the
design netlist (eg. Cadence Composer)
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capture a hierarchical view of the physical geometric aspect of
a design. The units of hierarchy are called cells, and have physical
extent (size). In general, good design requires that only one cell
contain the design info for a particular area of the chip (eg. Cadence
Virtuoso)
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Circuit Extraction
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Physical Design Rules Checking (DRC) checks for design
rule violations such as minimum spacing etc. DRC checking is complicated
by hierarchy and overlap between cells
Electrical Rule Checking (ERC) checks for violations such as
shorts between Vdd and GND, opens, and so on
Layout vs. Schematic (LVS) checks for a one-to-one
correspondence between transistor schematic and the layout
Formal verification is used to show that the design satisfies a formal
description of what it should do
Simulation is used to show that the design is functional on some well
selected set of input vectors
Timing analysis is used to predict design performance Penn ESE 570 Spring 2016 - Khanna
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Standard Cells
Circuit extraction extracts a schematic representation of a
layout, including transistors, wires, and possibly wire and
device resistance and capacitance.
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Lay out gates so that heights match
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Rows of adjacent cells
Standardized sizes
Motivation: automated place and route
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Error – Unintended
misalignment cause
poor contact
Complex designs invariably suffer design and design entry errors. There
are a number of tools and methodologies to detect and correct
Layout
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Mask misalignment
Both Metal 1 &
Diffusion
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Schematic capture
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-> Via Mask
Rules Checking
Hardware Description Languages (HDL) &
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Mn contact to Mn-1 for n = 2, 3,..
Intended Contact
Alignment
Design Capture Tools
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-> Contact Mask
Both Metal 1 &
Diffusion
Catastrophic Error –
Unintended overlap
cause fabrication of a
parasitic Transistor
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M1 contact to n-diffusion
M1 contact to p-diffusion
M1 contact to poly
EDA tools convert HDL to layout
Circuit extraction is used for LVS, and for spice simu- lation
of layouts
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Standard Cell Area
Standard Cell Layout Example
All cells
uniform
height
inv
nand3
Cell
area
Width of
channel
determined
by routing
http://www.laytools.com/images/StandardCells.jpg
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CMOS Process Enhancements
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CMOS Poly-Poly Capacitors
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L
C. Bipolar Transistors
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Resistors
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Big Idea
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Layouts are physical realization of circuit
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Geometry tradeoff
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Can decrease spacing at the cost of yield
Design rules
Can go from circuit to layout or layout to circuit by
inspection
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Admin
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HW 1 should be submitted
HW 2 due next week 1/28
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Office hours updated on Course website
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Posted tonight after class
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