Lecture Outline
ESE 570: Digital Integrated Circuits and
VLSI Fundamentals
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Finish: Design Space Exploration
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Lec 18: March 24, 2016
Sequential MOS Logic and Timing Hazards
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Penn ESE 570 Spring 2016 – Khanna
Design Problem Example: Match Circuit
Sequential MOS Logic
Timing Hazards
Penn ESE 570 Spring 2016 – Khanna
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Design Problem
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Design Space Exploration
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Function: Identify equivalence of two 32bit inputs
Optimize: Minimize total energy
Assumptions: Match case uncommon
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Deliberately focus on Energy to complement
project
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Penn ESE 570 Spring 2016 – Khanna
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Design Space Dimensions
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CMOS, Ratioed (N load, P load)
Transistor Sizing
Vth
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The choices you make impact area, speed (delay), power
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Ptot = Pstatic + Pdyn+ Psc
We know many things we can do to our circuits
Design space is large
Systematically identify dimensions
Identify continuum (trends) tuning when possible
Watch tradeoffs
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Penn ESE 570 Spring 2016 – Khanna
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Three components of power
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Gate choice, logical optimization
Fanin, fanout, Serial vs. parallel
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Penn ESE 570 Spring 2016 – Khanna
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Gate style / logic family
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…but will still talk about delay
Ideas
Vdd
Topology
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Ie. Most of the time, the inputs won’t be matched
…don’t over-tune
Penn ESE 570 Spring 2016 – Khanna
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1
Classes of Logic Circuits
Sequential MOS Logic
two stable op. pts.
Latch – level triggered.
Flip-Flop – edge triggered.
one stable op. pt.
One-shot – single
pulse output
no stable op. pt.
Ring Oscillator
Combinational Circuits:
a. Current Output(s) depend ONLY on Current Inputs.
b. Suited to problems that can be solved using truth tables.
Sequential Circuits or State Machines:
a. Current Output(s) depend on Current Inputs and Past Inputs via State(s).
b. Suited to problems that are solved by completing several steps using
current inputs and past outputs in a specific order or a sequential manner.
Penn ESE 570 Spring 2016 – Khanna
Penn ESE 570 Spring 2016 – Khanna
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Kenneth R. Laker,
University of
Pennsylvania,
Sequential Circuit (or State Machine) Construct
updated
25Mar15
Inputs
Functions Using Sequential Operations
Outputs
Vo1
.
.
.
.
Present
State
REGISTER
.
.
.
.
Vo2
Vo3
Next
State
Clock
-> Register is used to Store Past Values of State(s) and Output(s)
-> Synchronous Sequential Circuit – clock, outputs change with clock event
-> Asynchronous Sequential Circuit – no clock, outputs change after inputs change
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
Static Bistable Sequential Circuits
updated 25Mar15
Static Bistable Sequential Circuits
Basic Crosscoupled Inverter
pair
Basic Crosscoupled Inverter
pair
Q
Q
Q
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
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Q
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
12
2
Static Bistable Sequential Circuits
Static Bistable Sequential Circuits
Basic Crosscoupled Inverter
pair
Basic Crosscoupled Inverter
pair
Q
VOH = VDD
Q
Q
Q
VOL = 0
maintain stable state.
STATIC: VDD and GND are required to maintain a stable state.
Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s)
to change the circuit's State.
Penn ESE 570 Spring 2016 – Khanna
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Kenneth R. Laker,
University of
Pennsylvania,
Latch
updated 25Mar15
Basic Sequential Circuits (Cells)
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Latches
Registers
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Level-sensitive device
Positive Latch
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Register
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Output follows input if
CLK low
Q = CLK ⋅ Q + CLK ⋅ In
Penn ESE 570 Spring 2016 – Khanna
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Shift Register
Edge-triggered storage
element
Positive edge-triggered
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Output follows input if
CLK high
Negative Latch
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Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
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How do you make a shift register out of latches?
Input sampled on
rising CLK edge
Negative edgetriggered
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Input sampled on
falling CLK edge
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
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Two Phase Non-Overlapping Clocks
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Two Phase Non-Overlapping Clocks
Build master-slave register from pair of latches
Control with non-overlapping clocks
Penn ESE 570 Spring 2016 – Khanna
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Two Phase Non-Overlapping Clocks
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Clocking Discipline
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What could go wrong if the overlap?
Penn ESE 570 Spring 2016 – Khanna
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CMOS SR Latch – NOR2
Follow discipline of combinational logic broken by
registers
Compute
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Penn ESE 570 Spring 2016 – Khanna
Two Phase Non-Overlapping Clocks
Build master-slave register from pair of latches
Control with non-overlapping clocks
Penn ESE 570 Spring 2016 – Khanna
Build master-slave register from pair of latches
Control with non-overlapping clocks
From state elements
Through combinational logic
To new values for state elements
As long as clock cycle long enough,
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Will get correct behavior
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Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
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CMOS SR Latch – NOR2
CMOS SR Latch – NOR2
basic crosscoupled inverter
pair
basic crosscoupled inverter
pair
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Penn ESE 570 Spring 2016 – Khanna
CMOS SR Latch – NOR2
CMOS SR Latch – NOR2
SET OP:
S = 1, R = 0
RESET OP:
R = 1, S = 0
basic crosscoupled inverter
pair
basic crosscoupled inverter
pair
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CMOS SR Latch – NOR2
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Penn ESE 570 Spring 2016 – Khanna
CMOS SR Latch – NOR2
HOLD OP:
S = 0, R = 0
HOLD OP:
S = 0, R = 0
basic crosscoupled inverter
pair
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
basic crosscoupled inverter
pair
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Penn ESE 570 Spring 2016 – Khanna
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CMOS SR Latch – NOR2
CMOS SR Latch – NAND2
basic cross-coupled
inverter pair
“ACTIVE HIGH”
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Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
Synchronous Latches
updated 25Mar15
CMOS SR Latch – NAND2
NAND
LATCHNOTE: S and R are
NAND
SRSR
Latch
asynchronous.
S/R
S’/R'
CK
“ACTIVE LOW”
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Penn ESE 570 Spring 2016 – Khanna
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Synchronous Latches
Synchronous Latches
NAND
LATCHNOTE: S and R are
NAND
SRSR
Latch
asynchronous.
S/R
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Penn ESE 570 Spring 2016 – Khanna
HOLD STATE:
CK = 1, S = 0, R = 0
S’/R'
T glitch
CK
Q error due to
glitch on S
SET STATE:
RESET STATE:
NOT ALLOWED:
CK = 1, S = 1, R = 0 => S' = 0, R' = 1 => Qn+1 = 1, Qn+1 = 0
CK = 1, S = 0, R = 1 => S' = 1, R' = 0 => Qn+1 = 0, Qn+1 = 1
CK = 1, S = 1, R = 1 => S' = 0, R' = 0
R
IS CK = 1, S = 0, R = 0 a HOLD STATE?
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
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Static CMOS D-Latch
Latch
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If CK = 1
Level-sensitive device
Positive Latch
S
Output follows input if
CLK high
LATCH
R
Negative Latch
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Output follows input if
CLK low
If CK = 0, HOLD
Q = CLK ⋅ Q + CLK ⋅ In
Penn ESE 570 Spring 2016 – Khanna
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
Static CMOS TG D-LATCH – 8 Transistors
updated 25Mar15
Static CMOS D-Latch
If CK = 1
S
LATCH
If CK = 0, HOLD
R
18 Transistors
CK
1
1
0
D
1
0
x
S'
0
1
0
R' Qn+1
1 1
0 0
0 Qn
Qn+1
0 SR-Set
1 SR-Reset
Qn SR-Hold
8 Transistors
**Transistor level implementation using transmission gates requires
fewer transistors
+ NO TOGGLE
+ NO NOT-ALLOWED INPUTS
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Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
Static CMOS TG D-LATCH
updated 25Mar15
Penn ESE 570 Spring 2016 – Khanna
40
Kenneth R. Laker,
University of
Pennsylvania,
Static CMOS TG D-LATCH
updated 25Mar15
CK
Q
D
CK
Q
CK
CK
When CK = 1 output Q = D, and tracks D until CK = 0, the D-Latch is
referred to positive level triggered.
When CK → 1 to 0, the Q = D is captured, held (or stored) in the Latch.
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
41
Penn ESE 570 Spring 2016 – Khanna
Kenneth R. Laker,
University of
Pennsylvania,
updated 25Mar15
42
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D-LATCH Timing Requirements
Ideas
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Synchronize circuits
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to external events (eg. Clk)
disciplined reuse of circuitry
Leads to clocked circuit discipline
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Uses state holding element (eg. Latches and registers)
Prevents
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Penn ESE 570 Spring 2016 – Khanna
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Timing assumptions
(More) complex reasoning about all possible timings
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Admin
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HW 7 due 3/31
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Design 8 bit adder
Extra Credit: Modify design for optimized delay (Submit
online before 4/8)
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Get up to 10 points added to your Midterm grade
NO LAYOUT
Penn ESE 570 Spring 2016 – Khanna
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