(Xilinx Answer 67256) - 40G/50G Ethernet Sub-System - 2016.1 - How can the core be targeted to Kintex UltraScale/ Kintex UltraScale+ devices The l_ethernet_v1_0.zip file contains an IP repository that can be used in Vivado 2016.1 with added support for Kintex UltraScale and Kintex UltraScale+ GTH devices. Use the following steps to add the IP repository to your project. Step 1: Unzip the l_ethernet_v1_0.zip file to your local drive. Step 2: Open Vivado 2016.1 and create a new project (note screen shots are from earlier repository steps done with Vivado 2014.2 and the Interlaken core, but still apply to Vivado 2016.1 and the 40/50G Ethernet core) Step 3: Click on “Create New Project” © Copyright 2016 Xilinx Step 4: Click “Next” Step 5: Type a project name and location, click “Next” © Copyright 2016 Xilinx Step 6: Click “Next” Step 7: Click “Next” © Copyright 2016 Xilinx Step 8: Click “Next” Step 9: Click “Next” © Copyright 2016 Xilinx Step 10: Select “Kintex UltraScale+” or “Kintex UltraScale”, “Package”, “Speed grade” etc, click “Next” Step 11: Click “Finish” © Copyright 2016 Xilinx Step 12: In the left pane, under “Project Manager”, click “IP Catalog” Step 13: In the “IP Catalog” window, right click and select “IP Settings” © Copyright 2016 Xilinx Step 14: In the “Project Settings” window, click “Repository Manager” and then click “Add Repository”, browse to the unzipped IP core folder “l_ethernet_v1_0” and click “Select” Step 15: Click “Apply” and “OK” © Copyright 2016 Xilinx Step 16: Type “40G” in the search window and you should be able to see the 40G/50G Ethernet Sybsystem IP core v1.0 Step 17: Double click on the IP core and you can configure the core and click “OK” © Copyright 2016 Xilinx Step 18: Click “Generate” © Copyright 2016 Xilinx Step 19: After the IP core is generated, you should see the below window, with a green check mark in the bottom “Design Runs” window for the core Step 20: In the “Sources” window, right click on the .xci file and click “Open IP Example Design” © Copyright 2016 Xilinx Step 21: This will open a new Vivado window with an example design. © Copyright 2016 Xilinx