Data Sheet
0.01 GHz to 10 GHz, GaAs, pHEMT, MMIC,
Low Noise Amplifier
HMC8410
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low noise figure: 1.1 dB typical
High gain: 19.5 dB typical
High output third-order intercept (IP3): 33 dBm typical
6-lead, 2 mm × 2 mm LFCSP package
HMC8410
RFIN/VGG1
RFOUT/VDD
14657-001
APPLICATIONS
Software defined radios
Electronics warfare
Radar applications
Figure 1.
GENERAL DESCRIPTION
The HMC8410 is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), pseudomorphic high
electron mobility transistor (pHEMT), low noise wideband
amplifier that operates from 0.01 GHz to 10 GHz. The HMC8410
provides a typical gain of 19.5 dB, a 1.1 dB typical noise figure,
and a typical output IP3 of 33 dBm, requiring only 65 mA from
a 5 V supply voltage. The saturated output power (PSAT) of up to
22.5 dBm enables the low noise amplifier (LNA) to function as a
local oscillator (LO) driver for many of Analog Devices, Inc.,
balanced, I/Q or image rejection mixers.
Rev. 0
The HMC8410 also features inputs/outputs (I/Os) that are
internally matched to 50 Ω, making it ideal for surface-mounted
technology (SMT)-based, high capacity microwave radio
applications.
The HMC8410 is housed in a RoHS-compliant, 2 mm × 2 mm,
LFCSP package.
Multifunction pin names may be referenced by their relevant
function only.
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Last Content Update: 08/30/2016
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HMC8410
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 12 General Description ......................................................................... 1 Applications Information .............................................................. 13 Revision History ............................................................................... 2 Recommended Bias Sequencing .............................................. 13 Electrical Specifications ................................................................... 3 Typical Application Circuit ....................................................... 13 0.01 GHz to 3 GHz Frequency Range ........................................ 3 Evaluation Board ............................................................................ 14 3 GHz to 8 GHz Frequency Range ............................................. 3 Evaluation Board Schematic ..................................................... 15 8 GHz to 10 GHz Frequency Range ........................................... 4 Outline Dimensions ....................................................................... 16 Absolute Maximum Ratings............................................................ 5 Ordering Guide .......................................................................... 16 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY
7/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
HMC8410
ELECTRICAL SPECIFICATIONS
0.01 GHz TO 3 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
NOISE FIGURE
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY CURRENT
SUPPLY VOLTAGE
Symbol
P1dB
PSAT
IP3
IDQ
VDD
Min
0.01
17.5
Typ
19.5
0.01
1.1
19.0
2
Max
3
1.6
Unit
GHz
dB
dB/°C
dB
15
24
dB
dB
21.0
22.5
33
65
5
dBm
dBm
dBm
mA
V
80
6
Test Conditions/Comments
Adjust VGG1 to achieve IDQ = 65 mA typical
3 GHz TO 8 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
NOISE FIGURE
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY CURRENT
SUPPLY VOLTAGE
Symbol
P1dB
PSAT
IP3
IDQ
VDD
Min
3
15.5
18.0
2
Typ
18
0.01
1.4
Max
8
1.9
Unit
GHz
dB
dB/°C
dB
12
12
dB
dB
21.0
22.5
31.5
65
5
dBm
dBm
dBm
mA
V
80
6
Rev. 0 | Page 3 of 16
Test Conditions/Comments
Adjust VGG1 to achieve IDQ = 65 mA typical
HMC8410
Data Sheet
8 GHz TO 10 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 3.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
NOISE FIGURE
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY CURRENT
SUPPLY VOLTAGE
Symbol
P1dB
PSAT
IP3
IDQ
VDD
Min
8
13
17.5
2
Typ
16
0.01
1.7
Max
10
2.2
Unit
GHz
dB
dB/°C
dB
6
10
dB
dB
19.5
21.5
33
65
5
dBm
dBm
dBm
mA
V
80
6
Rev. 0 | Page 4 of 16
Test Conditions/Comments
Adjust VGG1 to achieve IDQ = 65 mA typical
Data Sheet
HMC8410
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4.
Parameter1
Drain Bias Voltage (VDD)
Radio Frequency (RF) Input Power (RFIN)
Rating
7 V dc
20 dBm
Continuous Power Dissipation (PDISS), T = 85°C
(Derate 1.48 mW/°C above 85°C)
Channel Temperature
Storage Temperature Range
Operating Temperature Range
Thermal Resistance (Channel to Ground
Paddle)
Maximum Peak Reflow Temperature (MSL3)2
ESD Sensitivity
Human Body Model (HBM)
1.3 W
175°C
−65°C to +150°C
−40°C to +85°C
67.73°C/W
ESD CAUTION
260°C
Class1B Passed
500 V
When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the specification is listed.
For the full pin names of multifunction pins, refer to the Pin Configuration
and Function Descriptions section.
2
See the Ordering Guide section for more information.
1
Rev. 0 | Page 5 of 16
HMC8410
Data Sheet
GND 1
RFIN/VGG1 2
NIC 3
HMC8410
TOP VIEW
(Not to Scale)
6
NIC
5
RFOUT/VDD
4
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THIS PIN
MUST BE CONNECTED TO THE RF/DC GROUND.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF/DC GROUND.
14657-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
Mnemonic
GND
RFIN/VGG1
3, 4, 6
5
NIC
RFOUT/VDD
EPAD
Description
Ground. This pin must be connected to the RF/dc ground. See Figure 3 for the interface schematic.
RF Input (RFIN). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic.
Gate Bias of the Amplifier (VGG1). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface
schematic.
Not Internally Connected. This pin must be connected to the RF/dc ground.
RF Output (RFOUT). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic.
Drain Bias for Amplifier (VDD). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic.
Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
14657-005
GND
14657-003
RFOUT/VDD
Figure 3. GND Interface Schematic
14657-004
RFIN/VGG1
Figure 5. RFOUT/VDD Interface Schematic
Figure 4. RFIN/VGG1 Interface Schematic
Rev. 0 | Page 6 of 16
Data Sheet
HMC8410
TYPICAL PERFORMANCE CHARACTERISTICS
25
22
–40°C
+25°C
+85°C
20
15
10
18
GAIN (dB)
5
0
–5
16
14
–10
12
–15
–20
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
8
0
0
OUTPUT RETURN LOSS (dB)
–4
INPUT RETURN LOSS (dB)
6
8
10
Figure 9. Gain vs. Frequency for Various Temperatures
–40°C
+25°C
+85°C
–2
4
FREQUENCY(GHz)
Figure 6. Gain and Return Loss vs. Frequency
0
2
14657-009
–30
10
S21
S11
S22
–25
14657-006
GAIN (dB) AND RETURN LOSS (dB)
20
–6
–8
–10
–12
–14
–16
–40°C
+25°C
+85°C
–5
–10
–15
–20
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
Figure 7. Input Return Loss vs. Frequency for Various Temperatures
4.0
–25
14657-007
–20
2
3
4
5
6
7
8
9
10
Figure 10. Output Return Loss vs. Frequency for Various Temperatures
15
–40°C
+25°C
+85°C
12
NOISE FIGURE (dB)
3.0
2.5
2.0
1.5
9
6
1.0
3
0
0
2
4
6
8
10
FREQUENCY (GHz)
0
0
0.2
0.4
0.6
0.8
1.0
FREQUENCY (GHz)
Figure 8. Noise Figure vs. Frequency for Various Temperatures
Figure 11. Noise Figure vs. Frequency for Various Temperatures,
10 MHz to 1 GHz
Rev. 0 | Page 7 of 16
14657-011
0.5
14657-008
NOISE FIGURE (dB)
1
FREQUENCY (GHz)
–40°C
+25°C
+85°C
3.5
0
14657-010
–18
HMC8410
25
Data Sheet
50
–40°C
+25°C
+85°C
24
45
23
OUTPUT IP2 (dBm)
P1dB (dBm)
22
21
20
19
18
17
40
35
30
25
0
2
4
6
8
10
FREQUENCY (GHz)
20
14657-012
15
0
2
4
6
8
10
FREQUENCY (GHz)
Figure 12. P1dB vs. Frequency for Various Temperatures
14657-015
16
Figure 15. Output IP2 vs. Frequency at POUT/Tone = 5 dBm
25
0
–40°C
+25°C
+85°C
24
–5
REVERSE ISOLATION (dB)
23
PSAT (dBm)
22
21
20
19
18
–10
–15
–20
–25
17
2
4
6
8
10
FREQUENCY (GHz)
–35
2
3
4
5
6
7
8
9
10
Figure 16. Reverse Isolation vs. Frequency for Various Temperatures
36
34
34
32
32
OUTPUT IP3 (dBm)
36
30
28
26
24
22
30
28
26
24
22
0
20
2
4
6
8
10
FREQUENCY GHz)
18
0dBm
5dBm
0
2
4
6
8
10
FREQUENCY (GHz)
Figure 14. Output IP3 vs. Frequency for Various Temperatures,
Output Power (POUT)/Tone = 5 dBm
Figure 17. Output IP3 vs. Frequency for Various POUT/Tone
Rev. 0 | Page 8 of 16
14657-017
–40°C
+25°C
+85°C
20
14657-014
OUTPUT IP3 (dBm)
1
FREQUENCY (GHz)
Figure 13. PSAT vs. Frequency for Various Temperatures
18
0
14657-016
0
14657-013
15
–30
–40°C
+25°C
+85°C
16
Data Sheet
HMC8410
40
55
PAE
PSAT
35
PSAT (dBm) AND PAE (%)
45
30
25
20
0
0.2
35
30
25
20
15
5
0.4
0.6
0.8
1.0
FREQUENCY (GHz)
0
0
2
Figure 18. Gain, P1dB, PSAT, and Output IP3 vs. Frequency
0.6
POWER DISSIPATION (W)
10
25
20
15
10
0.4
0.3
0.2
2
4
6
8
10
FREQUENCY (GHz)
0
–10
14657-019
0
40
35
–4
–2
0
2
4
6
8
10
22
95
20
20
75
15
70
10
65
5
60
0
–10
–5
0
INPUT POWER (dBm)
5
55
10
GAIN (dB)
80
16
14
12
10
14657-020
25
IDD (mA)
18
85
14
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
90
30
12
Figure 22. Power Dissipation at 85°C vs. Input Power at Various Frequencies
100
POUT
GAIN
PAE
IDD
–6
INPUT POWER (dBm)
Figure 19. P1dB and Power Added Efficiency (PAE) vs. Frequency
45
–8
14657-022
0.1
Figure 20. POUT, Gain, PAE, and Supply Current with RF Applied (IDD) vs.
Input Power (Performance Below 100 MHz Is Limited by the Bias Network and
Does Not Reflect True Device Performance)
Rev. 0 | Page 9 of 16
8
0
2
4
6
FREQUENCY (GHz)
8
10
14657-023
P1dB (dBm) AND PAE (%)
0.5
5
POUT (dBm), GAIN (dB), AND PAE (%)
8
1GHz
3GHz
5GHz
7GHz
9GHz
PAE
P1dB
30
0
6
Figure 21. PSAT and PAE vs. Frequency
40
35
4
FREQUENCY (GHz)
14657-021
10
40
10
GAIN
P1dB
PSAT
OUTPUT IP3
15
14657-018
GAIN (dB), P1dB (dBm), PSAT (dBm),
AND OUTPUT IP3 (dBm)
50
Figure 23. Gain vs. Frequency for Various Supply Currents, VDD = 5 V
HMC8410
Data Sheet
7
5mA
25mA
45mA
70mA
5mA
15mA
25mA
35m
40
4
3
2
30
25
2
4
6
8
10
FREQUENCY (GHz)
15
Figure 24. Noise Figure vs. Frequency for Various Supply Currents (IDQ),
VDD = 5 V
0
2
4
6
8
Figure 27. Output IP3 vs. Frequency for Various Supply Currents (IDQ),
POUT/Tone = 5 dBm, VDD = 5 V
25
22
2V
3V
4V
5V
6V
7V
20
20
18
GAIN (dB)
15
10
10
FREQUENCY (GHz)
14657-027
0
14657-024
0
35
20
1
P1dB (dBm)
45mA
65mA
70mA
75mA
5
OUTPUT IP3 (dBm)
NOISE FIGURE (dB)
6
45
15mA
35mA
65mA
75mA
16
14
12
2
10
4
6
8
10
FREQUENCY (GHz)
Figure 25. P1dB vs. Frequency for Various Supply Currents (IDQ), VDD = 5 V
2
4
6
8
24
3.5
2V
3V
4V
5V
6V
7V
3.0
NOISE FIGURE (dB)
22
21
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
19
0
2.5
2.0
1.5
1.0
0.5
2
4
6
FREQUENCY (GHz)
8
10
0
14657-026
20
10
Figure 28. Gain vs. Frequency for Various Supply Voltages, IDQ = 65 mA
4.0
18
0
FREQUENCY (GHz)
25
23
PSAT (dBm)
8
14657-028
0
15mA
35mA
65mA
75mA
Figure 26. PSAT vs. Frequency for Various Supply Currents (IDQ), VDD = 5 V
0
2
4
6
FREQUENCY (GHz)
8
10
14657-129
0
5mA
25mA
45mA
70mA
14657-025
5
Figure 29. Noise Figure vs. Frequency for Various Supply Voltages, IDQ = 65 mA
Rev. 0 | Page 10 of 16
Data Sheet
HMC8410
90
24
80
22
70
20
IDD (mA)
16
40
30
2V
3V
4V
5V
6V
7V
12
0
20
10
2
4
6
8
10
FREQUENCY (GHz)
0
–0.90 –0.85 –0.80 –0.75 –0.70 –0.65 –0.60 –0.55 –0.50 –0.45
VGG1 (V)
Figure 30. P1dB vs. Frequency for Various Supply Voltages, IDQ = 65 mA
14657-133
14
10
50
14657-130
P1dB (dBm)
60
18
Figure 33. Supply Current with RF Applied (IDD) vs. VGG1, VDD = 5 V,
Representative of a Typical Device
27
120
25
100
23
2V
3V
4V
5V
6V
7V
15
0
20
2
4
6
8
10
FREQUENCY (GHz)
0
–10
45
0
5
10
20
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
80mA
18
16
GAIN (dB)
35
30
15
Figure 34. Supply Current with RF Applied (IDD) vs. Input Power for
Various Supply Currents (IDQ), VDD = 5 V
2V
3V
4V
5V
6V
7V
40
–5
INPUT POWER (dBm)
Figure 31. PSAT vs. Frequency for Various Supply Voltages, IDQ = 65 mA
14
12
25
10
20
0
2
4
6
8
10
FREQUENCY (GHz)
Figure 32. Output IP3 vs. Frequency for Various Supply Voltages,
POUT/Tone = 5 dBm
6
–10
–5
0
5
INPUT POWER (dBm)
10
15
14657-135
15
8
14657-132
OUTPUT IP3 (dBm)
5mA
25mA
45mA
70mA
80mA
15mA
35mA
65mA
75mA
40
17
13
60
14657-134
IDD (mA)
19
14657-131
PSAT (dBm)
80
21
Figure 35. Gain vs. Input Power for Various Supply Currents (IDQ) at 5 GHz,
VDD = 5 V
Rev. 0 | Page 11 of 16
HMC8410
Data Sheet
THEORY OF OPERATION
The HMC8410 is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), pseudomorphic (pHEMT),
low noise wideband amplifier.
The cascode amplifier uses a fundamental cell of two field effect
transistors (FETs) in series, source to drain. The basic schematic
for the cascode cell is shown in Figure 36, which forms a low
noise amplifier operating from 0.01 GHz to 10 GHz with
excellent noise figure performance.
VDD
RFOUT
The HMC8410 has single-ended input and output ports whose
impedances are nominally equal to 50 Ω over the 0.01 GHz to
10 GHz frequency range. Consequently, it can directly insert
into a 50 Ω system with no required impedance matching
circuitry, which also means that multiple HMC8410 amplifiers
can be cascaded back to back without the need for external
matching circuitry.
The input and output impedances are sufficiently stable vs.
variations in temperature and supply voltage that no impedance
matching compensation is required.
Note that it is critical to supply very low inductance ground
connections to the ground pins as well as to the backside
exposed paddle to ensure stable operation.
VGG1
14657-029
RFIN
Figure 36. Basic Schematic for the Cascode Cell
To achieve optimal performance from the HMC8410 and prevent
damage to the device, do not exceed the absolute maximum
ratings.
Rev. 0 | Page 12 of 16
Data Sheet
HMC8410
APPLICATIONS INFORMATION
During Power-Down
Figure 37 shows the basic connections for operating the
HMC8410. AC couple the input and output of the HMC8410
with appropriately sized capacitors. DC block capacitors and RF
choke inductors are supplied on the RFIN and RFOUT pins of
the HMC8410 evaluation board. See Table 6 for additional
information. These dc block capacitors and RF choke inductors
form wideband bias tees on the input and output ports to provide
both ac coupling and the necessary supply voltages to the RFIN
and RFOUT pins. A 5 V dc bias is supplied to the amplifier
through the choke inductor connected to the RFOUT pin, and
the negative VGG1 voltage is supplied to the RFIN pin through
the choke inductor.
The recommended bias sequence during power-down for the
HMC8410 follows:
1.
2.
3.
4.
The bias conditions previously listed (VDD = 5 V and IDQ =
65 mA) are the recommended operating points to achieve
optimum performance. The data used in this data sheet was
taken with the recommended bias conditions. When using the
HMC8410 with different bias conditions, different performance
than what is shown in the Typical Performance Characteristics
section may result.
RECOMMENDED BIAS SEQUENCING
To not damage the amplifier, follow the recommended bias
sequencing.
Figure 18, Figure 30, and Figure 31 show that increasing the
voltage from 2 V to 7 V typically increases P1dB and PSAT at the
expense of power consumption with minor degradation on
noise figure (NF).
During Power-Up
The recommended bias sequence during power-up for the
HMC8410 follows:
1.
2.
3.
4.
5.
Turn off the RF signal.
Decrease VGG1 to −2 V to achieve a typical IDQ = 0 mA.
Decrease VDD to 0 V.
Increase VGG1 to 0 V.
Connect to GND.
Set VGG1 to −2 V.
Set VDD to +5 V.
Increase VGG1 to achieve a typical supply current (IDQ) =
65 mA.
Apply the RF signal.
TYPICAL APPLICATION CIRCUIT
VGG1
+
C13
4.7µF
VDD
C6
10nF
C4
20pF
C6
10nF
L2
590nH
C4
20pF
HMC8410
RFIN/VGG1
J1
1
6
2
5
3
4
L2
590nH
RFOUT
J2
PACKAGE
BASE
GND
Figure 37. Typical Application Circuit
Rev. 0 | Page 13 of 16
14657-030
R2
15Ω
+
C13
4.7µF
HMC8410
Data Sheet
EVALUATION BOARD
The HMC8410 evaluation board is a 4-layer board fabricated
using a Rogers 4350 and the best practices for high frequency
RF design. The RF input and RF output traces have a 50 Ω
characteristic impedance.
The HMC8410 evaluation board and populated components
operate over the −40°C to +85°C ambient temperature range.
For proper bias sequence, see the Applications Information
section.
14657-031
The HMC8410 evaluation board schematic is shown in Figure 39.
A fully populated and tested evaluation printed circuit board
(PCB) is available from Analog Devices, Inc., upon request
(see Figure 38).
Figure 38. HMC8410 Evaluation PCB
Rev. 0 | Page 14 of 16
Data Sheet
HMC8410
EVALUATION BOARD SCHEMATIC
VGG1
C12
DNI
C13
100nF
C14
+ 4.7µF
VDD
J8
R2
15Ω
C4
100nF
C3
DNI
R1
0Ω
C15
20pF
C5
2.2µF
J3
C16
20pF
L1
590nH
RFIN
GND
RFIN/VGG1
J1
C1
10nF
NIC
HMC8410
1
6
2
5
EPAD
3
4
L2
590nH
NIC
RFOUT
RFOUT/VDD
J2
C2
10nF
NIC
VGG2
C6
DNI
C7
DNI
C8
DNI
J5
DNI
THRU CAL
J6
C9
C10
DNI
DNI
DNI
J7
DNI
14657-032
GND
J4
Figure 39. HMC8410 Evaluation Board Schematic
Table 6. Bill of Materials for Evaluation PCB EV1HMC8410LP2F
Item
J1, J2
J3, J4, J8
C1, C2
C3, C6 to C10, C12, J5 to J7
C4, C13
C5
C14
C15, C16
L1, L2
R1
R2
U1
Heat sink
PCB
Description
PCB mount SMA RF connectors, SRI 21-146-1000-01
DC bias test points
Capacitors, broadband, 10 nF and 82 pF, 0502, 160 kHz and 40 GHz; Presidio Components MBB0502X103MLP5N8L
Do not install (DNI)
Capacitors, ceramic, 100 nF, 0402 package
Capacitor, tantalum, 2.2 μF, Size A
Capacitor, tantalum, 4.7 μF, 3216 package
Capacitors, ceramic, 20 pF, 0402 package
Inductors, 590 nH, 0402, 5%, ferrite DF, Coilcraft 0402DF-591XJRU
0 Ω resistor
15 Ω resistor, 0402 package
Amplifier, HMC8410
Heat sink
600-01660-00 evaluation PCB; circuit board material: Rogers 4350
Rev. 0 | Page 15 of 16
HMC8410
Data Sheet
OUTLINE DIMENSIONS
1.65
1.60
1.55
6
4
PIN 1 INDEX
AREA
1.05
1.00
0.95
EXPOSED
PAD
0.25
BSC
TOP VIEW
PKG-005040
0.90
0.85
0.80
SEATING
PLANE
SIDE VIEW
0.35
0.30
0.25
0.30
0.25
0.20
3
0.05 MAX
0.02 NOM
COPLANARITY
0.08
1
PIN 1
INDICATOR
(0.20 × °45)
BOTTOM VIEW
0.65 BSC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.203 REF
10-27-2015-A
2.05
2.00 SQ
1.95
Figure 40. 6-Lead Lead Frame Chip Scale Package [LFCSP],
2 mm × 2 mm Body and 0.85 mm Package Height
(CP-6-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
HMC8410LP2FE
Temperature Range
−40°C to +85°C
MSL Rating2
MSL3
Lead Finish
100% Matte Sn
Package Description
6-Lead LFCSP
Package Option
CP-6-9
HMC8410LP2FETR
−40°C to +85°C
MSL3
100% Matte Sn
6-Lead LFCSP
CP-6-9
EV1HMC8410LP2F
1
2
3
Evaluation PCB
The HMC8410LP2FE and HMC8410LP2FETR are RoHS Compliant Parts.
See the Absolute Maximum Ratings section for additional information.
XXX is the three digit lot number.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14657-0-7/16(0)
Rev. 0 | Page 16 of 16
Branding3
8410
XXXX
8410
XXXX