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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 6, NOVEMBER 2004
Critical Bandwidth for the Load Transient
Response of Voltage Regulator Modules
Kaiwei Yao, Senior Member, IEEE, Yuancheng Ren, and Fred C. Lee, Fellow, IEEE
Abstract—This paper investigates the relationship between the
control bandwidth and the load transient response in voltage regulator modules (VRMs), which are designed with multiphase interleaving synchronous buck converters. Both voltage- and currentmode controls are discussed. A critical bandwidth value is discovered, beyond which pushing the bandwidth can no longer reduce
the output voltage spike during the load transient response. Also,
the critical bandwidths are different according to different kinds
of output capacitors. The critical bandwidth concept highlights the
trend of high-frequency VRM design that uses ceramic capacitors
to achieve smaller size and faster load transient response. Simulation and experimental results prove the theoretical analysis.
Index Terms—Load transient analysis, synchronous buck converter, voltage regulator.
I. INTRODUCTION
I
T IS perceived that Moore’s Law will prevail at least for
the next decade with the continuous advancement of processing technologies for integrated circuits. According to Intel’s
roadmap, by the year 2010, over one billion transistors will be
integrated in one processor; the processor’s clock speed will
approach 15 GHz; the core static currents will increase up to
200 A; the dynamic current slew rate will rise up to 120 A/ns;
and the core voltage will decrease to 0.8 V [1], [2]. The rapid
advancement of processor technology has posed stringent challenges to the design of a voltage regulator module (VRM), the
special power supply for the microprocessor.
One pressing issue is dynamic voltage regulation during
the fast load transient change. The VRM must maintain a
low output voltage within a tight tolerance range during the
operation, which includes a large current step change and high
slew rate. For example, Intel’s specification VRM 9.1
% steady-state regulation accuracy and less
[3] requires a
than 108-mV output voltage spike for an 82-A load current
step change. The slew rate of the processor load at the socket
is 450 A/ s. Many output capacitors have already been used
for current VRM design in order to limit the voltage spikes
that occur during the load transient period. Increasing the
number of capacitors to meet the more stringent load transient
Manuscript received August 20, 2003; revised March 17, 2004. This work was
presented at the PESC’02 Conference, Cairns, Australia, June 23-27. This work
was supported by Intel, Texas Instruments, National Semiconductors, Intersil,
TDK, Hitachi, Hipro, Power-One, Delta Electronics, ERC shared facilities, and
the National Science Foundation under Award EEC-9731677. Recommended
by Associate Editor F. Blaabjerg.
The authors are with the Center for Power Electronics Systems, The Bradley
Department of Electrical and Computer Engineering, Virginia Polytechnic
Institute and State University, Blacksburg, VA 24061-0179 USA (e-mail:
kyao@vt.edu).
Digital Object Identifier 10.1109/TPEL.2004.836669
requirement for the future VRM design is no longer a suitable
solution because of size and cost issues.
As a result, a lot of research has gone into VRM load transient analysis [4]–[12] to determine the best way to minimize the
number of output capacitors. However, no paper has considered
the relationship between control bandwidth and the load transient response. It is just assumed that the higher the bandwidth,
the faster the load transient response. And all of the analysis for
the transient voltage spike is based on an ideal control in which
the bandwidth is so high that the duty cycle is saturated during
the load transient period.
This paper investigates the relationship between the control
bandwidth and the voltage spike for both the voltage- and current-mode controls during the load transient change. Also, it derives the bandwidth value that will saturate the duty cycle in the
load transient period. Section II studies the fundamental reason
for the transient voltage spikes. With the help of the average
small-signal models, Section III establishes the relationship between the transient voltage spike values and the control bandwidths. A critical bandwidth value is derived, beyond which
pushing the bandwidth can no longer reduce the output voltage
spike during the transient response. Section IV discusses the validity of the small-signal analysis method, and the critical inductance concept is introduced. Finally, in Section V the simulation
and experimental results are shown to prove all of the theoretical analyses.
II. TRANSIENT VOLTAGE SPIKE ANALYSIS
Currently, the multiphase interleaving synchronous buck converter is widely used in the design of VRMs in order to support the
low voltage and high current [13]. Instead of using a single synchronous buck converter with many devices in parallel, we can
separate these devices to form many “baby” converters and use
these paralleled converters to perform the same function. Then
we can phase-shift the control signals (360 divided by phase
number) of these miniaturized converters to reduce the input and
output current ripples. However, this interleaving effect does not
change the average small-signal model of the entire circuit because interleaving only changes the ripple values and there is no
ripple information in the average model. Additional supporting
analysis can be found in other work [14], [15], which shows that
the average small-signal model of a single synchronous buck converter can be used to analyze the multiphase case.
Fig. 1 shows a synchronous buck converter with a closed-loop
design. For a 12 V-input VRM, since the output filter inductor current increases faster than it decreases, the transient during stepdown is worse than during step-up. As a result, only the step-down
transient is analyzed here. For simplicity, the delay effect in the
0885-8993/04$20.00 © 2004 IEEE
YAO et al.: CRITICAL BANDWIDTH
Fig. 1.
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Synchronous buck converter with a closed control loop.
Fig. 3. Small-signal blocks: (a) voltage-mode control and (b) current-mode
control.
transient voltage spike according to (1). So if the relationship can
be developed between the control bandwidth and the inductor average current during the transient period, it is easy to investigate
the relationship between the transient voltage spike and the control bandwidth. The next section will accomplish this goal based
on the average small-signal model.
III. SMALL-SIGNAL MODEL ANALYSIS
Fig. 2.
Key current waveforms during the step-down transient.
control loop is ignored. Since the load current slew rate of the microprocessor is much higher than the output filter inductor current
slew rate (for example, 450 A/ s for a Pentium 4) [3], the load current transient is simply discussed as an ideal step change.
Fig. 2 shows the reason for the output voltage spike that occurs during the load step-down transient. Since the output filter
inductor current cannot follow the fast-changing load current
, some extra current goes through both the output capacand its equivalent series resistance (ESR). The capacitor
charge variation and the
voltage drop combine to
itor
form the output voltage spike that occurs in the transient period.
Here, the equivalent series inductor (ESL) of the bulk output
capacitor is not considered, since the high-frequency ceramic
capacitors in parallel will eliminate the di/dt effect. The output
voltage waveform during the step-down transient can be calculated as
(1)
Fig. 2 shows the inductor current falling-time period from the
goes to negafull load current to the light load current. After
tive andtheoutputvoltage continuesdecreasing.Asaresult,the
voltage spike happens only in the period. The inductor current
information obtained during the period can be used to calculate
the transient voltage spike. To further simplify the analysis, the
current ripples can be ignored. The inductor average current information during the transient period can be used to analyze the
Fig. 3 shows the small-signal block of the synchronous buck
converter with voltage- and current-mode controls that follows
is the power stage
the feedback-control model [16], [17].
open-loop output impedance.
is the transfer function of
to the duty cycle d.
is the transfer funcoutput voltage
is the transfer
tion of inductor current to load current .
repfunction of the inductor current to the duty cycle d.
resents the comparator effect.
is the current loop compenis the voltage loop compensator
sator transfer function, and
transfer function. The compensator designs here just follow the
classic methods outlined in previous work [16], [17].
In the voltage-mode control, the control loop is defined as
(2)
In the current-mode control, the voltage loop is the same as (2).
The current loop is defined as
(3)
Current-mode control is a multiloop control system. The
power stage with current loop closed can be defined as a
function block, and then the entire system can be treated as a
single-loop control system. The measured system loop gain
outside of the closed current loop is referred to as the outer
loop gain [16], as
(4)
In the small-signal blocks, the current transfer function
represents the relationship between the inductor current and the
load current in the open-loop condition, as
(5)
(6)
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 6, NOVEMBER 2004
where
is the ESR zero of the output capacitor,
is the
power stage double pole, and Q represents the damping effect
in the
in the second-order system because of the resistance
power stage. The ESR of the inductor, the trace resistance, and
the turn-on resistance of the power MOSFETs all contribute to
[17].
With a closed voltage loop, the closed-loop current transfer
function can be derived from the small-signal block diagram of
the system in Fig. 3(a)
(7)
With both the current and voltage loops closed, the closedloop current transfer function can be derived from the smallsignal block diagram of the system in Fig. 3(b), as
(8)
Further mathematic analysis can simplify (7) and (8) as
(9)
(10)
where is the crossover frequency of the control loop; i.e., it is
the voltage loop in voltage-mode control, but is the outer loop in
is half of the switching frequency.
current-mode control. The
In the frequency domain, the normalized load current with
step change can be expressed as
Fig. 4. Voltage-mode control: (a) current transfer function
response inductor current (bottom).
G
(s) and (b) step
G
(s) and (b) step
(11)
Based on all the information in the frequency domain, the average inductor current waveform in the transient period, which
is in the time domain, can be easily derived using an inverse
Laplace transformation.
Fig. 4 shows the current transfer function and the step
response inductor current with voltage-mode control. In the
open loop, the inductor current responds to the load current
step change as a second-order system, in which the oscillation
frequency is the power stage double pole. With the loop closed,
the oscillation frequency is modified to the level of the control
bandwidth, which is much faster than the condition in the
open loop. The inductor current rising time is approximately
a quarter of the oscillation period. Thus, the average inductor
current during the step-down transient is about
(12)
.
where
Fig. 5 shows the current transfer function and the step response inductor current with peak-current-mode control. The
inductor current with closed loop responds to the load current
step change as a first-order system, in which the time constant
is the outer-loop control bandwidth. The average inductor current during transient is approximately
(13)
Fig. 5. Current-mode control: (a) current transfer function
response inductor current.
Now, the relationship between the control bandwidth and the
inductor current in the transient period is shown in (12) and (13).
Since the current through the output capacitor is the same as the
inductor current during the transient period, it is easy to derive
the output voltage spike by calculating the maximum value of
YAO et al.: CRITICAL BANDWIDTH
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Fig. 8. Relationship between the bandwidth and the transient voltage spike:
(a) voltage-mode control and (b) current-mode control.
Fig. 6. Transient waveforms with voltage-mode control: (a)
.
(b)
f f
f <f
and
The transient voltage spike is
(17)
Fig. 8 shows the relationship between the bandwidth and the
voltage spike in the transient response. In the low-frequency
range, the higher the bandwidth, the smaller the transient voltage
spikes. However, the ESR of the output capacitor limits the
voltage spike when the bandwidth is higher than the critical
value.
It is much easier to understand the critical bandwidth based on
the output impedance consideration. Following the analysis in
[16], [17], the open-loop output impedance of the synchronous
buck converter is
Fig. 7.
(b)
Transient waveforms with current-mode control: (a)
.
f f
f <f
and
(18)
(1). It is very interesting that there exists a critical bandwidth for
both voltage- and current-mode controls. With a low-bandwidth
design, the maximum transient voltage is reached at some point
after the load step change. This means that the control of the
power stage determines the value of the transient voltage spike.
When the bandwidth is higher than the critical value, the maximum transient voltage always occurs at the same time as the
load step change. The ESR of the output capacitor determines
the voltage spike. Figs. 6 and 7 show the calculated voltage transient waveforms (the voltage value is normalized to the output
voltage) in both the voltage-mode and current-mode controls.
The waveforms are only effective within the inductor-currentfalling periods.
For voltage-mode control, the critical bandwidth is
(14)
The transient voltage spike is
where
includes the dc resistance of the inductor L, the conduction resistance
of the MOSFETs, and the parasitic
.
resistance of the traces, and
For the current-mode control, a high-bandwidth current-loop
design can simplify the synchronous buck converter from a
two-order system to a one-order system. When the current loop
is closed and the voltage loop is open, the synchronous buck
converter operates as an ideal current source, and its output
impedance can be approximately represented as
(19)
When the voltage loop is closed, the closed-loop output
impedance can be derived from the small-signal block diagram
of the system in Fig. 3, as
for voltage-mode control
(20)
for current-mode control
(21)
(15)
For current-mode control, the critical bandwidth is
(16)
Fig. 9 shows the relationship between the control bandwidth
and the closed-loop output impedance for the current-mode
, the corner frequency
control. For the output impedance
, which is right at the
is just at the capacitor ESR zero
critical bandwidth. Continuously pushing the bandwidth higher
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 6, NOVEMBER 2004
(a)
(b)
Fig. 9. Closed-loop output impedance with the current-mode control: (a) !
reduces the output impedance maximum value when the bandwidth is within the critical bandwidth range. However, beyond
the critical bandwidth, the loop gain can no longer attenuate
the impedance in the high-frequency range, which is the ESR
value of the output capacitor. As a result, the transient voltage
spike is determined by the output capacitor ESR voltage drop.
The voltage-mode control follows the same principle. But
since there is a double pole in the open-loop output impedance,
the critical bandwidth needs to be higher than the ESR zero
so that the loop gain can sufficiently attenuate the impedance
within the control bandwidth. But the critical bandwidth value
in (14) cannot be easily seen using the closed-loop output
impedance analysis.
IV. CRITICAL INDUCTANCE DESIGN
The preceding analysis is based on the small-signal models.
If the duty cycle is saturated, the closed-loop current transfer
function can no longer be used for transient analysis. Instead, the
output filter inductance determines the inductor current during
the transient period. The inductor current slew rates during the
step-up and step-down are
(22)
(23)
According to (12) and (13), the small-signal model analysis
also determines an inductor current slew rate during the transient. For voltage-mode control
(24)
For current-mode control
(25)
(26)
However, the maximum inductor current slew rates derived
from the small-signal models in (24) and (26) cannot exceed the
Faraday Law limitations given in (22) and (23). Larger values
from (20) and (22) mean that the duty cycles are saturated and
the small-signal model is no longer valid. The equivalent points
give a critical inductance value. For voltage-mode control
(27)
<!
(c)
, (b) !
=!
, and (c) !
>!
.
For current-mode control
(28)
For the 12 V-input VRMs, D is smaller than (1-D). As a result,
(27) and (28) can be further simplified as
(29)
(30)
The critical inductance concept reveals the point at which the
duty cycle will go to saturation in a closed-loop controlled converter. The crossover frequency determines the critical inductance value. More detailed analysis is provided in other work
[18].
Also, the preceding analysis shows that both the control
bandwidth and the inductance impact the speed of the inductor
current transient response. With the inductance designed to be
smaller than the critical value, the control bandwidth determines the effect. But for an inductance design that is larger than
the critical value, the same control bandwidth is over-designed,
and the inductor itself determines its current transient response
speed. For each inductance design, an effective control bandwidth can be derived from (29), as
(31)
Any bandwidth design beyond this value saturates the duty
cycle but cannot improve the transient response speed.
Assuming that the bandwidth design is always higher than
the effective value obtained in (31) for different inductance designs, (31) can be substituted into (15), which yields the following relationship between the transient voltage spike and the
inductance:
(32)
where
(33)
It is clear that reducing the inductance below a certain value
can no longer help to reduce the transient voltage spike.
YAO et al.: CRITICAL BANDWIDTH
Fig. 10.
f
=
Transient voltage spikes with voltage-mode control. (Top)
12:5 KHz. (Middle) f = f
= 25 KHz. (Bottom) f = 37:5 KHz.
This analysis shows that for the critical bandwidth design, the
relative critical inductance value is a good design point in terms
of both the transient response speed and the efficiency. There is
no need to further reduce the inductance or to push the bandwidth. Of cause, a certain design margin should be considered
in real VRM applications.
V. SIMULATION AND EXPERIMENTAL RESULTS
Pspice software is used to simulate a two-phase interleaving synchronous buck converter with both voltage- and
current-mode controls. The dc-dc conversion is from 12 to
1.5 V with 25-A full load current. The switching frequency of
each phase is 300 KHz. The output capacitor is modeled with
F and
m , which represents four Sanyo
Oscon capacitors (4SP820M) in parallel. The output filter choke
in each phase is 800 nH, which allows as high as 37.5 KHz
bandwidth for voltage-mode control and 24-KHz bandwidth for
current-mode control without duty cycle saturation, according
to (29) and (30).
Simulation results shown in Figs. 10 and 11 prove the existence of the critical bandwidth in both control methods. The
voltage ripple is not included in the voltage spikes. According
to (14) and (16), for the Oscon capacitor 4SP820M, the critical
bandwidth is 25 KHz in voltage-mode control and 16 KHz in
current-mode control. Bandwidths higher than the critical value
can no longer reduce the transient voltage spikes. The ESR of
the output capacitor and the step load current value determine
the transient voltage spike values, which are 75 mV.
A two-phase interleaving synchronous buck converter is developed to verify the results of the theoretical analysis. The design is the same as for the simulation case. The output capacitors
are four Sanyo Oscon capacitors (4SP820M) in parallel. The
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Fig. 11.
f
Transient voltage spikes with current-mode control. (Top)
= 16 KHz. (Bottom) f = 24 KHz.
= 10 KHz. (Middle) f = f
output filter choke in each phase is one DELTA DPF146-0R8
(800 nH).
Figs. 12 and 13 show the transient waveforms with
voltage-mode and current-mode controls. The experimental
results agree with the theoretical analysis. Because the output
interconnection resistor is also responsible for some of the
voltage drop that occurs in the transient period, the real voltage
spike limitation is slightly larger than the theoretical result
(75 mV).
The critical bandwidth is very useful for design. Table I lists
the critical bandwidth values with different kinds of capacitors,
the size of each capacitor, and the numbers required to meet
the VRM 9.1 standard. Currently, the Oscon capacitor is widely
used in VRM design. For this kind of capacitor, the critical bandwidths for both the voltage- and current-mode controls are relatively low. A switching frequency of 200–300 KHz is sufficient to achieve the critical bandwidth design. The ESRE series
capacitor from Cornell Dubilier has a much smaller size than
the Oscon capacitor. However, the switching frequency must
reach about 500 KHz to realize the critical bandwidth design.
For the ceramic capacitor, it is impossible to push the bandwidth
to the critical value; this design must follow the case in which
the bandwidth is lower than the critical value. For a specified
, the requirements of the output
voltage spike requirement
capacitance can be derived from (15) and (17).
For voltage-mode control
(34)
For current-mode control
(35)
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 6, NOVEMBER 2004
= 10 KHz, (b) f
=f
Fig. 12.
Transient voltage spikes with voltage-mode control: (a) f
Fig. 13.
Transient voltage spikes with current-mode control: (a) f = 8 KHz, (b) f = f
TABLE I
CRITICAL BANDWIDTH WITH DIFFERENT KINDS OF CAPACITORS
VI. CONCLUSION
The dynamic output voltage regulation during the fast load
transient changes is a severe challenge for VRM design. This
paper investigates the relationship between the control bandwidth and the output voltage spike during the load transient
change. A critical bandwidth is derived to facilitate the VRM
design. In the low-frequency range below the critical bandwidth,
the control bandwidth determines the transient voltage spike
value, and increasing the control bandwidth can reduce the transient voltage spike. However, pushing the control bandwidth
higher than the critical value is unhelpful because the transient
voltage drop across the ESR of the output capacitors dominates the transient voltage spike. Since the critical bandwidth
is related to the time constant of the output capacitors, the critical bandwidths are different for VRM designs with different
kinds of output capacitors. For VRM design, Oscon capacitors
are widely used, but their large ESR values yield critical bandwidths of around 20–30 KHz. Further increasing the switching
frequency for a higher control bandwidth offers little help for
further reducing capacitor numbers. The chance and trend for
the design of small, high-frequency VRMs depends on the use
of capacitors with smaller ESR values, such as ceramic capacitors.
= 25 KHz, and (c) f = 36 KHz.
= 16 KHz, and (c) f = 30 KHz.
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July 2002.
Kaiwei Yao (M’95–SM’04) received the B.S. degree
from Xi’an Jiaotong University, Xi’an, China in
1992, the M.S. degree from Zhejiang University,
Hangzhou, China in 1995, and the Ph.D. degree from
Virginia Polytechnic Institute and State University
(Virginia Tech), Blacksburg, 2004, all in electrical
engineering.
From 1995 to 1998, he was an Engineer for UPS
Design, Hwadar Electronics, Shenzhen, China. In
2003, he was Technical Coordinator at the Center
for Power Electronics Systems (CPES), Virginia
Tech. His research interests include power management, high-frequency
high-density power supplies, modeling and control for converters, design for
distribute-power systems, and power-factor-correction techniques.
Yuancheng Ren received the B.S. and M.S. degrees
in electrical engineering from Zhejiang University,
Hangzhou, China, in 1997 and 2000, respectively,
and is currently pursuing the Ph.D. degree in power
electronics at the Center for Power Electronics
Systems (CPES), Virginia Polytechnic Institute and
State University, Blacksburg.
His research interests include power management, high-frequency high-density power supplies,
modeling and control for converters, and design for
distribute-power systems.
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Fred C. Lee (S’72–M’74–SM’87–F’90) received
the B.S. degree in electrical engineering from the
National Cheng Kung University, Taiwan, R.O.C.,
in 1968 and the M.S. and Ph.D. degrees in electrical
engineering from Duke University, Durham, NC, in
1971 and 1974, respectively.
He is a University Distinguished Professor with
Virginia Polytechnic Institute and State University
(Virginia Tech), Blacksburg, and prior to that he was
the Lewis A. Hester Chair of Engineering at Virginia
Tech. He directs the Center for Power Electronics
Systems (CPES), a National Science Foundation engineering research center
whose participants include five universities and over 100 corporations. In
addition to Virginia Tech, participating CPES universities are the University
of Wisconsin-Madison, Rensselaer Polytechnic Institute, North Carolina A&T
State University, and the University of Puerto Rico-Mayaguez. He is also
the Founder and Director of the Virginia Power Electronics Center (VPEC),
one of the largest university-based power electronics research centers in
the country. VPEC’s Industry-University Partnership Program provides an
effective mechanism for technology transfer, and an opportunity for industries
to profit from VPEC’s research results. VPEC’s programs have been able to
attract world-renowned faculty and visiting professors to Virginia Tech who, in
turn, attract an excellent cadre of undergraduate and graduate students. Total
sponsored research funding secured by him over the last 20 years exceeds
$35 million. His research interests include high-frequency power conversion,
distributed power systems, space power systems, power factor correction
techniques, electronics packaging, high-frequency magnetics, device characterization, and modeling and control of converters. He holds 30 U.S. patents,
and has published over 175 journal articles in refereed journals and more than
400 technical papers in conference proceedings.
Dr. Lee received the Society of Automotive Engineering’s Ralph R. Teeter
Education Award (1985), Virginia Tech’s Alumni Award for Research Excellence (1990), and its College of Engineering Dean’s Award for Excellence in
Research (1997), in 1989, the William E. Newell Power Electronics Award, the
highest award presented by the IEEE Power Electronics Society for outstanding
achievement in the power electronics discipline, the Power Conversion and Intelligent Motion Award for Leadership in Power Electronics Education (1990),
the Arthur E. Fury Award for Leadership and Innovation in Advancing Power
Electronic Systems Technology (1998), the IEEE Millennium Medal, and honorary professorships from Shanghai University of Technology, Shanghai Railroad and Technology Institute, Nanjing Aeronautical Institute, Zhejiang University, and Tsinghua University. He is an active member in the professional
community of power electronics engineers. He chaired the 1995 International
Conference on Power Electronics and Drives Systems, which took place in Singapore, and co-chaired the 1994 International Power Electronics and Motion
Control Conference, held in Beijing. During 1993-1994, he served as President
of the IEEE Power Electronics Society and, before that, as Program Chair and
then Conference Chair of IEEE-sponsored power electronics specialist conferences.