Circuits, Devices, Microelectronics, and Networks
Textbook title: Circuits, Devices, Networks and Microelectronics
CHAPTER 13: DC-DC SWITCHING CONVERTERS
13.1 INTRODUCTION TO POWER CONVERTERS
Converters are the most common form of power electronics. A converter takes one form of electrical
power and converts it into another. AC-AC converters are the simplest. AC-AC conversion is
accomplished by inductive coupling for which the time-varying nature of AC power is well suited. ACAC converters also are the means to tap power from the power grid which accomplishes its task at 50Hz
or 60Hz frequencies over high-voltage transmission lines.
A cousin to this type of converter is the AC–to–DC converter. Conversion from the bipolar nature of AC
to the unipolar form of DC is accomplished through the artifact of diode rectifier circuits under such
categories as half–wave, full–wave, three-phase, etc.
Considerably more conversion versatility and efficiency can be accomplished by means of transistors as
high-speed switches. These are categorized as ‘switching power supplies’ and are most commonly
employed as DC-DC converters. They also find use as DC-AC converters, also identified as ‘inverters’.
Since the DC-DC switching technique is simple and straightforward and offers advantages in adaptability,
size, and efficiency, it is rapidly taking the lead over the older linear technologies.
The generic form of the switching converter is DC to DC, for which a unipolar, steady-state source level (
I1 ,V1 ) is converted to a unipolar steady-state load requirement (I2 ,V2 ). Assuming that it is lossless, then
I 1V1 = I 2V2
(13.1-1)
13.2 THE DC-DC DOWNCONVERTER
The assumption that a converter is lossless is a typical idealization caveat, but not unreasonable. The
basic converter topology is represented by figure 13.2–1 and consists of a series element and a shunt
element. For the direct converter these are switches and for proper operation must be complementary.
Figure 13.2–1(a) and (b): Basic topology. 12V – 9V example
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Figure 13.2–1(c): (I,V) waveforms for the 12V – 9V converter
The switching power supply relies on time-averages levels as defined by the duty cycles of its two
switches. The duty cycle DS of the series switch SW1 defines the average voltage level V2 transferred
from the source side to the load side. Switch SW2 keeps the current I2 flowing through the load when
switch 1 is off. For the converter represented by figure 13.2–1, switch #1 has a duty cycle DS = 0.75 and
switch #2 will therefore have complementary duty cycle (1 – DS) = 0.25.
V1 is assumed to be a steady levels of voltage. I2 is assumed to be a continued flow of current, as
afforded by SW2. The action of the switches and time-averaging then yields
V2 = V2 (t ) = D S V1
(13.2-2a)
I 1 = I SW 1 (t ) = D S I 2
(13.2-2b)
where x(t ) indicates time averaging. The variation in levels from the switching action are smoothed
over by use of capacitances and inductances. Note that equations (13.2-2a) and (13.2-2b) also obey the
lossless condition (equation (13.2-1)).
The switching is usually executed at sufficiently high frequencies so capacitance and inductances of
modest sizes can be used to smooth out the waveforms. Both of these elements are energy storage
elements, for which capacitances are used to store voltage (in the form Q/C), and smooth out the
voltage waveform. Inductances are used to store current and smooth out the current waveform.
The effects of these components in the circuit are realized by the definitions
dV =
I
dt
C
(13.2-3a)
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dI =
V
dt
L
(13.2-3b)
It should be no great revelation that the larger the values of C and L , the smaller the ripple.
Equation (13.2-3b) is also emphasizes that an emf (voltage) will be generated across the inductance with a
change in current. This effect is manifested by figure 13.2–2 for which an interruption of current flow
such as that caused by a switch induces an emf of magnitude that can easily break-over the switch gap. In
the early part of the century, when many unwary experimenters would hook up a DC induction motor to a
simple knife switch, a panicky yank on the switch to shut off the motor would create an enormous,
dangerous arc, usually sufficient to melt parts of the switch. In modern circuits, this effect merely
annihilates the switching transistor as the overvoltage surges well beyond junction
breakdown. For this reason, many circuits containing an inductance add a ”snubber” to shunt destructive
overvoltage spikes and arcs. Snubbers are even included in digital integrated circuits, since at high
switching speeds, the small inductances due to long interconnects may be sufficient to cause large
overvoltages.
Fi
gure 13.2–2: Induced voltages in an inductance due to current interruption.
This effect is of advantage in converter circuits because the opening of the controlled switch will induce
sufficient reactive voltage to turn on a reactive switch such as a diode. This action is illustrated by figure
13.2–3.
Figure 13.2–3: Inductive complementary switching by means of a diode.
As indicated by the figure the diode is pulled into forward bias by the emf induced across the inductance.
The diode will therefore serve as the complementary switch to that of the controlled switch (which usually
is a transistor)
A complete converter circuit might then be represented by figure 13.2–4, which represents the topology
which we usually call a direct converter.
Figure 13.2–4: The direct converter topology (down converter).
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The converter transfer action is defined by the switches. For the topology shown the input voltage is
stored on capacitance C and voltage V1 supplied to the switches = VC. The capacitance is discharged by a
current of magnitude I2 during the interval in which SW1 is on. It is supplied continuously by current I1
flowing from the input source, as represented by figure 13.2–5.
Figure 13.2–5: Charge and discharge current
The drop in voltage on the capacitance over the interval from 0 to DST is then
ΔVC = ΔV1 =
1
C
DS T
∫ (I
2
0
− I 1 )dt ≅
⎛
⎞
1
(I 2 − I 1 )DS T = 1 ⎜⎜1 − I 1 ⎟⎟(DS I 2 )T
C
C⎝
I2 ⎠
which is the same as
ΔVC = ΔV1 =
I1
(1 − DS )T
C
(13.2-4)
since DS x I2 = I1.
Equation (13.2–4) represents the decrement of VC during discharge or the magnitude of the ripple. Figure
13.2–5 illustrates the effect of the capacitance on average voltage V1.
Figure 13.2–6. Ripple on V1 (= VC ) .
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The amplitude of this ripple can also be evaluated by evaluating ΔVC when SW1 is open for which the
capacitance is charged up by a flow of current I1 onto the capacitance. This current causes an increment
of voltage across C of value
1
ΔVC = ΔV1 =
C
T
∫
I 1 dt =
DS T
I1
(1 − DS )T
C
(13.2–5)
and is the same as that of equation (13.2–4).
Which is expected and should be no surprise.
Similarly, a ripple in the current I2 will occur as the inductance discharges through the load while SW2 is
closed, i.e.
T
V
1
ΔI 2 =
V2 dt = 2 (1 − D S )T
LDT
L
∫
(13.2–6a)
S
This ripple will induce a corresponding ripple in V2, i.e.
ΔV2 = ΔI 2 × R2
(13.2–6b)
**********************************************************************************
EXAMPLE 13.2–1: The circuit of figure 13.2–7 shows a direct converter which is supplied by a source
of value VB = 26 V and internal resistance RB = 0.1Ω. RB also acts as the resistive component of the R-C
input filter. It is assumed that the load can be represented by R2 = 0.1Ω. It is switched by a clock at fs
=50 kHz.
(a) What are the converter values I2, V1, and I1 and what duty cycle DS is required.
(b) What values of L and C are needed to keep the current ripple at the output and the voltage
ripple of the input to less than 2%?
Figure 13.2–7: 26V–to–5V direct converter operating at fs = 50 kHz
SOLUTION: For V2 = 5V, we have: I2 = V2/R2 = 5/0.1 = 50 A.
Assuming V1 x I1 = V2 x I2 = 250 W, and I1 = ( 26 – V1 )/R1, we get the quadratic:
10V1(26 - V1) = 250
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which has solutions V1 = 25 and V1 = 1. Only the solution V1 = 25V makes sense since the other solution
is less than V2 (= 5V). For this value, we then get:
I1 = (26 – V1 )/R1 = 10A
The duty cycle DS is then: DS = V2 / V1 = 0.2
The ripple current at the output is, from equation (13.2–5),
ΔI 2 = .02 × 50 =
1
× 5.0 × (1 − 0.2) × 20 μs
L
from which the inductance needs to be (at least) L =
5.0 × 0.8 × 20u
0.02 × 50
= 80μH
Similarly, from equation (13.2–4)
ΔV1 = .02 × 25 =
1
× 10 × (1 − 0.2) × 20 μs
C
from which the capacitance will need to be (at least) C =
10 × 0.8 × 20u
= 320μF
0.02 × 25
**********************************************************************************
The topology of figure 13.2–4 in general will end up with the quadratic equation
V1 (V B − V1 ) = PL R B
which has solution
V1 =
VB
2
⎛
⎜1 + 1 − 4 PL R B
⎜
V B2
⎝
⎞
⎟
⎟
⎠
(13.2–8)
where only the positive root is valid, required in order that V1 > V2.
13.3 THE DC-DC UPCONVERTER
The topology represented by figure 13.3–4 is also called the down converter or buck converter, since it
”bucks” the voltage down to a lower output level. It has a sister topology that uses the same principles,
called the boost converter or up converter, represented by figure 13.3–8.
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Figure 13.3–8: The direct converter ‘boost’ topology.
This converter will take the energy stored in the inductance during the first part of the duty cycle and
dump it into the right–hand side of the circuit at a higher voltage induced by the inductance. If DP
represents the duty cycle of the controlled switch, which is now the shunt switch, then current through the
diode results only when the controlled switch turns off. The fraction of the interval for which the
controlled switch is off corresponds to duty cycle (1– DP) for which the diode is toggled into a conducting
state. The conduction current through the diode is therefore
I D = I 2 = (1 − D P ) I 1
(13.3–9)
Since we require that the circuit be lossless, for which I2V2 = I1V1, then, by equation (13.3–9) the voltage
at the output must be:
V2 =
V1
(1 − D P )
(13.3–10)
Since (1 – D’) is always less than 1, then V2 > V1, and the converter therefore ’boosts’ the voltage.
The voltage across capacitance C is VC = V2. Compare this condition to the buck converter, it was V1 that
fell across capacitance C. Therefore, if we designate DS = the duty cycle of the series switch, which for
the boost converter is defined by (13.3-9) as 1 – DP, then equations (13.3–10) and (13.3–2a) are exactly
the same.
This is no coincidence, of course. The topologies are the same, except that figure 13.3–8 is a right–to–left
reflection of figure 13.3–4. The only difference is in the achoice of the controlled switch and the diode.
Analysis is therefore entirely the same as for the down converter except that subscripts are interchanged.
Ripple equations for voltage across the capacitance and current through the inductance are the same as
(13.3–4) and (13.3–6), except that the subscripts may be interchanged if we adhere to subscript 1 as being
at the input and subscript 2 as being at the output. A comparison is represented by example 13.3–2.
**********************************************************************************
EXAMPLE 13.3–2: Warrior–brand combat underwear uses a muscle electrostimulation (ESM) unit
which requires 72V at 1A to operate in the superman mode. If it is supplied by a 9V battery belt capable
of supplying 50A of short–circuit current, determine (a) converter values V1, and I1 and duty cycle D’ of
the controlled switch, (b) values of L and C needed to keep the voltage ripple at the output and the current
ripple of the input to less than 2%, assuming that the circuit is toggled at switching frequency fs = 50
kHz.
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SOLUTION: (a) the output requirement is P2 = PL = I2 V2 = 1A x 72V = 72W.
Assuming that the converter is approximately lossless, I1V1 = I2V2.
In this case we have V1 = VB – I1R1, where VB = battery voltage = 9V and R1 = RB = 9V/50A = 0.18Ω.
Therefore
(V B − I 1 R B ) I 1 = P2 = 72
Which, with values is of the form
(9 − 0.18I 1 ) I 1 = 72
which has solutions I1 = 10A and 40A. Although both solutions will work, I1 = 10A is the more
reasonable one, and will correspond to
V1 = 7.2V
and DP = 1 – I2/I1 = 0.9
(b) For ripple of less than 2%,
ΔV2 = ΔVC = .02 x 72 = 1.44 V
According to equation (13.3-4)
C=
I1
(1 − DS )T
ΔVC
As far as the topology is concerned DP and (1 - DS) are the same, since both are the fraction of the cycle
for which the two sides are not conjoined. I1 is the current flowing off the capacitance, which for the
boost converter corresponds to that through the load = 1.0A, so that
C=
1 .0
× (0.9 × 20 μs )
1.44
= 12.5μF
where we have used T = 1/fs = 20
Similarly for a 2% ripple in input current, and evaluating for the condition that SW1 = ON (and for which
the two sides are disconnected)
1
ΔI 1 = ΔI L = .02 × 10 = × (7.2 × (0.9 × 20 μs ))
L
and which gives L = 648μH
**********************************************************************************
The topology of figure 13.3–8 requires the need of the quadratic equation
(V B − I 1 R B ) I 1 = PL
for which the required solutions is
I1 =
VB
2RB
⎛
⎜1 − 1 − 4 PL R B
⎜
V B2
⎝
⎞
⎟
⎟
⎠
(13.3–11)
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Synopsis: For the direct converter (whether up or down), equations (13.3-8) and (13.3-11) are the
benchmarks for the voltage and current transfer from one type of energy storage element to the other and
can be restated as
⎛
⎜1 + 1 − 4 PL R B
⎜
V B2
⎝
VC =
VB
2
IL =
VB
2RB
⎞
⎟
⎟
⎠
⎛
⎜1 − 1 − 4 PL R B
⎜
V B2
⎝
(13.3–12a)
⎞
⎟
⎟
⎠
(13.3–12b)
for which VC is the averaged voltage that appears across the capacitance and IL is the averaged current that
flows through the inductance. Equations (13.3-12a) and (13.3-12b) identify the unknown input level,
from which the duty cycle D that is required to accomplish the conversion can then be identified.
The ripple across these elements is defined by the R-C and R-L constants which can be restated in terms
of equations (13.3-4) and (13.3-6a)
IC
D S (off )T
C
(13.3-13a)
VL
D S (off )T
L
(13.3–13b)
ΔVC =
ΔI L =
where the usage identifies that the ripple is stated in terms of current IC that is supplying the capacitance
and voltage VL that is supplying the inductance. The use of Dseries(off) nomenclature identifies the fraction
of the duty cycle for which the two sides of the converter are electrically isolated from each other as
results of the series switch being off.
It is a little more practical to express equations (13.3-13a) and (13.3-13b) in terms of the time constants τC
= RC C and τL = L/RL , where RC is the resistance in the capacitance path and RL is the resistance in the
inductance path. Using these relationships the ripple equations take the form
ΔVC
1
=
Δt (off )
I C RC τ C
(13.3-14a)
ΔI L
1
=
Δt (off )
VL RL τ L
(13.3–14b)
In the case of the direct-down converter topology, the resistance in the capacitance path corresponded to
RB and the resistance in the inductance path corresponded to RL. And for the nomenclature used with this
topology, I1 corresponds to IC and I2 corresponds to IL. Take note that VC ≠ I C RC for the down converter.
It is not good practice to assume that the resistance RB of the power source be equal to zero. When it is
assumed then the down-converter will have no need of a capacitance. And the up-converter will
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(apparently) have no need of an inductance, which is not true since the inductance is needed to toggle the
reactive switch. The mathematics does become simpler since the duty cycle D is sufficient to describe the
relationships between input and output, since both are then either known or identified by the load
requirement and the source characteristics.
13.4 THE DC-DC INDIRECT (UP/DOWN) CONVERTER
Another topology is the indirect converter represented by figure 13.4–9. This topology can be either an
‘up‘ converter or a ‘down’ converter.
Figure 13.4-9. The indirect (buck-boost) converter topology
If we acknowledge that the time average of voltage over the inductance must be zero, then
V1 DT − V2 (1 − D )T = 0
so that
V2
D
=
V1 1 − D
(13.4-15)
where D is the duty cycle of the controlled switch and T is the period of the cycle. Depending on the value
of D, V2 can be either greater or less than V1. We also note that the average capacitance current must be
zero, in which case,
I 2 DT = I 1 (1 − D )T
which is the same as
I2 1− D
=
I1
D
(13.4-16)
This result just confirms that the (ideal) net power going into the converter should be zero, assuming that
the converter is approximately lossless.
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13.5 LOSS ANALYSIS OF DC-DC CONVERTERS
But as is true for the power amplifiers, the converter is not lossless, since some power is dissipated in the
switching components themselves. For the cases represented by figure 13.5–4 and its cousins, these are
the transistor(s) and the diode(s). Although considerably better than mechanical switches, these
components will have finite turn–on and turn–off times during which significant power levels are
dissipated in the switches. The principle is represented by figure 13.5–10.
Figure 13.5–10: Power dissipation in the switches.
Assuming that a switching transition can be represented by an approximately linear behavior over
transition interval (0 < t < ΔtON) as represented by Figure 13.5–8, then during this transition time
I (t ) = I ON ×
i
Δt ON
and
⎛
t
V (t ) = (VOFF − VON )⎜⎜1 −
Δt ON
⎝
⎞
⎟⎟ + VON
⎠
The power dissipated in the switch during transition is the time–average P (t ) over the switching
interval 0 < t < ΔtON for which
P (t ) =
1
T
Δt ON
∫
0
I (t )V (t )dt =
Δt ⎡ 1 1 VON
×⎢ +
T ⎣ 6 3 VOFF
⎤
⎥ I ON VOFF
⎦
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(13.5-17)
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where Δt is the transition time (= either ΔtON or ΔtOFF) and T = 1/fS, with fS = switching frequency.
Equation (13.5-17 is the same for either the ON-OFF or the OFF-ON transition.
The current ION that passes through either one of the switches is always the current through the
inductance. The voltage VOFF across a switch is always the voltage across the capacitance. It should be
no surprise that the energy–storage elements define the levels of voltage and current that are switched
on/off by the two complementary switching elements to yield the desired I1,V1 -> I2, V2 conversion.
Furthermore, the power dissipated when the switch is on is
⎛ DT − Δt ON ⎞
PD (ON ) = I ON VON × ⎜
⎟
T
⎝
⎠
(13.5-18)
where D is the duty cycle for the switch, whether defined by external control or defined by the reflexive
nature of the circuit.
Turn–on and turn–off times ΔtON and ΔtOFF are a function of the levels of current and voltage, since these
switches must usually be ”charged up” for minority–carrier injection or the depletion of a drift region.
ΔtON and ΔtOFF are on the order of μs for large power transistors and diodes . These response times are the
fundamental limit to the switching speed fs. Also the switches themselves will have a finite voltage drop,
which, as we noted in section 20.3. These may on the order of 1 to 6V for a power BJT in the ”ON” state.
A power diode will have an ”ON” voltage drop on the order of 0.6V to 2.0V. For low–voltage
converters, as represented by examples 13.5–1, and 13.5–2, common off–the–shelf, large BJTs and diodes
may be used, for which the voltage drop across the devices is less severe.
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EXAMPLE 13.5–3: Assume that the controlled switch (= BJT) of example 13.5–1 has VCE (on) = 1.0V,
and that the diode has V(on) = 0.6 V. Assume that ΔtON = 1.0μs = ΔtOFF for both devices. Determine the
power dissipated in the switches.
SOLUTION: The switching frequency fS = 50kHz, for which 1/fS = 20μs. From the example ION = IL =
I2 = 50A and VOFF = VC = V1 = 25V. From equation (13.5–8) the power dissipated during switch
transitions is then
PD1 (transition) = (50 × 25) ×
1.0 μs + 1.0μs ⎡ 1 1 1.0 ⎤
×⎢ +
⎥
20 μs
⎣ 6 3 25.0 ⎦
= 22.5W
PD 2 (transition) = (50 × 25) ×
1.0 μs + 1.0 μs ⎡ 1 1 0.6 ⎤
×⎢ +
⎥
20 μs
⎣ 6 3 25.0 ⎦
= 21.8W
The power dissipated during the time when the switches are ‘ON is
(0.2 × 20 μs ) − 1.0 μs
20 μs
(0.8 × 20 μs ) − 1.0μs
PD 2 (ON ) = (50 A × 0.6V ) ×
20 μs
PD1 (ON ) = (50 A × 1.0V ) ×
Therefore the power dissipated budget due loss in the switches is
12
= 7.5W
= 22.5W
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PD1 = PD1 (trans ) + PD1 (ON )
= 30W
PD 2 = PD 2 (trans ) + PD 2 (ON )
= 44.3W
This loss represents a total PD of 74.3 W. Since the power load requirement was 250W, it is necessary to
factor this power loss into the analysis, for which it is apparent that duty cycle D will have to be increased
in order to compensate for the loss in the switches. The process is iterative. If iterations are carried back
and forth between examples 20.8.1 and 20.8.2, with the modification
I 1V1 = I 2V2 + PD
With PD = PD1 + PD2 and a repeat of the analysis, we find that the duty cycle must be increased to D =
0.203. And with this change we also find that V1 increases t 24.62 V
**********************************************************************************
In example 13.5–3, the change in the duty cycle D due to the power loss in the switches is relatively
minor. The analysis does alert us that we need to have a BJT and a diode capable of dissipating
approximately 30W and 44.3W, respectively. Allowing for safety margins and de-rating via the heat
sinks, this converter can probably be constructed using a 75W power transistor and a 100W diode to
support the 250W load with circuit efficiency 77%.
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