WWW.UandiSTAR.org - DICA JNTU ONLINE EXAMINATIONS [Mid 1 -DICA] b. 4 1. _ _ _ _ _ _ _ _ _ _ _ _ as a voltage controlled c. 2 resistance. d. 1 a. TTL 13. In CMOS inverter circuit we prefer the pull-down b. DTL transistor in _ _ _ _ _ _ _ _ _ c. RTL a. Depletion mode PMOS d. MOS WWW.UandiSTAR.org 2. Fabrication of components on a single chip b. Enhancement mode PMOS a. Differentiated circuit c. Depletion mode NMOS b. Integrated circuit d. Enhancement mode _MOS c. Multiplexer circuit 14. When Vin of 0.0V is applied to CMOS circuit d. Logic circuit PMOS is _ _ _ _ _ _ _ _ _ _MOS is _ _ _ _ _ _ 3. ``MOS`` is usually spoken as ``MOSS`` and ___ ``CMOS`` has always been spoken as a. Off, On a. C MOSS b. On, Off b. See Moss c. Off, Off c. Sea Moss d. On, On d. Cea Moss 15. When Vin of 5V is applied to the CMOS circuit 4. First logic family came into picture PMOS is _ _ _ _ _ _ _ _ and _MOS is _ _ _ _ a. TTL _____ b. CMOS a. Off, On c. NMOS b. On, Off d. PMOS c. Off, Off 5. State 0 representing bit CMOS logic d. On, On a. 0 - 1.5V 16. In _ _ _ _ _ _ _ _ _ _ _ _ _ transistors act as a b. 3.5 - 5V voltage controlled resistance. c. 0 - 0.8V a. TTL, ECL d. 2.0 - 5.0V b. CMOS, TTL 6. `0` state representing bit in relay logic. c. CMOS, _MOS a. 0 to 1.5V d. NMOS, TTL b. 3.5 to 5V 17. In CMOS logic `1` represents c. Circuit open a. 0 - 1.5V d. Circuit close b. 3.5 - 5V 7. `1` state representing bit in fibre optics c. 1.5 - 3.5V a. Circuit open d. 0- 0.8V b. Circuit closed 18. In PMOS transistor Vgs decreased then Rds is c. Light off a. Increased d. Light on b. Decreased 8. `1` STATE REPRESE_TI_G BIT I_ DY_AMIC c. Constant MEMORY. d. Infinity a. Capacitor discharged 19. In _MOS transistor Vgs increased then Rds is b. Capacitor charged a. Increased c. Fuse blown b. Decreased d. Fuse intact c. Insulator 9. First integrated circuit logic familes in year. d. Constant a. 1933 20. In _MOS transistor has a very high impedance b. 1947 because the gate separates source and c. 1960 drain by an material with a very high resistance. d. 1969 a. Semiconductor 10. Beginning in the mid _ _ _ _ _ _ _ , CMOS vastly b. Conductor increased their Performance and c. Insulator popularity. d. Wood a. 1960 21. Output loading for HC series cmos with a 5V b. 1980 supply find Maximum low state output c. 1970 current (mA) d. 2000 a. 0.1 11. In 2 i/p CMOS _A_D gate, no. of _MOS transistors b. 0.02 used are _ _ _ _ _ _ c. -0.02 a. 3 d. 4.4 b. 4 22. Output loading for HC series CMOS with a 5V c. 2 supply find the Maximum high state output d. 1 current (mA) Ioh maxc 12. In 2 i/p CMOS A_D gate, no. of PMOS transistors a. 0.1 used are _ _ _ _ _ _ b. 0.02 a. 3 c. -0.02 Page 1 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile WWW.UandiSTAR.org - DICA d. 4.4 23. The range of Vih min in cmos is a. of Vcc b. of Vcc c. of Vcc d. of Vcc 24. When the current flows from the power supply through the load and through the device output to ground. a. sourcing current b. sinking current c. conventional current WWW.UandiSTAR.org d. of Icc 25. When current flows from the power supply out of the device output and through the load to ground. a. sourcing current b. sinking current c. conventional current d. of Icc. 26. Low state dc noise margin between ` a. V ,V b. V ,V c. V ,V d. V , V 27. .When Vdd=5V define a cmos low input level under _ _ _ voltage. a. 1.6V b. 1.4V c. 2.4V d. 2V 28. The range of Voh min in cmos circuit is a. Vcc-0.7V b. Vcc-0.1V c. Vcc-0.6V d. Vcc-0.2V 29. The range of Vil max in cmos is a. of Vcc b. of Vcc c. of Vcc d. of Vcc 30. The range of pull up transistor resistance is a. >1Mohm b. >1Kohm c. >10ohm d. >100 ohm 31. Total dynamic power dissipation of a CMOS circuit is the sum of Pt and Pl a. Pd= (Cpd-C_L).Vc.f b. (Cpd/C_L).Vc.f c. Pd= (Cpd+C_L).Vc.f d. Pd= (Cpd.C_L)V2cc.f 32. Obtain the rise time of CMOS output as Vout= 1.5V a. t1.5=24.08ns b. t1.5=7.13ns c. t1.5=71.3ns d. t1.5=2.408ns 33. Due to the rise time of CMOS output Vout = _ _ _ _______. a. b. c. d. 34. Due to fall time of CMOS output Vout = _ _ _ _ _ _ ___. a. vdd.e b. vdd.e c. d. 35. Internal power dissipation due to output transition a. Pt= Cpd.Vc.f b. Pt= Cpd.Vcc.f c. Pt= Cpd.Vc/f d. Pt= Cpd/Vc.f 36. In CMOS loading effects out voltage may _ _ _ _ _ _ _ beyond Vo Lmax a. decrease b. increase c. constant d. zero 37. In CMOS loading effects propagation delay to the output may _ _ _ _ beyond WWW.UandiSTAR.org specifications. a. decrease b. increase c. constant d. zero 38. The amount of time that the output of a logic circuit takes to change from one state to another is called the a. delay time b. propagation time c. transition time d. diffusion time 39. In CMOS output takes change from low to high state a. rise time b. fall time c. propagation delay time d. constant time 40. In CMOS output takes change from high to low state a. fall time b. rise time c. constant time d. propagation delay time 41. In CMOS load what is low level output current in VHC family a. 0.02 b. 0.05 c. 0.2 d. 0.5 42. AB_ORMAL region in CMOS devices as follows a. HC less,HCT more b. HC more,HCT less c. HC constant,HCT constant d. HC zero,HCT zero 43. In HC/HCT,VHC/VHCT outputs have symmetric output drive ie.,an output can _ _ _ _ _ _ ___ a. sink current=source current b. sink current > source current c. sink current < source current d. constant current 44. Typical propagation delay (ns)in VHC series is a. 9 b. 10 Page 2 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile WWW.UandiSTAR.org - DICA c. 5.2 d. 5.5 45. 74series is used for commercial devices .Its temperature range is _ _ _ _ _ _ _ _ _ 0C a. 0 to 85 b. 55 to 125 c. 0 to 70 d. 0 to 10 46. `` 74FAMnn`` form of CMOS device nn represents as a. AC b. HC c. HCT d. 30 47. CMOS high speed represents a. 74ACT30 b. 74AHC30 c. 74HC30 d. 74AC30 48. The prefix '54' is used for identical parts that are specified for operation over a wider range of temperature use in _ _ _ _ _ _ application a. commercial b. military c. industrial d. instrument WWW.UandiSTAR.org 49. In 74HC30 series Vihmin= _ _ _ _ _ _ _ _ and Vcc=5.0V a. 1.5 V b. 3.5V c. 3.84V d. 0.33V 50. In 74HCT30 series Vilmax= _ _ _ _ _ _ _ _ _ _ _ and Vcc=5.0V a. 0.33V b. 2.0V c. 0.8V d. 3.84V 51. Low output of TTL is in between a. 2.0 to 5.0 b. 2.0 to 3.0 c. 0 to 0.8 d. 0 to 2 52. TTL output stage is called _ _ _ _ _ _ _ a. totem pole b. push back c. pull back d. pull down 53. In bipolar logic family _ _ _ _ _ _ _ _ _ type of transistor operates fastly a. npn b. pnp c. schottky transistor d. CCtransistor 54. Vγ voltage of schottky transistor a. 0.25V b. 0.6V c. 0.3V d. 0.4V 55. _ _ _ _ _ _ _ _ _ _ _ combination will give fastest inverter. a. CE &CB b. CE & Schottky c. CE &CC d. CC &CB 56. The negative leakage current flow in diode when it is a. forward biased b. reversed bias c. short circuited d. constant 57. Logic levels in a simple diode logic system when signal level 2-3volts a. low b. high c. noise margin d. 1 58. In transistor logic family _ _ _ _ _ _ _ _ region works as binary `1` a. cut off region b. active region c. saturation region d. break down region 59. We can also call transistor as _ _ _ _ _ _ _ Diodes connected a. back to front b. back to back c. front to back d. front to front 60. Basically the single stage CE transistor act as _ _ _ _ _ _ _ logic circuit a. multiplexer b. inverter c. differentiator d. decoder 61. The 74F family is positioned between _ _ _ _ _ _ _ _ and _ _ _ _ _ _ _ _ _ in the speed/powertrade off a. 74S,74LS WWW.UandiSTAR.org b. 74LS,74AS c. 74S,74AS d. 74AS,74ALS 62. The original TTL family of logic gates was introduced by _ _ _ _ _ _ _ _ in 1963 a. paul b. leach c. Sylvania d. goutham saha 63. Speed power product units used in 74ALS family a. ns b. mw c. pj d. v 64. Power consumption per gate units used in 74F family a. ns b. mw c. pj d. watts 65. More power consumption present from following family a. 74LS b. 74AS c. 74ALS d. 74S 66. Low state dc noise margin for popular TTL families (74LS,74S,74ALS,74AS,74F) a. 0-0.5 b. 0.5-0.8 Page 3 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile WWW.UandiSTAR.org - DICA c. 0.8-2 d. 2.0-2.7 67. High state dc noise margin for popular TTL families(74LS,74S,74ALS,74AS,74F) a. 0-0.5V b. 0.5-0.8V c. 0.8-2.0V d. 2.0-2.7V 68. The value of IoL(max) for typical LS-TTL output is exactly _ _ _ _ _ _ _ times the absolute value of I a. 10 b. 5 c. 20 d. 40 69. The absolute value of IoH(max) is exactly _ _ _ _ _ _ _ _ times I in LS-TTL a. 10 b. 20 c. 5 d. 40 70. The overall fanouts of low state and high state fanout in LS-TTL is a. <10 b. >40 c. <20 d. >20 71. Best family of following according to speedpower product a. 74S b. 74LS c. 74AS d. 74ALS 72. Best family of following according to power consumption per gate a. 74S b. 74LS c. 74AS d. 74ALS 73. The V of 3.3V LVTTL family is _ _ _ _ _ _ _ _ _ _ _ a. 3.3V WWW.UandiSTAR.org b. 2.4V c. 2.0V d. 1.5V 74. The V of 2.5V CMOS family a. 0.7V b. 1.7V c. 1.2V d. 0.4V 75. The transtition from 3.3V to 2.5V logic in CMOS families _ _ _ _ _ _ _ _ _ circuit is preferred a. inverter b. pushpull c. level translator d. amplifier 76. The low state dc noise noise margin equal to _ _ _______ a. b. c. d. 77. The V of 5V TTL family a. 2.4V b. 0.4V c. 0.8V d. 2.0V 78. The high state dc noise margin equal to _ _ _ _ _ _____ a. V b. V c. V d. V 79. The external input and output circuits also called in CMOS a. core logic b. pad logic c. pad ring d. core ring 80. The V of 5v CMOS family a. 5.0V b. 4.4V c. 3.5V d. 2.5V 81. JEDEC stands _ _ _ _ _ _ _ _ _ _ _ _ _ _ a. Joint Electrical Device Engineering Council b. Joint Electronic Device Engineering Council c. Joint Electronic Device and Electrical Components d. Joint Electric Device and Electronic Components. 82. In ECL propagation delay is a. shorter b. long c. constant d. zero 83. For basic CML inverter/buffer circuit applied inputs are Vin=3.6V, Vbb=4.0V, Vcc=5.0V. Find outputs when R1=R2=300ohms, R3=1.5Kohms a. 5.0,4.8V b. 4.8,4.2V c. 5.0,4.2V d. 5.0,4.8V 84. In ECL 100k family shorter propagation delay typically is _ _ _ _ _ _ _ _ _ _ a. 0.85ns b. 0.95ns c. 0.65ns d. 0.75ns 85. In PECL, `P` represents a. pulse b. propagation WWW.UandiSTAR.org c. positive d. p channel 86. ECL belongs to _ _ _ _ _ _ _ _ _ _ _ family. a. bipolar-saturated b. bipolar- non-saturated c. unipolar- saturated d. unipolar-non saturated 87. ECL is also called as a. TTL b. CMOS c. CML d. CPL 88. ECL concept was soon refined initially by a. Texas Instruments b. Motorola c. Intel d. Philips 89. Very poor speed-power product is for a. TTL b. CMOS Page 4 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile WWW.UandiSTAR.org - DICA c. HTL d. ECL 90. In few applications like fiber optic transreceiver interfaces for gigabit Ethernet, from the following _ _ _ _ _ _ logic family is used a. TTL b. CMOS c. HTL d. ECL 91. Units of dynamic power dissipation in CMOS a. PJ b. ns c. mw d. mv/MHz. 92. From following standard TTL IC,Quad 2 input _OR a. 7408 b. 7400 c. 7432 d. 7402 93. Logic family that gives totempole output a. TTL b. ECL c. RTL d. DTL 94. Fastest logic family from the following. a. TTL b. Schottky TTL c. RTL d. DTL 95. Typical propagation delay of 74HCnn series is a. 9 or 18 b. 10 or 20 c. 5.2 or 7.2 d. 5.2 or 8. 96. Fastest logic family from the following. a. ECL b. TTL c. NMOS d. PMOS. 97. Logic Family that dissipates more power. a. TTL b. ECL c. CMOS d. DTL WWW.UandiSTAR.org 98. Highest noise margin is present in which of the following logic families. a. HTL b. DTL c. RTL d. TTL 99. Which one of the following belongs to nonsaturated logic family. a. TTL b. HTL c. CML d. RTL 100.Which one of the following belongs to unipolar logic family. a. TTL b. CMOS c. CML d. HTL 101.A VHDL _ _ _ _ _ _ _ _ allows you to define and apply inputs to your desired and to obsevreits outputs a. synthesis b. timing verification c. compilation d. simulator 102.VERILOG was introduced by _ _ _ _ _ _ _ _ _ _ in 1984 as a proprietary hardware description and simulation language a. gate way digital automation b. gateway Design application c. gateway design automation d. gateway digital application 103.VHDL gives you ability to create _ _ _ _ _ _ _ _ _ _ that automatically apply inputs & compare them with expected outputs a. compiler b. interrupt c. test benches d. verification 104._ _ _ _ _ _ _ _ _ converting the VHDL description into set of primitives /components that can be assembled in the target technology a. compilation b. verification c. coding d. synthesis 105.In the _ _ _ _ _ _ _ _ _ Step maps the synthesized primitives/components on to available device resources a. verification b. coding c. fitting d. synthesis 106.From the following select the odd one a. Vhdl b. Verilog c. System c d. Unix 107.In VHDL ``V`` stands for a. VHSIC b. VHIC c. VIC d. VHS 108.In VHDL is specialized with _ _ _ _ _ _ _ _ _ _ for easier a. operating system b. help manual c. text editor d. windows 109.In design flow after computation next stage is _ _ ______ a. coding b. simulation /verification WWW.UandiSTAR.org c. place & routing d. fitting 110.In backend design flow after synthesis next stage is. a. coding b. fitting/place & route c. compilation d. timing verification 111.Port is used in following syntax a. architecture b. entity c. concurrent statements d. sequential statements Page 5 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile WWW.UandiSTAR.org - DICA 112.From the following symbol compulsory to complete syntax or statement a. : b. = c. ; d. & 113.In VHDL architecture syntax a. architecture entityname of architecture name is b. architecture architecturename of entity name is c. architecture name architecture of entity name is d. entity name architecture of architecture name is 114.In VHDL variable declarations syntax a. variable variable-name : variable-type; b. variable name variable : variable type; c. variable type variable : variable name; d. variable name variable type : variable; 115.One of the follwing is not used for mode(specify the signal direction) a. in b. out c. inout d. variable 116.A VHDL _ _ _ _ _ _ _ is simply a declaration of a module inputs and outputs. a. architecture b. dataflow c. entity d. behavioral model 117.A VHDL _ _ _ _ _ _ _ is a detailed description of the module`s internal structure or behavior. a. architecture b. dataflow c. entity d. behavioral model 118.In VHDL language comments are begined with _ _____ a. // b. c. - . d. . 119.In VHDL signal declaration a. signal signal name => signal type; b. signal name signal => signal type; c. signal name signal : signal type; d. signal signal name : signal type; 120.Below one of the definition present between architecture begin and end _ _ _ _ a. type declarations b. signal declarations c. component declarations d. concurrent statements 121.From the following find the odd one a. type type _ name is array(start to end) of element type; b. type type _ name is array(start down to end) of element type; c. constant type _ name is array (range _ type) of element type; WWW.UandiSTAR.org d. type type _ name is array(range _ type range start to end) of element type; 122.VHDL language only 1 and 0 are used in port by following predefined type. a. bit b. integer c. real d. boolean 123.Total number of values present in std _ logic. a. 8 b. 6 c. 7 d. 9 124.From the following find odd a. and b. or c. nand d. abs 125.Constant syntax from following a. Constant constant _ name:value:=type _ name; b. Constant constant _ name:type _ name:=type; c. Constant constant _ name:type _ name:=value; d. Constant type _ name:constantname:=value; 126.From the following select integer operators. a. U b. + c. and d. L 127.From following select integer operators. a. U b. and c. H d. abs 128.From following forcing unknown value is represented by. a. U b. X c. 0 d. 1 129.From following don't care is represented by a. b. -c. -, d. ; 130.From following concatenation operator. a. & b. & & c. d. 131.A VHDL _ _ _ _ _ _ _ _ _ _ _ is similar to a function , except it does not return a result a. attribute b. process c. procedure d. exit 132.In procedure syntax : procedure procedure name (parameter _ list) following is not comes under the parameter-list a. bit b. integer c. clause d. std _ logic 133.When a standard operator symbol is made to behave differently based on the type of its operands , it is called a. program overloaded b. operator overloaded c. syntax over loading d. no loading WWW.UandiSTAR.org 134.``Do nothing``represents _ _ _ _ _ _ _ _ _ _ _ statements a. exit Page 6 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile WWW.UandiSTAR.org - DICA b. null c. wait d. for 135.Where the single quote after a signal name means _ _ _ _ _ _ _ _ _ _ _ and range is built in identifier a. attribute b. null c. wait d. exit 136.In function at end of function _ _ _ _ _ _ _ _ _ type is preferred. . a. Exit b. Wait c. Return d. Null 137.Syntax of function. a. Function function-name(parameter-list). ________ _________ Return return-type; b. Function function-name(sequential statements). Function function-name(parameter-list). ________ _________ Return return-type; c. Function function-name (concurrent statements) Function function-name(parameter-list). ________ _________ Return return-type; d. Function function-name(parameter list) Function function-name(parameter-list). ________ _________ Return exit; 138.A function executes in minimum _ _ _ _ _ _ _ simulation time. a. Zero b. Infinity c. Negative infinity d. Finite. 139.A _ _ _ _ _ _ may or may not execute in zero simulation time depending on whether it has a wait statement or not. a. Function. b. Architecture. c. Procedure. d. Process. 140.If the same name is used for function with different data types at that function is a. Over loaded b. Under loaded c. No loading. d. Exit. 141.Which of the following does not come under type std _ logic? a. `U` b. `X` c. `0` d. `Y` 142.IEEE. Std _ logic _ 1164, 1164 represents standard logic _ _ _ _ a. function b. procedure c. package d. memory WWW.UandiSTAR.org 143.Library and use clause comes under _ _ _ _ _ _ visibility. a. implicit b. explicit c. over d. under 144.VHDL source design file is divided into primary and secondary unit; under secondary unit which of the following is not present a. Architecture bodies b. package bodies c. function calling d. entity declarations 145.Syntax for use clause is a. use library ieee.std _ logic _ 1164.all; b. use ieee.all.std _ logic _ 1164.all; c. use ieee.std _ logic _ 1164.all; d. use ieee.std _ logic.all; 146.A VHDL _ _ _ _ _ _ _ is a place where VHDL compiler stores information about a particular design project, including intermediate files. a. function b. procedure c. exit d. library 147.In VHDL library clause, the beginning of design file is with a. library isse; b. library use; c. library ieee; d. library std _ logic; 148.A VHD L _ _ _ _ _ _ _ is file containing definitions of objects that can be used in other programs ( signal, type, constant) a. exit b. null c. wait d. package 149.From the following, the package declaration that is wrong is a. package package-name is sub program declaration; end [package] [package-name]; b. package package-name is type declaration; end [package] [package-name]; c. package package-name is constant declaration; end [package] [package-name]; d. package package-name is null declaration; end [package] [package-name]; 150.Intermediate files that are not used in VHDL are a. analysis b. simulation c. synthesis d. operating system 151.Block syntax a. Block label :block begin end block; b. Block : block label begin end block; c. Block label: block begin end Block label; Page 7 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile WWW.UandiSTAR.org - DICA d. Block :block label begin end block label ; 152.Generic map clause is the same style as the _ _ _ _ _ clause. a. block b. package c. port d. generic. 153.For generate loop syntax a. label: for identifier in range generate WWW.UandiSTAR.org concurrent _ statement end generate; b. label: range identifier in for generate concurrent _ statement end generate; c. label: generate identifier in range generate concurrent _ statement end generate; d. label: for identifier in range generate concurrent _ statement end for; 154.Generic syntax a. generic(constant _ name: constant _ type; constant _ name : constant _ type); b. generic (constant _ name: constant _ type; constant _ name : constant _ type;) c. generic ( constant _ type: constant name; constant _ t ype: constant name); d. port (constant _ type: constant name); 155.Component declaration syntax a. component component _ name port (< port _ declaration>); end component; b. component _ name component port (<port _ declaration>); end component; c. component _ name component port (<port _ declaration>); end component _ name; d. component _ name component port (<port _ declaration>); end port; 156.Port map is used in following model a. data flow b. behavioural c. structural d. constant 157.Port map syntax a. label: component _ _ name port map(signal 1,signal 2,.....signal n); b. label: port map component _ name (signal 1,signal 2,. signal n); c. component _ name: label port map (signal 1,signal 2,.signal n); d. port map(signal 1,signal 2,.......signal n): label component _ name; 158.Component is used in following model a. data flow b. structural c. behavioral d. constant. 159.Component declaration is used in following model: a. data flow b. structural c. behavioral d. constant 160.Generic constants are declared in a. function b. entity c. architecture d. procedure 161.simple assigned programme of synthesized data flow model a. Y <= A and B b. Y= A and B; c. Y/ =A and B; d. Y < =A and B; WWW.UandiSTAR.org 162.simple assigned programme of synthesized data flow model a. Y <= A +B b. Y= A +B; c. Y/ =A +B; d. Y < =A +B; 163.case-statement syntax a. case <expression> is when <choices> =>statements; when others=>statements; End case; b. case <expression> is when others =>statements; when choices =>statements; end case; c. case <expression> is when statements=>choices; end case; d. case <expression> is when choices=>when others; end case; 164.component instantiation syntax A and B inputs and Y output a. label:component _ name port map(A,B,Y); b. label:port map component name(A,B,Y); c. label:component name port map(Y,A,B); d. label:component name port map(A,Y,B); 165.Assigning operator is used as a. < b. < = c. > = d. / = 166._ _ _ _ _ _ _ _ _ statement preferred in data flow a. concurrent b. sequential c. process d. procedure 167.concurrent assignments is as follows a. signal name <=expression; b. if Boolean expression then statement ; else statement; end if; c. exit label1 when condition; d. constant constant _ name : type-spec : = value; 168.conditional form of the concurrent signal assignment statement using keywords a. if else b. if else if else c. when else d. when else if else 169.``with select`` syntax Page 8 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile WWW.UandiSTAR.org - DICA a. with expression select signal name<=signal value when choices; b. with signal name select expression<=signal value when choices; c. with signal name select signal _ value <=expression when choices; d. with signalvalue select signal name<=expression when choices; 170.keyword ``others`` used in _ _ _ _ _ _ _ _ _ _ _ syntax a. with select b. if else c. if else if else d. process 171.Functional statement in Behavioral Model WWW.UandiSTAR.org a. process (variable) Begin ----------------------Functional statement; -------End process b. Begin Functional statement; Process(variable) Begin ---------------------End process; c. Begin Process(variable) Functional statement; Begin ------------------------End process; d. Begin Process (variable) Begin -------. ------------End process; Functional statement; 172.Procedure statement in Behavioral Model a. Process (variable) Begin --------------------------Procedure statement; ----------End process b. Begin Procedure statement; Process (variable) Begin -------------------End process; c. Begin Process (variable) Procedure statement; Begin ------------------End process; d. Begin Process (variable) Begin ------------. -------End process; Procedure statement; 173.Sequential statements is not following syntax's a. Case b. for loop c. loop d. with select WWW.UandiSTAR.org 174.while loop syntax in behavior model a. Wile Boolean expression loop Concurrent statement End loop; b. while Boolean expression loop Sequential statement End loop; c. While loop Boolean expression Sequential statement End loop; d. While loop Boolean expression Concurrent statement End loop; 175._ull statement in Behavioral Model a. Process (variable) Begin -----------------------_ull statement; ----------End process ; b. Begin Null statement; Process(variable) Begin -------------End process; c. Begin Process (variable) Null statement; Begin ---------------End process; d. begin process(variable) begin ---------. ---------End process; Null statement; 176._ _ _ _ _ _ _ _ _ _ _ statements are preferred in the Behavioral a. Concurrent b. Sequential c. Constant d. Exit 177._ _ _ _ _ _ _ _ _ _ _ is present in between process begin and end process a. Type Declarations b. Variable Declarations c. Constant Declarations Page 9 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile WWW.UandiSTAR.org - DICA d. Sequential Statements 178.Applying inputs to A, B not applied to Y in the program write process a. Process (A, B, Y) b. Process (A, B) c. Process (A, Y) d. Process (B, Y) 179.Assignment operator in Behavioral a. := b. =: c. d. WWW.UandiSTAR.org 180.Loop Syntax a. Sequential statement; loop end loop; b. loop sequential statements; end loop; c. loop concurrent statement; end loop; d. concurrent statement; loop end loop; 181.The _ _ _ _ _ _ _ _ _ _ mechanism ensures correct operation even through a processes or set of processes may require multiple execution a. delta delay b. event list c. case d. while 182.Following statement is incorrect time dimension a. wait on data; b. wait for 0ns; c. wait until clock =`1`; d. wait until A, B, C; 183.Simulator initializes all signals to a default values when simulator operation begins at simulation time of _ _ _ _ _ _ _ _ _ a. Zero ns b. 10 ns; c. 15 ns; d. 20 ns; 184.Signal Assignment statement of time dimension syntax a. signal _ object <= expression [after delay value] b. signal _ object <= [after delay value] expression c. signal _ object [after delay value] <= expression d. signal _ object [after delay value] / = expression 185.Following statement is incorrect time dimension assignment a. counter <= counter + "0010"; b. PAR <= PAR XOR DIN after 12sec; c. Z<= (A0 and A1) OR (B0 and B1) or (C0 and C1) after 6ns; d. PAR after 12ns <= PAR XOR DI_; 186.Following keyword not used for time dimensions a. after b. wait on c. wait until d. case 187.Following statement is incorrect time dimension a. wait on clock for 20ns; b. wait until sum>100 for 50ns; c. wait on clock or 20ns; d. wait on clock until sum>100ns; 188.The _ _ _ _ _ _ _ _ _ _ _ mechanism makes it possible to simulate the operation of concurrent processes even through the simulator runs on a single computer with a single thread of execution a. delta delay b. event list c. case d. while 189.Following statement incorrect time dimension a. wait on sensitivity _ list; b. wait or sensitivity _ list; c. wait until Boolean _ expression; d. wait for time expression; 190.Following statement incorrect time dimension WWW.UandiSTAR.org a. wait on A, B, C; b. wait until A=B; c. wait for 10ns; d. wait or A, B, C; WWW.UandiSTAR.org Page 10 100% free SMS: ON<space>UandiStar to 9870807070 for JNTUK Alerts,GATE,CAT… Alerts,Hacking Tips/Tricks… more directly to ur mobile