Control of the Dynamic Voltage Restorer to Improve
Voltage Quality
Samet Biricik a,b, Shafiuzzaman K. Khadem c, Soydan Redif b, Malabika Basu a
a
b
School of Electrical & Electronic Engineering, Dublin Institute of Technology, Ireland
Department of Electrical & Electronic Engineering European University of Lefke, North Cyprus
c
School of Engineering, Trinity College Dublin, Ireland
Abstract- In this study a method is proposed in order to
improve the voltage compensation performance of Dynamic
Voltage Restorer by using Self Tuning Filter. The proposed
control method gives an adequate voltage compensating even for
50% voltage sag and distorted voltage conditions. The proposed
DVR control method is modelled using MATLAB/Simulink and
tested both in off-line and real-time environment. Results are
then presented as a verification of the proposed method.
The remainder of this paper has been organized as follows.
The proposed control method with STF is discussed in details
in section II. Development of a three phase system in
MATLAB and results obtained by the simulation in presented
in section III. Section IV shows the part of the results from
real-time experimental result to verify the performance of the
proposed method in real environment.
II.
Keywords - DVR; voltage sag; voltage harmonics;
STF.
I.
INTRODUCTION
Voltage distortions and fluctuations are frequently
encountered in the weak grid network systems. The distorted
currents cause non-sinusoidal voltage drops and as a result the
network voltages become distorted. On the other hand, voltage
sag and swell problems are usually caused by short-circuit
current flowing into a fault. Voltage sag and swell are defined
as a sudden reduction or rise of grid voltages which may vary
from 10% to 90 % during sag and 110% to 180% during swell
of its nominal value [1]. Therefore, dynamic voltage restorer
(DVR) is used to solve such power quality problems. DVR
was introduced by the end of the 1980s. It operates mainly as
voltage regulator and as a harmonic isolator between the loads
and the utility system. This type of filter is able to compensate
the voltage related problems in the distribution system [2].
They can also be used to filter harmonic voltages, reduce
voltage-flicker and regulate line voltage. However, DVR is
less preferred to be used in industrial applications. Because it
has to handle high load current which increases the
losses.
The DVR is represented as a controllable voltage source. It is
controlled to present zero impedance at the fundamental
frequency and a high resistance to the source or load
harmonics.
In order to improve the performance of the DVR a selftuning filter (STF) is used in this study. Presently, the STF is
used as a part of filtering current harmonics in the controller
of the three phase shunt active power filter (APF) [3- 9] and
hybrid active power filter [10-11]. But till now, STF has not
yet been applied to the control of DVR. In this study, we
propose use of STF algorithm to increase the control
performance of the DVR in the case of both non-ideal grid
voltages and unbalanced voltage sag. Fig.1 shows the studied
DVR topology.
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PROPOSED CONTROL METHOD
The main aim of the DVR is to dynamically compensate
the voltage sag/swell along with the voltage harmonics.
Therefore, any kind of distortion in the instantaneous and
fundamental supply voltage ( ) is defined by the error
voltage ( ) which is calculated as
∆
1
1
1
(1)
230
230
230
is
where a, b, c subscripts represent the three phases.
the rms of the supply voltage and 230 V is the standard or
desired rms value of the supply voltage. The STF usually
requires two inputs which should contain the phase and
amplitude information of any system. Therefore, the
calculated error signal is then transformed into two phase
coordinate system using the Clarke (or α-β) transformation:
2 1
3
0
1
2
√3
2
1
2
√3
2
(2)
The per unit α-β reference voltage for the compensation
can then be obtained as:
230√2
(3)
230√2
In order to obtain undistorted and balanced waveform for
the control circuit, the α-β of the distorted grid voltage is
processed through the STF. In [3], the transfer function of the
STF is obtained by integration of the synchronous reference
frame and it is defined as:
H (s) =
Vxy (s)
U xy (s)
s + jω
s 2 + ω2
= Kx
(4)
where
V xy (t ) = e j ωt ∫ e − j ωt U xy (t )dt
(5)
The STF has a magnitude and phase response that is
similar to those of a general band-pass filter. Apart from the
integral effect on the input magnitude, the STF does not alter
the phase of the input, i.e. the input Uxy(s) and output Vxy(s)
have the same phase. Note that in order to have unit
magnitude, i.e. |H(s)| = 0 dB, a constant KX is incorporated in
to (4) [3], that is,
H (s) =
Vxy (s)
U xy (s)
= KX
(s + K X ) + jω
(s + K X ) 2 + ω 2 .
(6)
The signals generated by (3) are then transferred to the
STF to generate the two phase instantaneous un-distorted
signals in terms of α-β.
.
(7)
.
Then, the obtained un-distorted and balanced two phase
voltages can be converted to the three phase system by using
inverse Clark transformation as given by,
0
√3
3
2
2
√3
2
1
1
2
1
2
The phase information is also obtained by transferring the
generated per unit error signals to the Phase-Locked-Loop
(PLL). This angular position is then used to calculate the
required un-distorted and balanced three phase reference
voltages for the point of common coupling (PCC). This
reference voltage is given as
2
. sin . √3. 230
3
2
.
3
1
sin
2
1
√3. . cos
2
√3 . 230
2
.
3
1
sin
2
1
√3. . cos
2
√3 . 230
Extracted reference signal for the PCC is then used to
generate the reference signal for the sag/swell compensation.
If there is no sag/swell/distortion then this signal (error = 0) is
feed-forwarded to the PWM block to generate the gate pulses.
Otherwise, this signal is compared with secondary voltage and
then transferred to the proportional integrator (PI) controller to
generate the required compensation current for the DVR
controller.
This reference current is then compared with the actual
value to get the error in compensating current. A proportional
gain is used to convert this error current to the appropriate
voltage signal which is then added to the feed-forwarded
signal and passed to the PWM block to generate the gate
pulses. Fig. 2 shows the block diagram of the proposed
controller.
(8)
Fig.1. Circuit Topology of the Dynamic Voltage Restorer
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(9)
Fig.2. The block diagram of the DVR and proposed control method
a-)
b--)
c-)
d--)
Fig.3. a-) Three phase unbalanced and distoorted (non-ideal) grid voltages, b-) Injected three phase voltaages by the DVR, c-) Three phase
balanced and un-distorted (ideal) volttages at the load terminal. d-) Load (current) variation under ideal voltage condition
III.
SIMULATION RESULTS
In order to evaluate the performance of the proposed
control method, a power system structure has been developed
in MATLAB/Simulink. The performance of the proposed
control method is investigated for the case of
o 50% three phase
voltage sag with linear and non-linear load combinations.
c
Symbol
vS
f
Load 1
Load 2
Load 3
Lc
Udc
fs
TABLE I: PARAMETERS OF THE STUDIED
D SYSTEM
Value
Quantity
Ideal Grid L-N rms Voltage
230 V
Grid Frequency
50 Hz
4Ω, 10 mH
Linear Load Res. and Ind.
24Ω, 15 mH
Non-Linear Load Res. and Ind.
7.5Ω, 45 mH
Non-Linear Load Res. and Ind.
0.3 mH
Filter Inductor
600 V
dc- link Source Voltage
10 kHz
Switching Frequency
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The proposed method, load
l
change has been also
considered from 0.15s -0.20s. Load 1 is used to draw only
active and reactive power from the grid. However, Load 2 and
Load 3 draw both distorted cuurrents and reactive power. The
block diagram representation of the simulated power and
control systems are shown inn Figs 1 & 2 and the system
parameters used in the simulaations are calculated from [12]
and are given in Table I.
Simulation is performed for the following cases and
conditions;
A. Grid side disturbances
The system is operated unnder the non-ideal grid voltage
condition (including harmonicss and unbalances) and it can be
observed from Fig 3 (a). Thhe Total Harmonic Distortion
(THD) of the grid voltages in each
e
phase are found as 9.06 %,
9.65 % and 7.39 %. The rms values
v
of the unbalanced phase
voltages are 229.4V, 231.9V, 225.4V.
2
The simulation is run
for 0.3 sec and 50% sag is applied between 0.05 to 0.1 sec. As
a result the grid voltages are reduced to 1166.9 V, 116.9 V and
110.4 V. The performance of the proposed method
m
is observed
in Fig 3 (b) where DVR injects the required voltage to
compensate the voltage sag. The balancee and undistorted
voltage at the load side is shown in Fig 3(cc). By this method,
the voltage harmonics on the load terminall are reduced from
10 % around to 4 % and voltages are improvved from 116 V to
225 V.
Because, of the
losses on the injection
transformers (series transformers) 5 V iss dropped on the
injection transformer. Moreover, the load current harmonics
create additional voltage harmonic on
o
the injection
transformers impedances.
B. Load side disturbance
The THD of the load currents in eachh phase are found
17.91 %, 16.82 % and 17.68 % while the currrents are 107.9 A,
108.9 A, 107 A. Voltage change on the gridd side is created by
reducing the grid current to 58.48 A, 58.75A
A, 58.58 A. This is
observed from 0.15 to 0.20 sec. However, thhe load groups are
not affected from the voltage disturbance (see Fig 3 (d)). It is
found that in full load condition, the total active
a
power (P) is
70 kW; the total reactive power (Q) is 26 kVAr. During the
voltage sag condition, the consuming acttive power (P) is
reduced to 38 kW; the total reactive powerr (Q) is reduced to
12 kVAr on the grid side (see Fig. 4, betw
ween 0.05 to 0.10
sec). However, the proposed methhod dynamically
compensated the active and reactivate poweer cause of voltage
injection as presented in Fig. 5. As a result, the load groups do
not observed any power changes during the voltage sag on the
grid (see Fig.6, between 0.05 to 0.10 sec.)). In this study we
also verified the system performance duringg the load changes.
The load variation is applied between 0.15 too 0.20 sec. As can
be seen in Figs. 4, 5 & 6 the performance of the system is not
affected during the load variation.
Fig. 6. Consumed Active and Reaactive powers from the load side.
IV.
RFORMANCE STUDY
REAL-TIME PER
The proposed control methood and power system then have
been modelled in Simulink usinng RT-LAB real-time platform
and associated tools to observee the performance in a real time
environment. The system is then tested in software-in-the-loop
(SIL) with hardware synchronization mode, which is similar
to the hardware-in-the-loopp (HIL) test giving due
consideration for delay in the real time measurement of actual
signals and implementation of the
t control signals [13].
Fig. 7 shows the real-tim
me laboratory setup using the
OPAL-RT (OP5600) platfo
form, which manages the
communications between the CPUs, FPGA architecture and
the console PC (from whicch the global simulation is
controlled).
Fig. 7. Experimental seetup with the OPAL-RT
Fig. 4. Consumed Active and Reactive powers from the grid Side.
Figs. 8, 9 & 10 shows thhe real-time performance of the
proposed method to obtain undistorted and balance grid
voltage at PCC. Fig. 8 show
ws the grid voltage waveforms
through the real-time scope which are unbalanced and
distorted. The injected voltagee by the DVR in real-time is
observed in Fig. 9. Fig. 10 show
ws the undistorted and balanced
three-phase voltages at the loaad terminal which verifies the
performance of the proposed method.
m
Fig. 5. Injected Active and Reactive powerrs by the DVR
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REFERENCES
Fig. 8. Distorted and unbalanced grid voltages (93 V/div).
Fig. 9. Injected voltages by the DVR (93 V/div).
Fig. 10. The obtained un-distorted and balanced voltages at PCC
terminal (93 V/div).
V.
CONCLUSION
This paper shows the effectiveness of implementing STF
in the traditional control method of DVR to compensate the
distorted and unbalanced grid voltage condition as well as
sudden drop or increase in grid voltage. Performance of the
improved method is tested both in off-line and real-time
mode. Results show that the proposed method can
significantly improve the performance of the DVR and thus
the load does not sense any kind of grid voltage disturbances.
Moreover, the grid voltage harmonics are effectively
suppressed on the load terminal.
'978-1-4799-5115-4/14/$31.00 ©2014 IEEE'
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