TECHNICAL ARTICLE
Kevin M. Tompsett
Senior Applications Engineer,
Analog Devices, Inc.
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DESIGNING SECOND STAGE
OUTPUT FILTERS FOR
SWITCHING POWER SUPPLIES
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Input
VSW
Current
A
On-Time
Output
B
Current
Load
Input
Current
VSW
Off-Time
Output
Load
Areas Are Same
in Steady State
VSW
VOUT
VIN
TON
T
These days switching power supplies are nearly ubiquitous and used
throughout every electronic device. They are valued for their small size,
low cost, and efficiency. However, they have the major drawback in that
their outputs can be noisy due to the high switching transients. This
has kept them out of high performance analog circuits where linear
regulators have ruled the roost. It has been shown that in many applications
an appropriately filtered switching converter can replace a linear regulator
for production of a low noise supply. Even in those demanding applications
where an extremely low noise supply is required, there is probably a switching
circuit somewhere upstream in the power tree. Therefore, there is a need to be
able to design optimized, damped multistage filters to clean up the output
from switching power converters. In addition, it is important to realize how
the filter design will affect the compensation of the switching power converter.
In this article, boost circuits will be used for the example circuits, but
the results will be directly applicable to any dc-to-dc converter. Shown
in Figure 1 are the basic waveforms in a boost converter in constantcurrent mode (CCM).
B
A
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TOFF
The issue that makes an output filter so important for a boost or any of the
other topologies with discontinuous current mode is the fast rise and fall
in the current time in Switch B. This tends to excite parasitic inductances
in the switch, the layout, and the output capacitors. The result is that in
the real world the output waveforms look much more like Figure 2 rather
than Figure 1, even with a good layout and ceramic output capacitors.
ISWA
ISWB
Fast Current
Changes
IL
VOUT
Figure 2. Typical measured waveforms of a boost converter in DCM.
Figure 1. Basic voltage and current waveforms for a boost converter.
Visit analog.com
2
: The ESR of the chosen output capacitor.
ESR
Designing Second Stage Output Filters for Switching Power R
Supplies
FSW : The switching frequency of the converter.
CRIP : The output capacitor calculated assuming all of ΔIPP rip
flows into it.
The switching ripple (at the switching frequency) caused by the change in
charge of the capacitor is very small compared to the undampened ringing
of the output switch, which we will refer to as output noise. Generally, this
output noise is in the 10 MHz to 100+ MHz range, well beyond the selfresonant frequency of most ceramic output capacitors. Therefore adding
additional capacitors will do little to attenuate the noise.
TRAN
: The change in VOUT when ISTEP applied to the output.
ΔVOUT
ISTEP : An instantaneous change of the output load.
TSTEP : The approximate response time of the converter to an
instantaneous change in the output load.
There are a couple of reasonable choices for different types of filters to
filter this output. This article will illustrate each type of filter and give
a step-by-step process to a design. The equations are not rigorous and
some reasonable assumptions are made to simplify them somewhat.
There is still some iteration required since each component will affect
the values of the others. The ADIsimPower design tools get around this
problem by using linearized equations for component values, like cost
or size, to do an optimization before actual components are selected,
and then optimize the outputs once real components are chosen from the
database of thousands of parts. However, for a first pass at a design,
this level of complexity is not necessary. With the provided calculations
and possibly using a SIMPLIS simulator like the free ADIsimPE™
, or some
bench time in the lab, a satisfactory design can be found with a minimal
amount of effort.
Fu : The crossover frequency of the converter. For a buck it is generally
FSW ⁄10. For a boost or buck boost type converter it is generally about a
third of the location of the right half plane zero (RHPZ).
The simplest type of filter is just an RC filter as shown attached to the
output of a low current ADP161x-based boost design shown in Figure 3.
This filter has the advantage of low cost and will not need to be damped.
However, due to power dissipation it is only useful for very low output
current converters. For this article, ceramic capacitors with small ESR
are assumed.
Design Process for an RC Second Stage
Output Filter
Before designing the filter, consider what is achievable with a single stage
filter RC or LC filter. Typically with a second stage filter it is reasonable
to get the ripple down to a few hundred μV p-p and the switching noise
down below 1 mV p-p. A buck converter can be made somewhat quieter
since the power inductor provides significant filtering. These limitations
are because once the ripple is down in the μV the component parasitics,
and noise coupling between filter stages starts to become the limiting
factors. If even quieter supplies are required, then a third stage filter can
be added. However, switching power supplies do not generally have the
quietest references and also suffer from jitter noise. These both result in
low frequency noise (1 Hz to 100 kHz) that cannot be easily filtered out.
Therefore, for extremely low noise supplies it may be better to use a single
second stage filter and then add an LDO to the output.
Step 1: Choose C1 based on assuming the value output ripple at C1 is
approximately ignoring the rest of the filter; 5 mV p-p to 20 mV p-p
is a good place to start. C1 can then be calculated using Equation 1.
C1 =
RIP
: The approximate out voltage ripple at the switching frequency
ΔVOUT
of the converter.
RESR : The ESR of the chosen output capacitor.
FSW : The switching frequency of the converter.
L1
VIN
TRAN
: The change in VOUT when ISTEP applied to the output.
ΔVOUT
ISTEP : An instantaneous change of the output load.
SS
COMP
TSTEP : The approximate response
CC1 time of the converter to an
FREQ
FB
instantaneous change in the output load.
RC1
VIN
Fu : The crossover frequency of the converter. For aENbuck it is generally
FSW ⁄10. For a boost or buck boost type converter itGND
is generallySW
about a
third of the location of the right half plane zero (RHPZ).
CV5
RF2
RF1B
(1)
2
Step
C22can
then
Equation 2 through
a =3:AR
R2LOAD
C 21ωbe4 +calculated
AR2LOADωfrom
(3) Equation 6.
A, a, b, and c are just intermediate values to simplify calculation and have
ω2C1 –These
2ARLOAD
C1ω2 assumes R <<(4)
= 2AR2LOAD
nobphysical
meaning.
equations
RLOAD and the ESR
IPP
forCeach
capacitor
is
small.
These
are
both
very
good
assumptions
and
=
(1)
RIP+ A – 1
ω2C
c 1= AR
(5)
R
8F
ΔV
LOAD
1 –
OUT
SW error.
PP ESRbe the same or larger than C1. The ripple
introduce
little
C2ΔI
should
in Step 1–bcan
be adjusted
+ √b2
– 4ac to make this possible.
C2 =
(6)
RIP
2a
ΔVOUT
(2)
A=
ΔIPP RLOAD
ΔIPP: The approximate peak-to-peak current coming into the output
filter. For the calculations we assume that this is sinusoidal. The value
will depend on the topology. For a buck it is the peak-to-peak current
in the inductor. For a boost converter it is the peak current in Switch B
(often a diode).
CRIP : The output capacitor calculated assuming all of ΔIPPVrip
IN
flows into it.
IPP
RIP
8FSW ΔVOUT
– ΔIPP RESR
Step 2: R can be chosen based on power dissipation. R must be much
RIP
larger thanΔV
RESR
for the capacitors and for this filter to be effective. This
OUT
(2) 50 mA or so.
A =the range of output currents to something less that
limits
ΔIPP RLOAD
Before diving into a more detailed design process for each type of filter,
some values that will get used in the design process for each of the types
of filters are defined as follows:
ADP161x
a = AR21R2LOAD(C
C 21ω+4 C+2)AR2LOADω2
FRES ≈
2�2 √ L
2 C1C2
ωFILT
C1 – 2ARLOADC1ω2
b = 2AR
LOAD
(3)
(7)
(4)
+A–1
c = ARLOADω2C1ΔI
PP
C1 =
RIP
–bSW
+ΔV
√b2
– –4ac
8F
ΔIPP RESR
OUT
C2 =
2a
(5)
(8)
CBW =
D1
FRES ≈
ISTEP
�F
– I)STEP RESR)
(C + C
1 u(ΔV
2
RIP
1
R OUT
2� √ LFILT C1C2
C1
C2
(6)
(9)
VOUT
(7)
RLOAD
2(C1 + C2)
ωO =
C2PP
)
(LFILT C1ΔI
√
C1 =
RIP
8FSW ΔVOUT
– ΔIPP RESR L

FILT 
R
 LOAD LFILT (C1 + C2) – ω 

O 
RFILT =
I
+ C2)
RLOAD(C1STEP
CBW =
RIP
–L C
�Fu(ΔVOUT
ωO– ISTEP RESR) FILT 1
(10)
(8)
(11)
(9)
CSS
R 1 +ωICPP2)
L 2(C
– LFILT ω – RLOADC1RFILT ω (12)
= FILT LOAD
(10)
aω=
O
RIP
CC)
(L
√ ΔV
FILT
OUT 1 2
LFILT 
R
I
 ΔVOUT
O 
RFILT =
2
RLOAD(C1 + C2) + RLOADC1LFILT ω
– LFILT C1
ω –ωRO R
C L ω3
c=R R
R

R LOADL PP (C + C ) –

2
+2 R
 LOAD
= FILT
FILT –
1filter
Figure 3. ADP161x low output current boost converter bdesign
with
anRIP
added
RCR
the
output.
FILT on
FILT
ωLFILT C1ω ,
(13)
(11)
(14)
Visit analog.com Damping
Technique 1
RFILT
Damping
Technique 2
L1
VIN
D1
VIN
CD
Damping
Technique 3
LFILT
C1
RD
FB
RC1
FREQ
ADP1621ARMZ
COMP
CC1
RLOAD
RE
IN
SDSN
GND
CE
C2
VOUT
CS
RS
PIN
GATE
Q1
PGND
RFREQ
RF2
RF1
Figure 4. ADP1621 with an output filter with several different damping techniques highlighted.
Theb feedback
or after
2
C1 –before
2ARLOAD
C1ω2the filter inductor.
= 2AR2LOADisωtaken
(4)The thing that is
most surprising to people is how much the open-loop Bode plot changes
2
even
theωfilter
C1 +isAnot
– 1“in” the feedback loop. Since
c =when
ARLOAD
(5) the control loop is
affected with or without the filter in the feedback loop, one might as well
–b +for
√b2
– 4ac
compensate
it appropriately.
In general this will mean
C2 =
(6) scaling back the
target
crossover2afrequency to a maximum of a fifth to a tenth of the filter
resonant frequency (FRES).
FRES ≈
C1 =
(C1 + C2)
1
2� √ LFILT C1C2
ΔIPP
RIP
8FSW ΔVOUT
– ΔIPP RESR
(7)
(8)
Gain
The design process for this type of filter is iterative in nature since each
component selection drives the selection of the others.
40
20
0
–20
–40
–60
–80
–100
Gain (Feedback Before Filter)
Gain (Feedback After Filter)
C1 10
=
100
Phase (Degree)
For higher current supplies it is beneficial to replace the resistor in the pi
filter with an inductor as shown in Figure 4. This configuration gives very
good ripple and switching noise rejection in addition to low power loss.
The issue is that we have now introduced an additional tank circuit that
can resonate. This can result in oscillations and an unstable power supply.
Therefore, the first step to designing this filter is to choose how to damp
the filter. Figure 4 shows three viable damping techniques. Adding RFILT has
the advantage of adding little extra expense or size. The damping resistor
typically has little to no loss and can be small for even large power supplies.
The drawback is that it significantly reduces the effectiveness of the filter
by reducing the parallel impedance with the inductor. Technique 2 has the
advantage of maximizing filter performance. If an all ceramic design is
desired, RD can be a discrete resistor in series with a ceramic capacitor.
Otherwise a physically large capacitor with a high ESR is required. This
additional capacitance (CD) can add significant cost and size to the design.
Damping Technique 3 looks very advantageous since the dampening
capacitor CE is added to the output where it might help somewhat with
transient response and output ripple. However, this is the most expensive
technique since the amount of capacitance required is much larger. In
addition, the relatively large amount of capacitance on the output will lower
the frequency of the filter resonance, which will reduce the achievable
bandwidth of the converter—therefore Technique 3 is not recommended.
For the ADIsimPower design tools we use Technique 1 because of the low
cost and relative ease of implementing it in an automated design process.
IPP
Another
needs to be dealt with is compensation.
It may be
C1 = issue that
(1)
RIP
RESR always better to put the filter inside the
8FSW ΔVOUT
counterintuitive,
but–it ΔI
is PP
almost
feedback loop. This is because putting it in the feedback loop helps damp
the filter somewhat,
eliminates dc load shift and the series resistance of
RIP
ΔVOUT
theAfilter,
(2) ringing. Figure 5
= and gives a better transient response with less
ΔIPPBode
RLOADplot for a boost converter with an LC filter output added
shows the
to athe= output.
AR2R2LOADC 21ω4 + AR2LOADω2
(3)
A=
0
IPP
20 40 RIP
200 400
R
8F
ΔVOUT100– ΔI
SW
PP ESR
1k 2k 4k
10k 20k(1)
40k 100k
Frequency (Hz)
RIP
ΔVOUT
ΔIPP RLOAD
400k
1m
400k
1m
(2)
–100
a = AR2R2LOADC 21ω4 + AR2LOADω2
–200
Phase
Margin (Feedback Before
Filter)
2
ω2C1 –(Feedback
2ARLOADAfter
C1ω2Filter)
b = 2ARPhase
–300
LOAD Margin
40
ω2C1100
+ A200
– 1400
c =10AR20
LOAD
(3)
(4)
1k 2k 4k
10k 20k(5)
40k 100k
Frequency (Hz)
Figure 5. Phase
and gain
plots for a boost converter with an LC filter on the output.
–b + √b2
– 4ac
C2 =
(6)
2a
Design Process for an LC Filter Using Parallel
Resistor Damping (Technique 1 in Figure 4)
+ C2)
1 C(C
1
Step
1: ≈Choose
1 as if there was not going to be an output
FRES
(7) filter on the
2�
C C2 is a good place to start. C1 can then be
L
output. 5 mV √
to 20
FILTmV1 p-p
calculated using Equation 8.
C1 =
ΔIPP
8FSW ΔV
RIP
OUT
– ΔIPP RESR
(8)
Step 2: Select the inductor LFILT. Based on experience, a good value is
ISTEP
between
2.2
μF. The inductor should be chosen
CBW = 0.5 μF toRIP
(9) for a high self�Fu(ΔVOUT(SRF).
– ISTEP
RESR)inductors have larger SRFs, which means
resonant
frequency
Larger
they are less effective for high frequency noise filtering. Smaller inductors
will not have as much effect on ripple and will require more capacitance.
+ C2) frequency is the smaller the inductor can be.
2(Cswitching
The higher the
1
ωO =
(10)
When
comparing
with the same inductance, the part with
C
C inductors
)
(L
√ FILT two
1 2
higher SRF will have lower interwinding capacitance. The interwinding

LFILT 
R acts Llike a(C
capacitances
circuit
the filter for high frequency noise.
+C
) – around
 LOAD FILT short
1
2
ωO 

(11)
RFILT =
RLOAD(C1 + C2)
– LFILT C1
ωO
a=
LFILT RLOADωIPP
– LFILT ω – RLOADC1RFILT ω (12)
RIP
ΔVOUT
R
R
I
3
4
LOAD
1I
1
RIP
PP
– ΔIPP RESR
C1 = 8FSW ΔVOUT
(1)
–b + √b2 – 4ac
RIP
– ΔIPP RESR
8F
ΔV
–b
+
√b2
–
C2 =
(6)
OUT 4acStage
SW Second
Designing
Output Filters for
C2 =
(6)Switching Power Supplies
2a
2a
RIP
ΔVOUT
(2)
A = ΔV RIP
ΔI
R
OUT
LOAD
Step
3: As PP
described
previously, adding the filter will affect
Step 8: When1choosing
C2) components to match the calculated values,
(C1 +actual
(2) the compensaA=
ΔIPP
C2) 2 the
(C21 +by
1RR2 LOAD
FRES ≈to derate the capacitances of any ceramic capacitors
(7)
2converter
4 reducing
2 achievable crossover frequency (Fu).
tionaFof
remember
to account
= the
AR
C
ω
+
AR
ω
(3)
≈ LOAD 1
(7)
2� √ LFILT C1C2
LOAD
2 2
2 conversion,
2 maximum achievable F is the lesser
C4 1+C2AR2 ω
ForaaRES
the
for
dc
bias!
√ LCFILT
=current-mode
AR2�
RLOAD
ω
(3)
u
1
LOAD
2
2
ω2C1 –frequency,
2ARLOADCor1ω1/5
b = 2AR
of 1/10
of the
switch
the FRES of the(4)
filter as calculated
LOAD
2
2
2
As stated previously,ΔI
Figure 4 gives two viable techniques for damping
ω C1 – 2ARmost
C1ω loads do not (4)
b = 2ARLOAD
in Equation
7. Fortunately,
require an excepLOAD analog
PP
2 ΔI
(8)
the filter.
If
instead
of
choosing
a parallel resistor, a capacitor
CD can
C
=
ω
C
+
A
–
1
c
=
AR
(5)
PP
1
RIP
LOAD
1
tionally
transient
response. Equation 9 calculates
(8)the approximate
C1 = high
8F
–filter.
ΔIPPThis
RESRwill add some cost, but it provides the
ΔVOUT
2 RIP
SW
be
chosen
to
damp
the
ω
C
+
A
–
1
c = AR8F
(5)
–
ΔI
R
ΔV
LOAD
1
OUT(CBW) required
output capacitance
–b SW
+ √b2
– 4ac PP ESR on the output of a converter to provide
best filter performance of any technique.
= –b + √b2
(6)
forCa2 specified
transient
–
4accurrent step.
2a
ISTEP
C2 =
(6)
2a ISTEP
CBW = Process
(9)
Design
RIP for an LC filter Using an RC
CBW =
(9)
�Fu(ΔVOUT – ISTEP RESR)
RIP
�Fu(ΔVOUT
– ISTEP RESR)
Damping Network (Technique 2 in Figure 4)
(C1 + C2)
1
Step
4: ≈
Set1C2 as(C
the+minimum
of
C
and
C
.
FRES
(7)
Step 1: As in the previous topology, choose C1 as if there were not going
BW
1
C2)
1
FRES ≈ 2� √ LFILT C1C2
(7)
+C
2(C
to be an output
filter.
102) mV p-p to 100 mV p-p is a good place to start,
1
2�2(C
C2
+the
CC2)1approximate
Step 5: Calculate
damping filter resistance using
√ L1 FILT
ωO =
(10)
depending
on
the
final
target
output ripple. C1 can then be calculated
C
C
)
(L
ω
=
(10)
√
FILT 1 2
O
Equation
and
Equation
C C ) 11. These equations are not absolutely accurate,
√10(L
FILT 1ΔI2
using Equation
8. C1 can be smaller in thistopology than the previous
PP thing to a closed form solution without the need

butCthey
the closest
LFILT 
(8)
= are
ΔIPP
R

1
LFILT 
topologies because
filter
RIP
Lthe
(C
+ isC2more
) – effective.

8F
–
ΔI
R
ΔV
LOAD
FILT
1

to C
use
extensive
algebra.
The
ADIsimPower
design
tools
calculate
R
by
(8)
ωO 
=
FILT
OUT
SW
PP
ESR) –
L
(C
+
C
R



1
LOADRIP
FILT
2
ωO  (OLTF) of the converter with the
8FSW
– ΔI1PP
RESR
ΔV
(11)
R
=
OUT
calculating
the
open-loop
transfer
function
Step 2:FILT
As in theRprevious
(11)
R
=
(C1 topology
+ C2) an inductor between 0.5 μH to 2.2 μH is
LOAD
(C
+
C
)
filterFILT
and withRthe
inductor
shorted
out.
R
values
are
then
guessed
until
–
L
C
chosen.
1
μH
is
a
good
value
for
converters
between
500
kHz and 1200 kHz.
FILT
LOAD I1
2
FILT 1
ωO
STEP
– LFILT
Cfilter
1
= of the converter
(9)
theCpeak
OLTF
with
the
is
only
10
dB
above
the
OLTF
I
RIPω
BW
O
STEP
– ISTEP RESR)
Step 3: As before, C2 can be chosen from Equation 16, but with RFILT set to
= �Fu(ΔVOUT
(9)
of C
the
RIPthe inductor shorted. This technique can be used in a
BWconverter with
�Fu(ΔVOUT
– ISTEP RESR)
something large like 1 MΩ since it will not be populated. The reason this is
simulator like ADIsimPE or in the lab using a spectrum analyzer.
ωIPPC having an additional capacitor is that in order to
LFILT Rdespite
LOAD
the same
1– L
LFILT RLOADωIPP
ω – RLOADC1RFILT ω (12)
a = value
RIP
–
L
ω
–
R
C
R
ω
2(C
+
C
)
a=
(12)
ΔVOUT RD will FILT
provide good damping,
be made large enough that CD will not signifiFILT
LOAD 1 FILT
1
2
RIP
ΔV
ωO =
(10)
2(COUT+ C )
cantly reduce the ripple. Set C2 as the minimum of the calculated C2 value,
ωO = √ (LFILT1 C1C22)
(10)
R RLOADIPP
2
CI C )
R√FILT(LRFILT
CBW and
It can RIP
be useful
this+ point
return
1 and adjust the
– RatFILT
RFILTto
LFILT
C1ωto
, Step
(13)
b = C1.FILT
LOAD 1PP 2
2


L
–
R
+
R
L
C
ω
,
ΔVOUT
(13)
b=
FILT
RIP
FILT
FILT FILT
R
 1
ripple
assumed
on
C
to
get
a
calculated
C
that
is
closer
to CBW and C1.
L
(C
+
C
)
–
ΔV
1
2
 LOAD

Lω
1
2
OUT FILT
+ RLOADC1LFILT ω2
FILT


2
O L
– LOAD
C
ω

(11)
RFILT = RLOAD LFILT (C1 + C2+) R
ωO 1  FILT
Step 4: CD should be set to the same value as 3C1. In theory you can achieve
c = RFILT RLOAD ω – RFILT RLOADC1LFILT ω
(14)
(11)
RFILT = RLOAD(C1 + C2)
3
–
L
C
more damping
of the filter using a larger capacitance, but it needlessly adds
ω
–
R
R
C
L
ω
c = RFILT RLOAD
(14)
C2)LOAD 1FILT
RLOAD(C
FILT 1
ω1O+FILT
– LFILT C1
to thed cost
size,
ω
= –Rand
R and
ω2 it can reduce converter bandwidth.
(15)
LOAD FILT
d =6:–R
ω2 O
(15)
Step
C2LOAD
can Rnow
FILT be calculated using Equation 12 through Equation 15.
Step
5:
R
can
be
calculated
from
Equation
17.
F
is
calculated
using
D
RES
a, b, c, and
used to simplify Equation 16.
a2 + b2 the presence of C . This is a good approximation
LFILTd2Rare
2 ωIPP
LOAD
Equation
7,
ignoring
D
+
b
a
(16)
C
=
a ==L R RIPωI – LFILT ω – RLOADC1RFILT ω (12)
2
c2 + c2 large enough that CD will have little effect on the
(16)
C
PP
√ typically
2 LOAD
since Rd is
– LFILT ω – RLOADC1RFILT ω (12)
a 2= √FILTcΔV
+ OUT
c2
RIP
ΔV
location of the filter resonance.
R R OUTIPP
2
–
R
+
R
L
C
ω
,
(13)
b = R FILT R LOAD
1
RIPI
FILT
FILT FILT 1
PP
1LOAD
(17)
RD =
OUT
– RFILT + RFILT LFILT C1ω22, (13)
bR= = FILTΔV
RIP
F
�C
(17)
+ RLOADC1LFILT ω
1 RES
D
FOUT
�CΔV
1 RES
+ RLOADC1LFILT ω2
Step 6: Now that both CD and RD have been calculated either a ceramic
c = RFILT RLOAD ω – RFILT RLOADC1LFILT ω3
(14)
c = RFILT RLOAD ω – RFILT RLOADC1LFILT ω3
(14)
capacitor with a series resistance can be used, or a tantalum or similar
d = –RLOAD RFILT ω2
(15)
capacitor with large ESR should be chosen that matches the calculated
d = –RLOAD RFILT ω2
(15)
specifications.
a 2 + b2
(16)
C2 = a22 + b22
Step 7: When choosing actual components to match the calculated values,
(16)
C2 = √ c2 + c2
remember to derate the capacitances of any ceramic capacitors to account
√ c +c
for dc bias!
Step 7: Step 31 through Step 5 should be repeated until a well damped
(17)
RD =
1
Another filter technique is to replace the L in the previous filter with a
filter
that meets the required ripple
RES
(17) and transient
RDdesign
= �Cis1Fcalculated
ferrite bead. However, this arrangement has many drawbacks that limit
F
�C
specifications.
It should be noted that these equations ignore the dc
1 RES
its effectiveness at filtering switching noise and does almost nothing for
series resistance of the filter inductor RDCR. This resistance can be quite
switching ripple. First is saturation. The ferrite bead will saturate at a very
significant for lower current supplies. It improves filter performance
low level of bias current, meaning that the ferrite will give much lower
by helping to dampen the filter, which increases the required RFILT and
increases the impedance of the filter. Both effects can significantly improve impedance than shown in the zero bias curves shown in all data sheets.
It may still need damping since it is still an inductor and therefore can
the performance of the filter. It can therefore be very helpful for low noise
resonate with the output capacitance. However, now the inductance is
requirements to trade off a small amount of power loss in LFILT for improved
variable and poorly characterized in the very minimal data provided in
noise performance. Core loss in LFILT also helps to attenuate some of the
most data sheets. For this reason ferrite beads are not recommended for
high frequency noise. Therefore, high current-powdered iron cores can be a
use as a second stage filter, but can be used downstream from one to
good choice. They also tend to be smaller and cheaper for the same current
further reduce very high frequency noise.
capability. ADIsimPower of course factors in both the resistance of the filter
inductor in addition to the ESR of the two capacitors for maximum accuracy.
Visit analog.com Conclusion
This article has laid out several output filter techniques for switching
power supplies. For each topology, a step-by-step design process has
been devised to reduce the amount of guess and check required for filter
design. The equations have been simplified somewhat so that they are
useful to an engineer looking to do a quick design by understanding
what is achievable from a second stage output filter.
About the Author
Kevin M. Tompsett is a senior applications engineer for Power
Management Products in ADI’s Customer Applications Group in
Fort Collins, Colorado. He earned his B.A. in 2000, his B.E. in 2001,
and his M.S. in 2004, all from Dartmouth College and Thayer School
of Engineering. He has been with Analog Devices since 2007.
He can be reached at kevin.tompsett@analog.com.
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