CS 370 Computer Architecture Syllabus Fall 2014

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CS 370 Computer Architecture Syllabus

Fall 2014

1.

Credits and contact hours: 3 Units; MW 4:00-5:15 pm

2.

Instructor: Tao Xie, office hours: Monday & Wednesday: 11:00 am-12:00pm or by appointment, office: GMCS 535, office phone: 619-594-2014, email: txie@mail.sdsu.edu

3.

Required materials to include a.

Text book: Mano, M. Morris, and Kime, Charles R., Logic and Computer

Design Fundamentals, 4th Ed, Prentice Hall, 2007. b.

Other supplemental materials: LogicWorks, a schematic drawing and interactive digital simulation package, and its manual LogicWorks 5

Interactive Software.

4.

Specific course information a.

Logic gates, combinational circuits, sequential circuits, memory and bus system, control unit, CPU, exception processing, traps and interrupts, inputoutput and communication, reduced instruction set computers, use of simulators for analysis and design of computer circuits, and traps/interrupts. b.

Prerequisites: CS 237 - Machine Organization and Assembly Language

Knowledge of the MC68000 assembly language. c.

Course Type: Required

5.

Specific goals for the course a.

Specific course-level outcomes of instruction:

(1) The student will be able to design and implement a combinational circuit

(2) The students will be able to develop a sequential circuit

(3) The student will be able to implement ECC (error correction code) schemes in digital computers

(4) The student will be able to design a memory system. b.

Mapping to Program Course Outcomes: a) An ability to design, implement, and evaluate a computer-based system, process, component, or program to meet desired needs 
 b) An ability to function effectively on teams to accomplish a common goal c) Recognition of the need for and an ability to engage in continuing professional development

6.

Topics covered include: (1) Introduction; (2) Data types and representation; (3)

Boolean algebra and logic design; (4) Simplification of Boolean functions; (5)

Combinational circuit analysis and design; (6) Sequential circuit analysis and design;

(7) Memory organization; (8) Processor; (9) System bus.

7.

Course schedule that includes major assignments/due dates and exam dates

1.

Homework#1 is due in class on Monday Sept. 29

2.

Lab Assignment#1 is due 11:59 pm on Sept. 25 Thursday

3.

Midterm Exam #1 is scheduled in class on Oct. 1 Wednesday

4.

Homework#2 is due in class on Nov. 3

5.

Lab Assignment#2 is due 11:59 pm on Oct. 30 Thursday

6.

Midterm Exam #2 is scheduled in class on Nov. 5 Wednesday

7.

Homework#3 is due in class on Monday Dec. 1

8.

Lab Assignment#3 is due 11:59 pm on Dec. 4 Thursday

9.

Final Exam is scheduled from 3:30 pm ~ 5: 30 pm on Dec. 15 Monday

8.

Grading policies

Midterm Exam #1 75-minute close book & note in class ...15%

Midterm Exam #1 75-minute close book & note in class ...15%

Homework assignment1 ~ Homework assignment3 ...24% total (each homework assignment 8%)

Lab assignment1 ~ Lab assignment3 ...26% total (Lab1-6%; Lab2-10%; Lab3-10%)

Final exam 120-minute close book & note ...20%

A: 90~100; A - : 86 ~89; B+ : 82~85; B: 78~81; B-: 74~77; C+: 70~73; C: 66~69; C-:

62~65; D+: 58~61; D: 54~57; D-: 50~53; F: 0~49

9.

“Accommodating students with disabilities” statement:

If you are a student with a disability and believe you will need accommodations for this class, it is your responsibility to contact Student Disability Services at (619) 594-

6473 . To avoid any delay in the receipt of your accommodations, you should contact

Student Disability Services as soon as possible. Please note that accommodations are not retroactive, and that accommodations based upon disability cannot be provided until you have presented your instructor with an accommodation letter from Student

Disability Services. Your cooperation is appreciated.

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