VLSI AND SOFTWARE RADIOS By John Fakatselis Harris semi. AP96358 2-1
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VLSI AND SOFTWARE RADIOS By John Fakatselis Harris semi. AP96358 2-1 CONTRIBUTING ENABLING TECHNOLOGIES TO VLSI RADIOS. • Process Technology • Package Technology • IC Simulation Tools • System Simulation Tools RADIO DESIGN EXAMPLE • AN EXAMPLE OF A VLSI RADIO DESIGN: • WIRELESS LAN, BASED ON PROPOSED IEEE8021.11 SPEC. • RF, IF , MODEM DESIGN , AND PROTOCOL MAC. Wireless LAN (WLAN) Markets Current Market PRIMARILY AT 902 - 928MHz • MIX OF SPREAD SPECTRUM TRANSCEIVERS WITHOUT STANDARDS • NO COMPLIANT PROTOCOL STANDARDS • NO INTEROPERABILITY OF EQUIPMENT • LOW DATA RATES RF Emerging Market 2.4 - 2.5GHz • • • • • • • IEEE 802.11 STANDARD FOR WLANS COMPLIANT STANDARDS FOR INTEROPERABILITY CONNECTIVITY SUPPORT HIGHER DATA RATES PCMCIA LAN CARD SOLUTION LOWER COST HIGHER PERFORMANCE SPEED, RANGE, BATTERY LIFE AP96358 3-3 The 802.11 Wireless LAN Standard AP96358 3-1 IEEE 802.11 WLAN Standard • IEEE WLAN WORKING GROUP WITH GLOBAL REPRESENTATION • STANDARD FOR WLANS WITH A COMMON MULTI-USER MEDIA • GLOBAL EQUIPMENT INTEROPERABILITY • FREQUENCY: 2.4GHz ISM BAND (83.5MHz BW) • MEDIUM TO HIGH DATA RATES • APPLICATIONS RANGING FROM SMALL OFFICES TO INDUSTRIAL MANUFACTURING CAMPUSES • SPREAD SPECTRUM TECHNOLOGY - Limits Transmitted Power Density - Provides a Robust Solution in a Multi-user Environment AP96358 3-5 Industrial, Scientific and Medical (ISM) Bands 902 to 928MHz 2.400 to 2.4835GHz 26MHz 83.5MHz 1 2 3 FREQUENCY (GHz) 5.725 to 5.850GHz 125MHz 4 5 6 • UNLICENSED OPERATION GOVERNED BY FCC DOCUMENT 15.247, PART 15 • SPREAD SPECTRUM ALLOWED TO MINIMIZE INTERFERENCE • 2.4GHz ISM BAND - More Bandwidth to Support Higher Data Rates and Number of Channels - Available Worldwide - Good Balance of Equipment Performance and Cost Compared with 5.725GHz Band - IEEE 802.11 Global WLAN Standard AP96358 3-4 Direct Sequence Spread Spectrum • • • • DATA SIGNAL SPREAD BY A PN CODE PROPERTIES OF PN CODE CHIP RATE DS PROCESSING GAIN GP (dB) = 10LOG ( CHIP RATE DATA RATE CW SIGNAL AMPLITUDE (dBm) ) • PN CORRELATION AT RECEIVER • PSK DATA MODULATION 1 DATA 0 CHIP CLOCK SPREAD SIGNAL AMPLITUDE (dBm) 18 1.2 15 1.0 12 0.8 9 0.6 6 0.4 3 0.2 0 0 2.43 2.44 2.45 2.46 2.47 FREQUENCY (MHz) BARKER CODE SPREAD DATA AP96358 2-11 Frequency Hopping Spread Spectrum f5 AMPLITUDE f4 f3 f2 FREQUENCY f1 1 2 3 4 5 6 7 8 9 10 11 12 TIME • • • • • FSK DATA MODULATION PERIODIC CHANGES IN THE CARRIER FREQUENCY SPREADS THE SIGNAL CARRIER FREQUENCY CHANGES AT A SPECIFIED HOP RATE CARRIER FREQUENCY HOPS AFTER A PRESCRIBED TIME TOTAL SYSTEM BANDWIDTH INCLUDES ALL OF THE CHANNEL FREQUENCIES USED IN HOPPING AP96358 2-13 802.11 Protocol Layers Media Access Control Layer MAC - Layer MAC - PHY Sublayers PHY - Layer PROTOCOL AND PHYSICAL LAYER MANAGEMENT MAC-PHY Sublayers CONFIGURE DATA FRAMES AND PREAMBLES FOR TRANSMIT AND RECEIVE MODE Physical Layer RADIO TRANSMISSION MEDIA FOR EITHER DSSS, FHSS OR INFRARED AP96358 3-10 802.11 DSSS Physical Layer MODULATION: PN CODE: DATA RATE: CHIPPING RATE: TRANSMIT POWER: TRANSMIT FREQUENCY TOLERANCE: CHIP CLOCK ACCURACY: RECEIVER INPUT LEVEL SENSE: RECEIVER ENERGY DETECT: PREAMBLE LENGTH: DATA PACKET SIZE: ENVIRONMENT: DPSK 11-BIT BARKER 1Mbps/DBPSK, 2Mbps/DQPSK 11Mcps USA: 1W MAX. FCC 15.247 EUROPE: 100mW (EIRP) ETSI 300-328 JAPAN: 10mW / MHz MPT ORD. 78 25ppm MAX. 25ppm MAX. -2 -80dBm 8x10 FER (FRAME ERROR RATE) 20s MAX. 144 SYMBOLS 2048 BYTES MAX. PACKET BURST DATA AP96358 3-14 PRISM™ Chipset AP96358 4-1 WLAN Radio Requirements PCMCIA RADIO BOARD • LOW COST • HIGH DATA RATE AND HIGH THROUGHPUT • PCMCIA COMPATIBLE • LONG RANGE • MOBILITY WITH ROAMING CAPABILITY • LOW VOLTAGE, LOW POWER, BATTERY OPERATED • HIGH LEVEL OF INTEGRATION AP96358 4-2 PRISM™ “Antenna to Bits™” A Complete DS Spread Spectrum Radio Chipset ADC CCA I ADC HFA3424 LNA DESPREAD DEMODULATE HSP3824 BASEBAND PROCESSOR Tx/Rx DATA I/O Q ADC LO HFA3624 RF/IF HFA3724 QMODEM SPREAD MODULATE/ ENCODE CONTROL TEST I/O HFA3925 RF POWER AMPLIFIER AND Tx/Rx SWITCH HFA3524 DUAL SYNTHESIZER AP96358 4-4 RF IC Partitioning Criteria • FREQUENCY • ANALOG / DIGITAL SIGNALS • PROCESS TECHNOLOGY • ISOLATION REQUIREMENTS • POWER LEVELS • PACKAGING • EXTERNAL COMPONENTS AP96358 4-5 RF to IF Conversion Issues • NOISE FIGURE (NF) • INPUT/OUTPUT 1dB COMPRESSION POINT (IP1dB/OP1dB) HFA3424 LNA • INPUT/OUTPUT THIRD ORDER INTERCEPT POINT (IP3I/ IP3O) HFA3624 RF/IF • IMPEDANCE MATCHING • DYNAMIC RANGE DUAL SYNTHESIZER • SPURIOUS FREE DYNAMIC RANGE (SFDR) AP96358 4-6 HFA3624 RF to IF Converter BIAS Receive • LNA • SINGLE CONVERSION HETERODYNE MIXER • INTEGRATED RECEIVE / TRANSMIT FRONT END • 2.4 TO 2.5GHz RF FREQUENCY RANGE • 10 TO 400MHz IF OPERATION • SINGLE SUPPLY 2.7V TO 5.5V BIAS Transmit • ALL RF I/Os MATCHED TO 50 • SINGLE CONVERSION MIXER • LINEAR POWER PREAMP • INDEPENDENT RECEIVE / TRANSMIT POWER ENABLE 28-PIN SSOP Rx 0 Tx POWER CONSUMPTION 0 0.3A • 150mil WIDE • 0.08 SQUARE INCHES 0 1 48mA 1 0 18mA AP96358 4-8 HFA3624 Receive Section LNA IMAGE NOISE SUPPRESSION LNA @ 2.5GHz • POWER GAIN . . . . . . . 15.6dB • OP1dB . . . . . . . . . . . . . 5.5dBm • NF . . . . . . . . . . . . . . . . . 3.8dB Rx BIAS Rx AMP Rx MIXER Mixer (LO = 2.15GHz) • POWER CONVERSION GAIN . . . . . . . . . . . . . . . • IP3O . . . . . . . . . . . . . . . . 3.0dB 4.0dB • NF . . . . . . . . . . . . . . . . . 12.0dB Transmit Section BIAS NF = 10LOG(F) = NOISE FIGURE WHERE (F) = NOISE FACTOR F = SNRI / SNRO AP96358 4-9 HFA3624 RF Front End Cascaded Performance Rx MIXER LNA Cascaded Performance Data • NF. . . . . . . . . . . . . . . . . . . . 4.5dB • IP1dB . . . . . . . . . . . . . . . . . -28dB • IP3I . . . . . . . . . . . . . . . . . . . -18dB LO Cascaded Performance Data FC = F1 + F2 - 1 + F3-1 +... G1 G1G2 • FC = CASCADED NOISE FACTOR • Gn = GAIN OF STAGE n System Performance Fc Effect on Sensitivity (MDS) • MDS = FC(kTB) (SNR)O where: MDS = Minimum Discernible Signal k = Boltzmann’s Constant T = Absolute Temperature in Kelvin B = Bandwidth (SNR)O = Output Signal-to-Noise Ratio • DYNAMIC RANGE (IP1dB - MDS) • SPURIOUS FREE DYNAMIC RANGE 2/3(IP3I - MDS) AP96358 4-10 HFA3624 Receive Amplifier Power Gain (S21) 20 15 10 GAIN (dB) 5 TESTED 0 SIMULATED -5 -10 0 2 4 6 FREQUENCY (GHz) AP96358 4-13 HFA3624 Transmit Section BIAS Receive Section Mixer (Upconverter) • POWER CONVERSION GAIN . . . . 5.8dB • LO LEAKAGE . . . . . . . . . . . . . . . . -20.0dB Pre-Amp • POWER GAIN . . . . . . . . . . . . . . . . 13.0dB • OP1dB . . . . . . . . . . . . . . . . . . . . . +7.5dBm Cascaded Performance BIAS • POWER GAIN . . . . . . . . . . . . . . . . 17.8dB • OP1dB . . . . . . . . . . . . . . . . . . . . . . 0.5dBm • LO LEAKAGE . . . . . . . . . . . . . . . . -5.0dBm UPPER/LOWER SIDEBAND SELECT AP96358 4-11 IF to Baseband Conversion Issues • PRIMARY SOURCE OF GAIN - Limiter or AGC ADC • RSSI TO MEASURE INPUT SIGNAL CCA I ADC DESPREAD HFA3424 LNA • COMPLEX DOWN CONVERSION TO BASEBAND DEMODULATE Q ADC Tx/Rx DATA I/O LO • QUADRATURE LOHFA3624 RF/IF GENERATION HFA3724 QMODEM • FILTERING (BASEBAND) HFA3925 - Anti-aliasing on Receive RF POWER - Pulse Shaping on Transmit AMPLIFIER SPREAD MODULATE/ ENCODE CONTROL TEST I/O AND TX/RX SWITCH • UP CONVERSION / MODULATION • POWER SAVING FEATURES HFA3524 DUAL SYNTHESIZER AP96358 4-15 HFA3724 Quadrature IF Modulator / Demodulator (A) Limiter and RSSI (B) Demodulator (C) Filter • IF UP TO 400MHz • 84dB GAIN • 70dB RSSI DYNAMIC RANGE • DOWN CONVERTS 10 TO 400MHz IF TO BASEBAND • IN PHASE (I) AND QUADRATURE (Q) • TWO LOW PASS FILTERS (I AND Q) • DIGITALLY SELECTABLE FILTER CUTOFF • MULTIPLEXED RECEIVE / TRANSMIT RxIN (D) Modulator (B) (A) I (E) ÷ 2 0° / 90° (D) TxOUT (C) MUX BIAS MUX Rx IOUT Rx QOUT Tx IIN Q Tx QIN REF 80 LEAD TQFP • UP CONVERT AND PHASE MODULATES I AND Q TO 300MHz (E) Power • POWER CONTROL INCORPORATING SLEEP MODE • HALF DUPLEX OPERATION AP96358 4-16 HFA3724 Limiter and RSSI Limiter • TWO INDEPENDENT AMPLIFIERS • GAIN (EACH AMP) FROM 10 TO 400MHz . . . . . . . . 42dB • LIMITER -3dB SENSITIVITY. . . . . . . . . . . . . . -84dBm • NF (FOR 250 SINGLE ENDED INPUT IMPEDANCE) . . . . . . . . . . 6dB RSSI RSSI • SENSITIVITY. . . . . . . . . . . . . . -84dBm • DYNAMIC RANGE . . . . . . . . . 70dB • RSSI SLOPE . . . . . . . . . . . . . 5A/dB AP96358 4-17 HFA3724 Q-Modem DC 280MHz 1 / TC Q Rx (TO FILTERS) Rx IFI I ÷ 2 OUT INPUT FREQUENCY RESPONSE . . . . 400MHz DIFFERENTIAL VOLTAGE GAIN . . . . . . . . 8dB PHASE MATCH . . . . . . . . . . . . . . . . . . . . . . 2° AMPLITUDE MATCH . . . . . . . . . . . . . . . 0.5dB • INTERNAL DIVIDE BY 2 FLIP-FLOP WITH DUTY CYCLE COMPENSATION • 50 DIVIDED BUFFER OUTPUT AVAILABLE 0° / 90° LOI I Quadrature Upconverter Tx (FROM FILTERS) • • • • Q DC 280MHz • • • • Quadrature LO Generator ÷2 Tx IFO Quadrature Downconverter 1 / TC PHASE MATCH . . . . . . . . . . . . . . . . . . . . . . . 2° AMPLITUDE MATCH . . . . . . . . . . . . . . . . 0.5dB LO LEAKAGE . . . . . . . . . . . . . . . . . . . . . .-30dBc MINIMUM SIDEBAND SUPPRESSION (400MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 26dBc AP96358 4-18 HFA3724 Baseband Filters RTUNE SEL 0 SEL 1 Tx I Tx I Tx Q Tx Q Rx I Rx I Rx Q Rx Q • 5 - POLE BUTTERWORTH FILTERS • MULTIPLEXED FILTERS FOR HALF DUPLEX OPERATION - Pulse Shaping on Transmit - Anti-aliasing on Receive • FOUR SELECTABLE CUTOFF • FREQUENCIES: 2.2MHz, 4.4MHz, 8.8MHz, 17.6MHz • 20% FINE TUNING WITH EXTERNAL RESISTOR Tx OR Rx POWER ENABLE f3dB = 0.8 (1/ TC) -30dBr -50dBr fc-33 fc-22 fc-11 fc+11 fc+22 fc+33 • TRANSMIT FILTERING REDUCES SPECTRAL PRODUCTS TO IEEE802.11 SPECIFIED LEVELS • TUNING RESISTOR COMPENSATES FOR SPECTRAL RE-GROWTH (MHz) 802.11 SPECTRAL MASK AP96358 4-21 Adjacent Channel Interference Versus Intersymbol Interference I TRANSMITTER Q o 90 0 o WIDEBAND FILTER CHANNEL BANDWIDTH NARROWBAND FILTER RF FREQUENCY SPECTRUM EYE DIAGRAM OF DATA AP96358 2-9 Filter Response Comparison • THEORETICAL AMPLITUDE AND GROUP DELAY OF FOUR DIFFERENT FILTERS • FILTERS ARE 5 POLE • CUTOFF FREQUENCY NORMALIZED TO 1kHz Group Delay Amplitude 2.0 20 1.75 0 (dB) 1.50 -20 1.25 -40 (s) 1.0 0.75 -60 0.50 -80 0.25 -100 0.1 0 1 10 FREQUENCY (kHz) 100 0.1 BESSEL BUTTERWORTH CHEBYSHEV ELLIPTIC 1 10 FREQUENCY (kHz) 100 AP96358 4-20 Filter Cutoff Frequency Selection ATTENUATION (dB) 0 2.2 -3 4.4 8.8 17.6 SEL 1 SEL 0 0 0 1 1 0 1 0 1 f3dB (MHz) 2.2 4.4 8.8 17.6 -6 1 2 4 FREQUENCY (MHz) 8 10 AP96358 4-19 HFA3724 Performance Data POWER (dBm) POWER (dBm) Modulator Output -24 Modulator Output with Filter Tuning Resistor -24 -28dBr -44 -44 -64 -64 -84 -84 255 280 FREQUENCY (MHz) 305 255 -36dBr 280 305 FREQUENCY (MHz) AP96358 4-23 Baseband Section Issues • ANALOG TO DIGITAL CONVERSION ADC • SPREAD / DESPREAD I ADC • MODULATE / DEMODULATE Q ADC CCA DESPREAD Tx/Rx DATA I/O • CLEAR CHANNEL ASSESSMENT • DATA FORMATTING AND HEADER CREATION DUAL SYNTHESIZER DEMODULATE SPREAD MODULATE/ ENCODE CONTROL TEST I/O HSP3824 BASEBAND PROCESSOR AP96358 4-29 HSP3824 Baseband Processor RSSIIN 6-BIT A/D CLEAR CHANNEL ASSESSMENT IIN 3-BIT A/D CORRELATOR QIN IOUT QOUT 3-BIT A/D Rx DATA BPSK/DQPSK DEMODULATE Tx/Rx DATA I/O Tx DATA CORRELATOR XOR MODULATE ENCODE XOR PN GENERATOR TEST AND CONTROL PORT I/O MAC CONTROL AP96358 4-30 HSP3824 Analog to Digital Converters • 44Msps, 3-BIT FLASH A/Ds SAMPLE I/Q INPUTS • PATENTED CIRCUITRY ACTS AS AGC TO KEEP A/Ds AT FULL SCALE IIN 3-BIT A/D MATCHED FILTER CORRELATOR QIN 3-BIT A/D MATCHED FILTER CORRELATOR REF + A/D REFERENCE AND LEVEL ADJUST REF - • 2Msps, 6-BIT A/D SAMPLES RSSI RSSIIN 6-BIT A/D TO CLEAR CHANNEL ASSESSMENT CIRCUIT AP96358 4-31 Why 3-Bits? Correlator SNRO vs SNRI • 3-BIT QUANTIZATION GIVES SIGNIFICANT ADVANTAGE OVER 1-BIT • QUANTIZATION TO GREATER THAN 3-BITS YIELDS NEGLIGIBLE IMPROVEMENT QUANTIZATION Q=• 0.22dB Q = 8 (3-BIT) Q=2 10.4 SNRO (3dB/DIV) EXPECTED OPERATING -5 POINT OF 10 BER 0 SNRI (3dB/DIV) AP96358 4-32 Sample Clock Timing LC FILTER BUTTERWORTH FILTER CUTOFF SELECT HFA3724 RSSI HSP3824 I ADC DESPREAD FROM RF/IF SECTION LIMITING IF DEMODULATE Rx DATA Q ADC 1 CHIP PERIOD AMPLITUDE TIME CHIP CLOCK IDEAL SAMPLE CLOCK 1/2 CHIP CLOCK AP96358 4-34 HSP3824 Matched Filter Correlator 2x CHIP CLOCK Rx DATA FROM ADCs PARALLEL PN REGISTER LOAD -1 -1 Z1 Z2 R1 -1 -1 Z3 Z4 R2 -1 -1 Z5 -1 Z6 Z2N RN N = 16 R3 SYMBOL PERIOD CHIP PERIOD 11-BIT BARKER CODE EXAMPLE: +1 -1 +1 +1 -1 +1 +1 +1 -1 -1 -1 A/D SAMPLE CLOCK CORRELATION SCORE AP96358 4-33 HSP3824 Receive Section DPSK Demodulator FROM CORRELATORS TIMING CONTROL • COHERENT LOOP FOR PHASE ERROR COMPENSATION • USER CONFIGURABLE SIGNAL QUALITY THRESHOLDS MAGNITUDE AND PHASE PHASE ROTATE SIGNAL QUALITY (1) SYMBOL TIMING PSK DEMOD DIFFERENTIAL DECODE PHASE ERROR ABS VALUE NCO DATA DESCRAMBLER AVG PHASE ERROR Rx DATA SIGNAL QUALITY (2) AVG PHASE FREQ LEAD/ LAG FILTER AP96358 4-35 Complete RF to Baseband Circuit THREE POLE DIELECTRIC OR LC FILTER fO = 2.4GHz BW = 80MHz LNA USED TO INCREASE GAIN 8 TO 10dB TWO POLE DIELECTRIC OR LC FILTER fO = 2.4GHz BW = 80MHz LIMITER 1/LIMITER 2 INTERSTAGE BPF fO = 280MHz BW = 17MHz FILTER CUTOFF SELECTION RSSI QUADRATURE DEMOD SAW FILTER fO = 280MHz BW = 17MHz HFA3424 LNA RxI 280MHz Tx/Rx LNA RxQ LIMITING IF/RSSI TRANSMIT SECTION HFA3925 RF POWER AMPLIFIER AND Tx/Rx SWITCH HFA3624 RF/IF VCO SET TO 2.21 TO 2.22GHz LO I/Q LO TRANSMIT SECTION VCO OSCILLATOR SET FOR 560MHz HFA3724 QUADRATURE DEMODULATOR HFA3524 DUAL SYNTHESIZER SYNTHESIZER CONTROL FROM MAC AP96358 4-28 MAC-PHY Glueless Interface TO HFA3724 FILTER CUTOFF SELECTION HSP3824 Tx_PE TxD TxCLK INT1 INT2 Tx/Rx POWER CONTROL AM79C930VC AMD RxDATA PC-NET RxCIN MD_RDY MOBILE MAC RxD RxC MD_RDY CS SD SCLK R/W AS ANTSEL TO HFA3624/3724 TxPE RxPE SEL 1 TxCMD TxDATA TxC Tx_RDY CCA SERIAL CONTROL BUS SEL 0 I/O CONTROL PORT PC INTERFACE RAM ROM CLOCK SYNTHESIZER CONTROL TO HFA3524 DATA STB AP96358 4-39 HSP3824 Evaluation Setup I OUT HP8780A VECTOR SIGNAL GENERATOR 280MHz NOISE/COM 6108 (NOISE ADDER) S+N 280MHz PAD BASEBAND DATA CLOCK GENERATOR CONTROL PORT HSP3824 EVALUATION BOARD CARRIER IBM-PC CONTROL TxQ TxI HP8981 VECTOR SIGNAL ANALYZER FIREBERD 6000A BER TESTER CLOCK GENERATOR Q OUT BASEBAND DATA HP8657B SIGNAL GENERATOR CONTROL PORT HSP3824 EVALUATION BOARD BERT Tx Rx AP96358 4-40 BER Performance LOSS IN dB -5 @ 10 BER PHASE NOISE * LIMITING AMPLIFIERS IN IF 0.5 I/Q PHASE AND AMPLITUDE IMBALANCE 0.75 NEGLIGIBLE A/D HEADROOM vs BIAS ADJUSTMENT NEGLIGIBLE SAMPLING STRADDLING OFFSET AND IF + LPF FILTER LOSSES 0.22 2.0 QUANTIZATION AND DQPSK DEMOD LOSS 0.5 PHASE LOCK LOOP NOISE 0.1 DESCRAMBLER ERROR EXTENSION 10-1 10-2 A/D LINEARITY OSCILLATOR OFFSET IN CORRELATOR AT 50ppm BER vs Eb/No Performance 0.5 * Depends on synthesiser 10-3 BIT ERROR RATE PARAMETER DQPSK 10-4 DBPSK 10-5 10-6 10-7 THEORY (DBPSK) 10-8 10-9 8.4 9.4 10.4 11.4 12.4 13.4 14.4 15.4 Eb/No (dB) AP96358 4-41 HSP3824 Transmit Section DPSK Modulator CLK -1 Z IOUT LATCH DATA SCRAMBLER QOUT Tx PORT PREAMBLE HEADER GENERATION MUX CLK FOR DQPSK I CH ONLY FOR DBPSK PN GENERATOR • FOUR SELECTABLE, INTERNALLY GENERATED PREAMBLE/HEADER FORMATS • SELECTABLE CHIP SEQUENCES OF 11, 13, 15 OR 16 CHIPS PER SYMBOL • SYMBOL RATE = MCLK/(N * CHIPS PER SYMBOL) WHERE MCLK = SAMPLE RATE CLOCK AND N IS A PROGRAMMABLE DIVIDER OF 2, 4, 8 OR 16 AP96358 4-36 RF Power Amplifier Issues ADC CCA I ADC DESPREAD DEMODULATE Q ADC HFA3925 RF POWER AMPLIFIER AND Tx/Rx SWITCH • POWER GAIN • POWER ADDED EFFICIENCY • 1dB COMPRESSION Tx/Rx DATA I/O SPREAD MODULATE/ ENCODE CONTROL TEST I/O • IMPEDANCE MATCHING • SUPPLY VOLTAGE DUAL SYNTHESIZER AP96358 4-42 HFA3925 RF Power Amplifier and Switch TO RECEIVE VDD1 VDD2 VDD3 TO ANTENNA VG1 VG2 VG3 Tx/Rx CONTROL • HIGHLY INTEGRATED GaAs POWER AMPLIFIER WITH T/R SWITCH • HIGH LINEAR OUTPUT POWER AT OP1dB 24dBm (250mW) • INDIVIDUAL GATE CONTROL FOR EACH AMPLIFIER STAGE • VSWR IN/OUT . . . . . . . . . . 1.75:1 • SUPPLY VOLTAGE . . . 2.7 TO 6V • T/R SWITCH - Insertion Loss . . . . . . . 1.2dB - Isolation . . . . . . . . . . . . 12dB 28 Lead SSOP AP96358 4-43 Complete Baseband to RF Circuit HFA3724 QUADRATURE MODULATOR THREE POLE DIELECTRIC FILTER fO = 2.4GHz BW = 80MHz HFA3624 RF/IF RECEIVE SECTION RECEIVE SECTION I/Q LO IF BP FILTER fO = 280MHz BW = 17MHz 5TH ORDER BUTTERWORTH LOW-PASS FILTER DIGITAL I/Q DATA RECEIVED FROM BBP HFA3925 RF POWER AMPLIFIER AND Tx/Rx SWITCH TWO POLE DIELECTRIC FILTER fO = 2.4GHz BW = 80MHz VCO SET TO 2.21 TO 2.22GHz LO VCO SET FOR 560MHz LO HFA3524 DUAL SYNTHESIZER SYNTHESIZER CONTROL FROM MAC AP96358 4-44 SOFTWARE RADIOS • PROGRAMMABLE RADIOS TO ACCOMODATE VARIOUS MODULATION REQUIREMENTS. • DIGITAL SIGNAL PROCESSING TECHNIQUES. • DIGITAL FILTERING TECHNIQUES. Summary of Cellular and PCS Standards IS-95 CDMA/FDM 20 Chs GSM 1.25MHz BW BPSK/OQPSK 798 Users/Ch TDMA/FDM 124 Chs 8 Users/Ch AMPS FDMA 832 Chs 30kHz BW FM 1 User/Ch IS-54/136 What Hardware Works with ALL of These Standards ? DECT TDMA/FDM 10 Chs 200kHz BW GMSK TDMA/FDM 832 Chs 30kHz BW /4 DQPSK 3 Users/Ch DCS 1800 1.728MHz BW GFSK TDMA/FDM 374 Chs 12 Users/Ch 200kHz BW GMSK 8 Users/Ch CELLULAR PROVIDER AP96358 7-2 DIGITAL AGC LOOP FILTER, LIMIT AND DETECTOR DECIMATE RD x83 ORDER CIC 256-TAP PROGRAMMABLE FIR FILTERS RESAMPLER SHIFT 1 TO 5 HALFBAND FILTERS FIR DECIMATION UP TO 32 POLYPHASE FILTER NCO POLYPHASE FILTER NCO ¦ I2 + Q2 CARTESIAN TO POLAR -1 TAN (Q) I OUTPUT MUX/FORMAT SHIFT LEVEL DETECT LOOP FILTER DIGITIZED IF INPUT LEVEL CONTROL HSP50214 - Digital IF Downconverter OUTPUT A OUTPUT B de dt DISCRIMINATOR SYMBOL TRACKING CARRIER TRACKING Features • • • • UP TO 51.2 Msps INPUT TO SUPPORT WIDEBAND CHANNEL SELECTION DIGITAL AGC WITH PROGRAMMABLE LIMITS AND SLEW RATE OVERALL DECIMATION FACTOR RANGING FROM 1 TO 2048 SUPPORTS DEMODULATION OF AM, FM, FSK, DPSK AP96358 9-4
