MOS SINGLE STAGE CIRCUITS
Goal:
To design
a) Common Source Amplifier of gain 20,
b) Common Source Amplifier of Current Gain 10
c) Simple Common Gate Amplifier and
find the 3 dB cut off frequency and output impedance for all the three .
COMMON SOURCE AMPLIFIER
+10 V
RL
10k
0.01F
o/p
2k
Bias Details:
We know the value of gm (say, at the mid point of triode region) from the first
experiment.
a) As gain is A0 = -gmRL, and A0 = 20, we can get RL.
b) So, connect a RL at the Drain end.
c) Now tune the 2k pot and set the output point at (VDD-VSS)/2 = (10-0)/2 = 5 V.
[Note that this is where we can expect a maximum output swing]
Amplifier Operation:
1) Now switch on the function generator [sine – 10mVpp-100Hz-zero DC offset]
2) Note the Voltage gain A0 = Vout/Vin.
3) Now with the same input amplitude, keep on increasing the frequency.
4) Note down the frequency where the output is 0.707 of its initial amplitude.
5) Reconfigure the circuit with a Current source replacing RL.
6) Use a Potential Divider to adjust the Vbias of the current source so that the
output DC operating point remains the same.
+10 V
Vbias
10k
0.01F
o/p
2k
6) Repeat the procedure 1 through 4.
Report the differences in the gain and 3 dB point from that of the previous circuit.
a) Is this the maximum gain?
b) Can the Vbias be increased to improve the gain?
c) If the Vbias is increased on the output side “something” happens.
What is this “something”?
What should be done on the input side to counteract this “something”?
Measuring the output impedance:
C = 0.01F
O/P of
amplifier
R = 200k
Vary R till the output becomes half its unloaded value. Don’t short the R and burn up
the FET!!
Now this R = output impedance of the amplifier. What is the value?
But why is this C added?
Report what happens when C is removed and the procedure is repeated.
COMMON DRAIN AMPLIFIER
+10 V
10k
0.1F
D
G
S
o/p
20k
RS
Bias Details:
1) The output point has to be at the mid point of the rail voltage.
2) So tune the 20k pot and move the source end to 5 volts.
3) Now we need to design RS. On the input side, the AC impedance is 10K
0.1F
I
10K
‘C’ can be assumed short at a little higher frequency. So ‘Z’ in the AC path is 10K.
4) So for a current amplification of 10, the resistance in the output path should
be 1k. [Reflection principle]. So put RS = 1k.
Amplifier operation:
1) Now switch on the function generator [sine – 1Vpp-1000Hz-zero DC offset].
2) Sweep the frequency till 5 MHz and find the 3-dB point.
3) Notice what happens to gain and 3dB point when a series network of 0.01F
capacitor and 3k resistor is added parallel to RS.
4) Measure the output impedance of this amplifier.
COMMON GATE AMPLIFIER
+10 V
10k
S
D
G
Amplifier Operation:
1) Connect the circuit as in figure.
2) Switch on the signal generator [20 mV, sin-100Hz] at the input.
3) Sweep the frequency and note down the 3dB point.
4) What happens if a capacitor of 10pF is added between the source and the
gate? What is expected? Why it didn’t happen? What happened to the miller
effect?
5) Measure the output impedance of this amplifier.
RESULTS:
COMMON SOURCE AMPLIFIER
a) The 3-dB point is ____
b) The output impedance is ____
COMMON DRAIN AMPLIFIER
a) The 3-dB point is ____
b) The output impedance is ____
COMMON GATE AMPLIFIER
c) The 3-dB point is ____
d) The output impedance is ____