U niversity of S outhern C alifornia
School Of Engineering
Department Of Electrical Engineering
EE 348:
Homework Assignment #01
(Due 01/18/2001)
Spring, 2001
Choma
Problem #01:
Under commonly encountered operating conditions, Fig. (P1) is a valid linearized equivalent circuit of a voltage buffer realized in MOSFET device technology. The input
signal source is represented by its Thévenin equivalent circuit, which consists of voltage source
Vs and resistance Rs. The output, or response, to this input signal is the indicated voltage, Vo,
which is developed across the shunt interconnection of load resistance Rl and load capacitance
Cl. The actual MOS transistor is modeled by the two voltage controlled current sources, gmVi
and λbgmVb, where gm (typically of the order of hundreds of micromhos to a few millimhos) is
the forward transconductance of the transistor, and λb (a dimensionless number generally smaller
than 0.1) emulates the impact exerted by the substrate on device forward transfer characteristics.
Note that regardless of the nature of the transistor parameters, the model in Fig. (P1) is a linear
active circuit, not unlike circuits encountered in the first course on circuit theory.
 bgmVb
gmVi
Rs
  Vi 

Vs

Vo

Vb
 Rl
Cl
Rin
Rout
Fig. (P1)
(a). Determine, and express as a function of Vs, the Thévenin equivalent voltage, say Vot, that
drives the load capacitor, Cl. Simplify the expression for Vot for the special case of an infinitely large load resistance, Rl. If Rl were to be omitted from the diagram in Fig. (P1),
would the resultant expression for Vot be identical to the originally derived expression?
(b). What is the low frequency value of the voltage gain, Vo/Vs, of the circuit and how does this
gain relate to the ratio, Vot/Vs?
(c). Derive an expression for the Thévenin equivalent resistance, Rout, facing capacitance Cl.
(d). Derive an expression for the low frequency input resistance, Rin, “seen” by the signal
source.
(e). What is the significance of the time constant, RoutCl, to the frequency domain transfer function, H(jω) = Vo(jω)/Vs(jω)? Give an expression for this transfer relationship in terms of
EE 348
University of Southern California
J. Choma, Jr.
Vot/Vs and the subject time constant.
(f). Give a simple expression for the 3–dB bandwidth of the circuit; that is, the frequency at
which the magnitude of the high frequency gain is a factor of root two smaller than its low
frequency value.
(g). Is there anything interesting about the gain bandwidth product, which is cleverly defined
as the product of the magnitude of zero frequency gain and 3–dB bandwidth?
(h). Take Rs = 300 , Rl = 1,000 , gm = 5 millimho, λb = 0.08, and Cl = 8 pF. Calculate the
low frequency voltage gain, the output resistance, the time constant of the circuit, and the
circuit 3-dB bandwidth.
Problem #02:
Under commonly encountered operating conditions, Fig. (P2) is a valid linearized equivalent circuit of a voltage amplifier realized in bipolar junction transistor (BJT)
device technology. The input signal source is represented by its Thévenin equivalent circuit,
which consists of voltage source Vs and resistance Rs. The output, or response, to this input signal is the indicated voltage, Vo, which is developed across the shunt interconnection of load
resistance Rl and load capacitance Cl. The actual BJT is modeled by the current controlled current source, I, and the two resistances, rb and r. Typically, , which is dimensionless, is of the
order of 100 or so, rb can be as large as 200 , and r is of the order of a few thousand ohms.
The resistance, Re, is a circuit element used for biasing and linearity purposes. It is generally
chosen to be of the order of fifty to a few hundred ohms. Note that regardless of the nature and
numerical value of the transistor and circuit parameters, the model in Fig. (P2) is a linear active
circuit, not unlike circuits encountered in the first circuit theory course.
Rs
Rout
rb
Vo

r
Vs

I
Rl
Cl
Rin
I
Rte
Re
Fig. (P2)
(a). Determine, and express as a function of Vs, the Thévenin equivalent voltage, say Vot, that
drives the load capacitor, Cl. Simplify the expression for Vot for the special case of a very
large current gain parameter, .
(b). What is the low frequency value of the voltage gain, Vo/Vs, of the circuit and how does this
gain relate to the ratio, Vot/Vs?
(c). Derive an expression for the Thévenin equivalent resistance, Rout, facing capacitance Cl.
(d). Derive an expression for the low frequency input resistance, Rin, “seen” by the signal
Homework #01
2
Spring Semester, 2001
EE 348
University of Southern California
J. Choma, Jr.
source.
(e). Derive an expression for the net effective resistance, say Rte, established across the terminals where resistance Re is connected.
(f). What is the significance of the time constant, RoutCl, to the frequency domain transfer function, H(jω) = Vo(jω)/Vs(jω)? Give an expression for this transfer relationship in terms of
Vot/Vs and the subject time constant.
(g). Give a simple expression for the 3–dB bandwidth of the circuit.
(h). Take Rs = 300 , Rl = 1,000 ,  = 120, rb = 190 , r = 1.5 K, Re = 100 , and Cl =
8 pF. Calculate the low frequency voltage gain, the output resistance, the time constant of
the circuit, the circuit 3-dB bandwidth, and the resistance parameter, Rte.
Problem #03:
Vs


Vc

L
R
Load Circuit

Interconnect
Lines
Source Circuit
Consider the simple RLC circuit in Fig. (P3), which can be viewed as a
simplified model of the high frequency parasitics that underlie an interconnect between two
integrated circuits on a circuit board. Interconnect lines have unavoidable distributed resistance,
inductance, and capacitance which serve to slow output responses to rapidly applied inputs. In
extreme cases, these high frequency parasitics can incur undesirable oscillations or, depending
on the electrical nature of the circuits they couple together, outright instability. Thus, you may
view this and the next problem as entailing significant mathematical “busy work,” but the problems herewith are very practical and are commonly addressed in some manner by integrated circuit designers.
Vs

Vr 

Vl 
C

Vc

Fig. (P3)
(a). The quality factor, Q of the circuit at hand is the ratio of the reactance of the inductor to the
series resistance at the resonant frequency, say ωo, of the circuit. Show that Q is given by
1
1 L
Q 

.
o RC
R C
(b). Derive expressions for the transfer functions, Vr(jωo)/Vs(jωo), Vl(jωo)/Vs(jωo), and
Vc(jωo)/Vs(jωo). Use these functions to demonstrate that the magnitudes of the capacitor
voltage, Vc, and the inductor voltage, Vl, are Q–times larger than the magnitude of the
source voltage, Vs, at the resonant frequency of the circuit.
(c). In terms of Q and ωo, determine the 3–dB bandwidth, say ωb, of the circuit transfer function, Vc(jωo)/Vs(jωo). Using EXCEL or other suitable software, plot the normalized bandwidth, ωb/ωo, versus Q for 0 < Q  6.
(d). Show that in the steady state and at circuit resonance, the energy delivered to the inductor
Homework #01
3
Spring Semester, 2001
EE 348
University of Southern California
J. Choma, Jr.
is the negative of the energy delivered to the capacitor. Give an engineering interpretation
of this observation.
Problem #04:
Reconsider the circuit of Fig. (P3) under the condition that the source voltage, Vs, is an idealized unit step function. Moreover, take the capacitor voltage, Vc, as the
response to this unit step excitation. In an ideal interconnect between two circuits, we would
want the output (Vc) to respond instantaneously to the applied input. Clearly, this type of
response is unrealizable because the capacitor prohibits instantaneous voltage changes. But in
the steady state, the capacitor behaves as an open circuit and the inductor emulates a short circuit, thereby allowing the output to follow faithfully the applied input. This ability to follow the
input is a desirable trait, but questions must be raised as to how much time must elapse before
the steady state is closely approximated.
(a). Show that the transfer function, say H(s), of the circuit is of the form,
H( s ) 
Vc ( s )
Vs ( s )

H( 0 )
 2
1  

 n

 s
s  



 n




2
.
Provide analytical expressions for H(0), the damping factor, ζ, and the undamped natural
frequency, ωn, and give engineering interpretations of each of these parameters. Relate ζ
and ωn to Q and ωo, respectively, as introduced in the preceding problem.
(b). What are the initial and steady state time domain values of the capacitor voltage response,
vc(t)?
(c). Assume that the circuit is underdamped; that is, ζ < 1. Determine the time domain capacitor voltage, vc(t), and cast this voltage in the form,
vc ( t )  vc (: )  ve ( t ) ,
where ve(t) can be interpreted as an “error” signal between the steady state, or ultimately
desired, response and the actual time domain response. Use EXCEL or other suitable
software to plot the error signal versus the normalized time, ωnt, for damping factor, ζ,
values of 0.25, 0.5, 1 2 , and 0.9.
(d). The one percent settling time, ts, is the time required for the magnitude of the unit step
response to achieve and forever maintain its steady state value to within ±1%; that is,
ve  ts   0.01 vc (: ) .
Derive a relationship for this settling time in terms of damping factor. What is the minimum damping factor commensurate with an error signal that is never any larger than one
per cent of the steady state response? For a 1% settling time of 1 nS, what is the minimum
tolerable circuit resonant frequency?
Homework #01
4
Spring Semester, 2001