EE 348:
Lecture Supplement Notes SN2
Semiconductor Diodes:
Concepts, Models, & Circuits
22 January 2001
Outline Of Lecture
• Rectification
• Semiconductor Diode
 Circuit Schematic Symbol
 Simplified Volt-Ampere Characteristic
 Model
 Static Volt-Ampere Relationship
 Time Domain Charge Control Model
• Diode Circuits
 Half Wave Rectifier
 Full Wave Rectifier
 Simple Limiter
EE 348 – Spring 2001
J. Choma, Jr.
Slide 44
Power Supply System
Sinusoidal
Voltage
Source
1
AC/DC
Converter
(Rectifier)
2
Lowpass
Filter
3
Voltage
Regulator
VDC
4
L
O
A
D
IDC
• System
 Voltage At “1” Has Given RMS Value And Zero Average Value
 Voltage At “2” Has Non-Zero Average Value; It Is A Time-Varying,
Harmonically Rich Half Or Full Wave Rectified Sinusoid
 Lowpass Filter Attenuates Harmonics At “2” To Produce Constant,
Time-Invariant Voltage At “3”
 Regulator Produces A Very Small Output Resistance Seen Looking
Back From “4”
• Load
 Effective Load Resistance Is VDC/IDC
 Voltage Source Nature At “4” Produces Near Constant VDC,
Regardless Of Current Value, IDC
EE 348 – Spring 2001
J. Choma, Jr.
Slide 45
SW
AC To DC Conversion
160
Vo

Vs

Rl
I/O Voltage (volts)
Rs
Output Voltage
120
80
40
0
-40 0
90
180
270
360
450
540
630
720
-80
-120
Input Voltage
-160
Zth

Vth

I
V
Load
Load
Linear
Network
I
V
General System
Thévenin Model
Zth

Vth

I
V
Normalized Time,  t (degrees)
Zl

Vl
Linear Load
• Sinusoid Input: Vs  V p Sin t 
• Output: Vo  0 , when SW is open; Vo  

V , when SW is closed
R R  s
s
 l
Rl
• Open Switch SW Whenever Vs < 0
• Plot Assumes Vs = 110 VRMS & Rl = 3Rs
EE 348 – Spring 2001
J. Choma, Jr.
Slide 46
SW
Average Output Voltage
160
Vo
I/O Voltage (volts)
Rs

Vs
Rl

Output Voltage
120
80
40
0
-40 0
90
180
270
360
450
540
630
720
-80
-120
Input Voltage
-160
Normalized Time,  t (degrees)
• Average Value Calculation
2

1  Rl 
1  Rl 
Voavg 

V p Sin x dx 

V p Sin x dx



2  Rl  Rs 
2  Rl  Rs 
o
o


V p  Rl 
Voavg 

  37.1 volts

  Rl  Rs 
• Conversion Efficiency Problem
EE 348 – Spring 2001
J. Choma, Jr.
Slide 47
Semiconductor Diode
i(
)
dt
• Schematic Symbol
 vd(t)
• Volt-Ampere
Characteristic
Equation
id ( t ) 
dQd ( t )
Qd ( t )
t
dt
id ( t )  C j ( vd )
• Parametric Definitions

dvd ( t )
dt
, for vd ( t )  0
, for vd ( t )  0
 Qd(t)  Excess Charge Stored In PN Junction
 Qd(t)  0: Diode Is Forward Biased
 Qd(t) < 0: Diode Is Reverse Biased Or Back Biased
 t
 Storage Time Constant (nSec –to- pSec)
 vd(t)  Diode Voltage (Generally < 800 mV)
 id(t)  Diode Current (Value Depends On Junction Area)
 Cj(vd)  Junction Depletion Capacitance
EE 348 – Spring 2001
J. Choma, Jr.
Slide 48
Semiconductor Diode Models
Cd(vd )
id(t)
id(t)
 vd(t) 
Cj(vd )
id(t)
 vd(t) 
 vd(t) 
Qd(t)/t
Schematic
Diagram
Forward
Bias
• Charge Function
• Forward Bias
• Reverse Bias
EE 348 – Spring 2001
Reverse
Bias

Qd ( t )  t I s e
id ( t ) 
dQd ( t )
C d ( vd ) 

vd ( t ) nVT
Qd ( t )
t
dt
dQd ( t )

dvd ( t )
id ( t )  C j ( vd )
VT  kT q
dQd ( t ) dvd ( t )
Qd ( t )



dvd ( t )
dt
t
t I s vd ( t ) nVT
e
nVT
dvd ( t )
J. Choma, Jr.

1 ;
dt
;
C j ( vd ) 
C jo

vd ( t ) 
1 


V j 

m
Slide 49
Diode At DC Steady State
id(t)
ID
ID

 vd(t) 
VD

Schematic
Diagram
 VD 
Qd(t)/t    Qd(VD )/t
Steady State,
Forward Bias
Steady State
Forward Bias Model
• Steady State
 Input Voltage Is Constant
 Capacitances Behave As Open Circuits
• Forward Bias Current (VD  0)
ID 
Qd ( t )
t

VD nVT
 Is e

VD nVT
 1  I se
• Reverse Bias Current (VD < 0)

VD nVT
ID  Is e
EE 348 – Spring 2001

 1   Is  0
J. Choma, Jr.
Slide 50
Diode DC V–I Characteristic
Forward Current (mA)
36
30
24
18
12
6
0
-0.5
-0.375 -0.25 -0.125
0
0.125
0.25
0.375
0.5
0.625
0.75
Forward Voltage (volts)
Is = 10 fA; T = 27 °C; n = 1
EE 348 – Spring 2001
J. Choma, Jr.
Slide 51
Piecewise Linear Approximation
• Two Segment Approximation
 ID = 0 For VD  V
 ID – IQ = (VD – VQ)/rD For VD  V
 IQ  Expected Quiescent, Or DC, Current Through Diode
 VQ  Corresponding Quiescent, Or DC, Diode Voltage
 rD  Incremental Diode Resistance At (IQ, VQ)
 V  Threshold Or Cut In Voltage Of Diode
• Operation For Diode Voltage Above Threshold

 Current
ID  Is e
 Slope
dI D
dVD
VD nVT
1
VQ
rD


VD nVT
 1  I se
Is
VQ nVT
e
nVT

VQ nVT
; IQ  I s e
IQ
nVT


 Threshold I  I  V  V  r  0  I  V  V
D
Q
D
Q
D
Q

Q rD
V  VQ  nVT  VQ
EE 348 – Spring 2001
J. Choma, Jr.
Slide 52
Piecewise Linear DC Diode Model

V
SW
VD
 VD 
VD
ID = 0
 VD 
rD
ID

36
30
Forward Current (mA)
ID

V
24
18
Piecewise
12
Linear
Actual
6
|
V
 VD 
0
-0.5
-0.375 -0.25 -0.125
0
0.125
0.25
0.375
0.5
0.625
0.75
Forward Voltage (volts)
• Model Parameters
 Threshold Voltage, V, Generally Around 700 mV For Silicon
 For Germanium Diodes, V Is Closer To 200 mV
 Diode Resistance, rD, Generally Around A Few Ohms
• Emulates Switch With Resistance And Offset
 Switch Closed For VD  V; Switch Open For VD < V
 Generally rD Is Negligibly Small
 For Large Applied Voltages, V Can Often Be Ignored
EE 348 – Spring 2001
J. Choma, Jr.
Slide 53
Half Wave Rectifier
ID
rD ID  V 
  VD 
Vo
Rs
Rs

Vs

Rl

Vs
• Reverse Bias
Vs  V p Sin t  


• Forward Bias
EE 348 – Spring 2001
Vo
Rs
  VD 

Rl

Schematic
Diagram
  VD 
Vo
Vs
Forward-Biased
Diode

Rl
Reverse-Biased
Diode
VD  Vs  I D Rs  Vo  V  Vs  V  Vo  I D Rs
 I D  0  Vo  0 , whenever Vs  V
Vs  V

Rl
Vo  
R r R
D
l
 s
J. Choma, Jr.

 Vs  V




Slide 54
Filtered Half Wave Rectifier
ID
rD ID  V 
  VD 
Vo
Rs
Rs

Vs

Rl

Schematic
Diagram
Cl
Vs
  VD 
Vo
Vo
Rs
  VD 

Rl

Diode Is Conductive,
Capacitor Charges
Cl
Vs

Rl  Cl

Diode Is Not Conductive,
Capacitor Discharges
• Load Resistance, Rl, Is Ratio Of Desired DC
Output Voltage –To– Desired DC Output Current
• Diode Conducts (Vs  Vo + V)
 Capacitor Charges With Time Constant, [Rl||(rD + Rs)]Cl
 For Small Time Constant, Output Voltage Follows Input
 Maximum Output Voltage


Rl
 V p  V
To Which Capacitor Charges: Vomax  

 Rl  rD  Rs 
EE 348 – Spring 2001
J. Choma, Jr.


Slide 55
Filtering–Cont’d
• Diode Non-Conductive
 Capacitor Voltage Does Not Change Instantaneously
 When Capacitor Charges To Its Maximum Voltage And The Input
Sinusoid Diminishes from Its Maximum Value, The Diode Open
Circuits And The Capacitor Discharges Through The Load
Resistance, Rl
 V  V
D
Vo  Vomax e
 t Rl C l
Rs
o
Vomin  Vomax e
T p Rl Cl


 Diode Begins To
V
R
s
l
 Cl
Conduct Again

When The
Unfiltered Output
Rises To Meet The
Decaying Capacitor Voltage
At Time Tp. At This Point, The Output Voltage Is Vomin
 See Plots On Next Slide
EE 348 – Spring 2001
J. Choma, Jr.
Slide 56
Waveforms: Capacitive Filter
Ripple, Vr
12
8
Voltage (volts)
Vomax
Vomin
Unfiltered
Output
Filtered
Output, V o
4
0
0
3
7
10
14
17
21
24
28
31
35
38
42
45
49
-4
DT
-12
t = Tp
Input: V s
t=0
-8
Time (mSEC)
EE 348 – Spring 2001
J. Choma, Jr.
Slide 57
Ripple of Filtered Rectifier
• Characteristic Voltage Equations
Vo  Vomax e
 t Rl C l
Vomin  Vomax e
T p Rl Cl
• Ripple Equations
T
•
RC
Vr  Vomax  Vomin  Vomax  Vomax e p l l
Tp
Vr
1
T p Rl C l
r 
 1 e


, for Rl C l  T p
Vomax
Rl C l
f Rl C l
  VD  Vo
Example
Rs
r  5%


Cl
f  60 Hz
 C l  667  F
Vs
Rl  Cl

100
Rl  500 

• Non-Ideal Large Capacitance
EE 348 – Spring 2001
J. Choma, Jr.
Slide 58
Diode Conduction Time
12
Vomax
8
Voltage (volts)
Vomin
Unfiltered
Output
Filtered
Output, V o
4
0
0
3
7
10
14
17
21
24
28
31
35
38
42
45
49
-4
DT
-8
Input: V s
0
Tp
-12
Time (mSEC)
Neighborhood Of Time t = 0
Reasonable
Result
vo ( t )  Vomax Cos t
vo (  DT )  Vomin  Vomax Cos( DT )
Vr  Vomax  Vomin  Vomax  1  Cos( DT )
 DT  2 

Vr  Vomax 


2


EE 348 – Spring 2001

DT 
2Vr

2r
Vomax
J. Choma, Jr.
Slide 59
Maximum Diode Current
12
Vomax
8
Voltage (volts)
Vomin
Unfiltered
Output
iD(t)
Filtered
Output, V o
4
vo(t)
Rs
0
0
3
7
10
14
17
21
24
28
31
35
38
42
45
-4
Vs
DT
-8
Input: V s
0

49

Rl
Cl
Tp
-12
Time (mSEC)
Diode Current
v (t )
dv ( t )
iD ( t )  o
 Cl o
; vo ( t )  VomaxCos(  t )
Rl
dt
Occurs At Diode Cut
In Point, t = –DT; Load Voltage Nearly Constant At Vomax
I Dmax 
Vomax
Rl
  Vomax C l Sin( DT ) 
Vomax 
I Dmax 
 1  2
Rl 
EE 348 – Spring 2001
Vomax
Rl

2 
  I DC  1  2 

r 

J. Choma, Jr.
  C l Vomax 2 r
2 

r 
Slide 60
Transformer Input

Vs1

ID
N:1

Vs2

Secondary
Winding
Primary
Winding
Is
Is

Vs1

Rs

Vs
ID
N:1
Vo

Vs2

Rl

Cl
Transformer
• Ideal Transformer
Vs1  NVs2 ; I D  NI s
 N Is Turns Ratio; Generally, N >>1
 Voltage On Primary Winding Is Stepped Down By Factor Of N
 Current In Primary Winding Is Stepped Down By Factor Of N
• Impedance Transformation
 Set Vs = 0 To Find Effective Source Resistance Seen By Diode
 Marked Resistance Reduction Vs2
Vs1 N
Vs1  I s
Rs
ID
EE 348 – Spring 2001
J. Choma, Jr.

 NI s

N
2

N2
Slide 61
Full Wave Rectifier
Cl
ID1 D1
Is
Rs

Vs

N:1

Vs1

N:1

Vs2


Vs3

Rl
Il
Vo
ID2 D2
• Center–Tapped Transformer
• Operation
Vs2  Vs3 
Vs1
N
 When Vs1 Is Positive, Vs2 = Vs3 > 0  ID2 = 0 & Il = ID1
 When Vs1 Is Negative, Vs2 = Vs3 < 0  ID1 = 0 & Il = ID2
 Result Is Full Wave Sinusoid For Unfiltered Case
EE 348 – Spring 2001
J. Choma, Jr.
Slide 62
Full Wave Performance
• Half Wave Analysis Can Be Replicated With
Minor Modifications
• Unfiltered Average Is Twice As Large As Half
Wave Case Because Current Is Now
Continually Supplied To Load
• Ripple Is Factor Of Two Smaller Because
Capacitor Now Decays For Only ½ Period
r 
Vr
Vomax
 1 e
T p Rl Cl

Tp

Rl Cl
1
2 f Rl C l
, for Rl C l  T p
 For Same Ripple, Filter Capacitor Can Be ½ As Large In Full
Wave Rectifier As In Half Wave Unit
 Maximum Diode Current, Expressed In Terms Of Ripple, Is The
Same As for Half Wave Case
EE 348 – Spring 2001
J. Choma, Jr.
Slide 63
Bridge Full Wave Rectifier
Il
D
2

Rl
1A
D
Vs
D
2A

1
D
Rs
Cl
• Operation
 When Vs > 0, Current Flows From Vs Through D1-Rl-D1A-Back To Vs
 When Vs < 0, Current Flows From Vs Through D2-Rl-D2A-Back To Vs
 Full Wave Unfiltered Output Results
• Comments
 Two Threshold Voltages In Each Current Path
 Does Not Require Center Tap Transformer
EE 348 – Spring 2001
J. Choma, Jr.
Slide 64