Mehmet Can Vuran, Instructor
University of Nebraska-Lincoln
Acknowledgement: Overheads adapted from those provided by the authors of the textbook
Assembly languages for different processors often use
different mnemonics for a given operation.
 To avoid the need for details of a particular assembly
language at this early stage, Chapter 2 uses English
words rather than processor specific mnemonics.
 This would, hopefully, ease the learning of specific
assembly languages described in Appendices A–D:





Nios II (App. B) – RISC (used in 230L)
Coldfire (App. C) – CISC
ARM (App. D) – RISC
Intel IA-32 (App. E) – CISC
2
3


Translate D = A+B+C to assembly
Translation Process:
1.
In assembly, can only add two at a time, hence
D = A+B;
D = D+C
2.
Assign variables:
For safe keeping in memory: Locations named #A, #B, #C, and #D
Temporarily, to processor registers R1–R4 respectively.
(Can think of each variable as having a static image in memory and
dynamic image in registers.)
3. Code each assignment statement in part 1) to assembly.
4
Load
Load
Add
Load
Add
Store
R1, #A
R2, #B
R4, R1, R2
R3, #C
R4, R4, R3
R4, #D
# D = A+B
# D = D+C
5


Translate HLL Statement: D = A+B+C to
assembly, minimizing the use of registers
Key Idea: Not all variables are needed
concurrently in the registers for doing the
computation. Can reuse registers to minimize
their number.
6
Load
Load
Add
Load
Add
Store
R1, #A
R2, #B
R2, R1, R2
R1, #C
R2, R1, R2
R2, #D
• Note that both R1 and R2 are reused to represent different
variables during the computation.
• A good compiler tries to minimize register usage.
7
8

Number of operands: One, two, or three

Type: Arithmetic, Logical, Data Transfer,
Control Transfer

Instruction Length: Fixed or variable – we’ll
consider fixed

Addressing Modes: How operands are found
9



In many RISC architectures (including Nios II),
register R0 is defined to be a read-only,
constant register with value 0.
R0 = 0
Can use to implement new instructions with
existing ones, e.g.
 Add R1, R0, R2
== Move R1, R2
10



In the previous examples, Move is not really
implemented on the processor but the
assembler can translate it into a real
instruction.
In general, a pseudoinstruction can be
thought of as a macro translated by the
assembler into one or more ISA instructions.
One of the ways, the assembly language can
be made to appear richer than the ISA of the
processor.
11
Load
R1, #A
#A  ?
12
13



Register, absolute, and immediate modes
directly provide the operand or address
Other modes provide information from which
the effective address of operand is derived
For program that steps through an array, can
use register as pointer to next number and
use the Indirect mode to access array
elements:
Load R2, (R5)
14
15







Consider index mode in: Load R2, X(R5)
Effective address is given by [R5]  X
For example, assume operand address is
1020, 5 words (20 bytes) from start of array at
1000
Can put start address in R5 and use X20
Alternatively, put offset in R5 and use X1000
Base with index mode: Load Rk, X(Ri, Rj)
Effective address is given by [Ri]  [Rj]  X
16
R5
17
R5
18

Example:
for i=0, i<N, i=i+1
{Body of Loop}

Semantics of the three parts:
 The first part, i=0, done once, before the loop is
entered
 The second part, the condition, i<N, is evaluated.
 If true, the body of the loop is executed. Then the
third part, the re-initialization step i=i+1 is done and
the condition is reevaluated.
 The loop terminates when the condition becomes
false.
19
Register Map
for i=0, i<N, i=i+1
{Body of Loop}
Intermediate Code
i=0;
Loop: if(!(i<N)) goto Exit
{Body of Loop}
i = i+1
goto Loop
Exit: …
i
N
R1
R2
Assembly Code
Move R1, #0
Loop: Branch_if_(i>=N) Exit
{Body of Loop}
Add R1, R1, #1
Branch Loop
Exit: …
20

Try implementing the following program
control constructs:
 If (condition) then {…} else {…}
 While (condition) {Body of Loop}
 Do {Body of Loop} until (condition)
21

Example
 for i=0, i<N {A[i] = A[i]+1}


Maintain the base A[0] and offset of A[i] from
A[0] in two separate registers.
Register Map:
i
N
A[i]
#A=Address A[0]
Offset A[i]
R1
R2
R3
R4
R5
22

i
N
A[i]
Address A[0]
Offset A[i]
R1
R2
R3
R4
R5
Initialization: R5 = 0; R4 = Address of (A[0])
 Code:

Move R5, #0; Load R4, #A
Body of Loop:
 Code:
Load
Add
Store
Add
R3,
R3,
R3,
R5,
(R4,R5) # R3 = A[i]
R3, #1
(R4,R5) # A[i] = A[i]+1
R5, 4
# Update offset for the next
23

Maintain pointer to A[i] in a register

Initialization: R4 = Address of A[0]
Load R4, #A

Body of Loop:
Load
Add
Store
Add
R3,
R3,
R3,
R4,
(R4)
R3, #1
(R4)
R4, 4
# R3 = A[i]
# A[i] = A[i]+1
# Update pointer to array element
24

Find the max of N numbers:
A[0], A[1], …, A[N-1].

HLL Code:
Max = A[0]
for i=1, i<N {
if(A[i]>Max) Max = A[i]
}
25
Max = A[0]
for i=1, i<N {
if(A[i]>Max) Max = A[i]
}
Variable: Max
Register
R1
i
#N =
(Addr. N)
A[i]
#A=
Addr. A[0]
R2
R3
R4
R5
Assembly Code
Intermediate Code
Loop:
Skip:
Max = A[0]
i=1
if(!(A[i])>Max)) goto Skip
Max = A[i]
i = i+1
if(N>i) goto Loop
Loop:
Skip:
Note: R2 is reused after the for loop
to store the address #Max
Move
R3, #N
Load
R3, (R3)
Move
R5, #A
Load
R1, (R5)
Move
R2, #1
Add
R5, R5, #4
Load
R4, (R5)
Branch_if_(R1>=R4) Skip
Move
R1, R4
Add
R2, R2, #1
Branch_if_(R3>R2) Loop
Move
R2, #Max
Store
R1, (R2)
26

For another example of array processing
using a for loop:
 Read and study the LISTADD example, Section
2.4.3 (pp. 45–47) of the textbook.
27



In the last example, “Load R5, #A” cannot be
a RISC ISA instruction if #A is an absolute 32bit address. Why?
Because it is a pseudoinstruction that must
be expanded to real instruction.
General problem, solved in RISC processors
by assembling 32-bit constants in two parts:
high and low, e.g.
Load_high
Add
R5, #A31-16
R5, R5, # A15-0
28





Mnemonics (LD/ADD instead of Load/Add)
used when programming specific computers
The mnemonics represent the OP codes
Assembly language is the set of mnemonics
and rules for using them to write programs
The rules constitute the language syntax
Example: suffix ‘I’ to specify immediate
mode
ADDI R2, R3, 5 (instead of #5)
29







Other information also needed to translate
source program to object program
How should symbolic names be interpreted?
Where should instructions/data be placed?
Assembler directives provide this information
ORIGIN defines instruction/data start position
RESERVE and DATAWORD define data storage
EQU associates a name with a constant value
30
31
Nios II
Assembly
Lang.
Address Label
Assembler Directive
Comment
Pseudo
-op
Operation
Operands
Register
Operands
Immediate
Operand
Memory
Addresses
Assembled
Machine
Code
32
35
Register names should
always in lower-case in
Nios II assembler
 Other symbols, e.g.
labels, are case-sensitive
 r0 is constant 0
 Don’t use r1 in your
programs.
 r2–r23 can be freely used
as general-purpose regs.

36
37

Load
 Form
ldw r2, 20(r3)
/* Load word instruction */
 Can also apply to bytes and halfword (ldb, ldh)
 Can control sign extension for byte and halfword
operand by using ldb (sign extended) or ldbu (sign
not extended)

Store: Similarly
38




mov
movi
movui
movia
ri, rj
ri, value-16
ri, value-16
ri, LABEL
/* 16-bit value */
/* unsigned */
/* 32-bit value –
typically an address */
 Assembler implements as:
orhi
ori
ri, r0, LABEL_HIGH
ri,ri, LABEL_LOW
39

Form
 br
 beq
LABEL
ri, rj, LABEL
where LABEL is 16-bit offset relative to PC
 Signed and Unsigned versions, e.g, beq and
bequ
 Full range of comparisons:
 beq, bne, bge, bgt, ble, plus their unsigned versions
40


Move type already mentioned
Subtract-Immediate:
subi

ri, rj, value-16 == addi ri, rj, -value-16
Branch Greater Than Signed
bgt
ri, rj, LABEL == blt
rj, ri, LABEL
41



.org
.equ
.byte
Value
/* ORIGIN */
LABEL, Value /* LABEL = Value */
expression /* Places byte size data
into memory */
 .halfword and .word work similarly


.skip
.end
size /* Reserves memory space */
/* End of source-code file */
42
Chapter 2
Loop:
Skip:
Move
R3, #N
Load
R3, (R3)
Move
R5, #A
Load
R1, (R5)
Move
R2, #1
Add
R5, R5, #4
Load
R4, (R5)
Branch_if_(R1>=R4) Skip
Move
R1, R4
Add
R2, R2, #1
Branch_if_(R3>R2) Loop
Move
R2, #Max
Store
R1, (R2)
Nios II
Loop:
Skip:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
r3, N /* addr. N */
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, Loop
r2, Max
r6, (r2)
Note: R1 is mapped to r6 because r1 is reserved as an
assembler temporary register in Nios II.
43
Nios II
Loop:
Skip:
Max:
N:
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, Loop
r2, Max
r6, (r2)
2000
/* Optional */
4
/* Reserve 4 bytes for Max */
20
/* Reserve word for N, initialized to 20 */
80
/* Reserve 80 bytes, or 20 words, for array A */
44





From source program, assembler generates
machine-language object program
Assembler uses ORIGIN and other directives
to determine address locations for code/data
For branches, assembler computes ±offset
from present address (in PC) to branch target
Loader places object program in memory
Debugger can be used to trace execution
45
Loop:
Skip:
Max:
N:
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, Loop
r2, Max
r6, (r2)
2000
4
20
80

Consider two-pass
assembly relative to
starting address of 0:
 Pass 1 builds the symbol
table
 Pass 2 generates code
46
0
Loop:
Skip:
Max:
N:
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, Loop
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
undefined
47
0
4
8
Loop:
Skip:
Max:
N:
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, Loop
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
undefined
A
undefined
48
0
4
8
12
16
20 Loop:
Skip:
Max:
N:
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, Loop
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
undefined
A
undefined
Loop
20
49
0
4
8
12
16
20:
24
28
Skip:
Max:
N:
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, Loop
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
undefined
A
undefined
Loop
20
Skip
undefined
50
0
4
8
12
16
20:
24
28
32
36 Skip:
Max:
N:
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, Loop
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
undefined
A
undefined
Loop
20
Skip
undefined -> 36
51
0
4
8
12
16
20:
24
28
32
36:
40
Max:
N:
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, Loop20
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
undefined
A
undefined
Loop
20
Skip
36
52
0
4
8
12
16
20:
24
28
32
36:
40
44
Max:
N:
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, 20
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
undefined
A
undefined
Loop
20
Skip
36
Max
undefined
53
0
4
8
12
16
20:
24
28
32
36:
40
44
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
2000 Max:
N:
.word
A:
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, 20
r2, Max
r6, (r2)
2000
.skip
4
20
80
Symbol Table
Symbol
Value
N
undefined
A
undefined
Loop
20
Skip
36
Max
undefined ->2000
54
0
4
8
12
16
20 :
24
28
32
36:
40
44
2000:
2004: N
A:
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, 20
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
undefined ->2004
A
undefined
Loop
20
Skip
36
Max
2000
55
0
4
8
12
16
20:
24
28
32
36:
40
44
2000:
2004:
2008 A:
2088
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
…
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, 20
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
2004
A
undefined->2008
Loop
20
Skip
36
Max
2000
56
0
4
8
12
16
20:
24
28
32
36:
40
44
2000:
2004:
2008:
2088
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
…
r3, N
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, 20
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
2004
A
2008
Loop
20
Skip
36
Max
2000
57
0
4
8
12
16
20:
24
28
32
36:
40
44
2000:
2004:
2008:
2088
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
…
r3, N 2004
r3, (r3)
r5, A
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, 20
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
2004
A
2008
Loop
20
Skip
36
Max
2000
58
0
4
8
12
16
20:
24
28
32
36:
40
44
2000:
2004:
2008:
2088
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
…
r3, 2004
r3, (r3)
r5, A2008
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip
r6, r4
r2, r2, 1
r3, r2, 20
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
2004
A
2008
Loop
20
Skip
36
Max
2000
59
0
4
8
12
16
20:
24
28
32
36:
40
44
2000:
2004:
2008 A:
2088
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
…
r3, 2004
r3, (r3)
r5, 2008
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, Skip36
r6, r4
r2, r2, 1
r3, r2, 20
r2, Max
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
2004
A
2008
Loop
20
Skip
36
Max
2000
60
0
4
8
12
16
20:
24
28
32
36:
40
44
2000:
2004:
2008 A:
2088
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
…
r3, 2004
r3, (r3)
r5, 2008
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, 36
r6, r4
r2, r2, 1
r3, r2, 20
r2, Max2000
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
2004
A
2008
Loop
20
Skip
36
Max
2000
61
0
4
8
12
16
20:
24
28
32
36:
40
44
2000:
2004:
2008 A:
2088
movia
ldw
movia
ldw
movi
addi
ldw
bge
mov
addi
bgt
movia
stw
.org
.skip
.word
.skip
…
r3, 2004
r3, (r3)
r5, 2008
r6, (r5)
r2, 1
r5, r5, 4
r4, (r5)
r6, r4, 36
r6, r4
r2, r2, 1
r3, r2, 20
r2, 2000
r6, (r2)
2000
4
20
80
Symbol Table
Symbol
Value
N
2004
A
2008
Loop
20
Skip
36
Max
2000
62