Quiz 4 – EECS 270, Spring '05
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This quiz is graded out of 100 points and is worth about 4% of your class grade. You will have 20 minutes
for this quiz. Closed everything including calculators! To receive partial credit, work must be shown.
1. Fill-in-the-blank: [20 points/4 each]

_________________ means that the memory loses its state when power is
turned off.

The D in DRAM stands for __________________ and means that
_____________________________________________

In a 16 by 16 memory array, if the output is to be 1 bit per address, you need
_____________ address lines.

A 2 MHz clock has a period of ________________ nano-seconds.

A clock with a period of 5ms has a frequency of ____________ KHz.
2. Clearly define the following terms [10 points/5 each]

Set-up time

Hold time
3. Using D-flip-flops, MUXes, and standard gates, design a 4-bit shift-left shift register.
The outputs are Q[3:0], where Q3 is the left-most bit. It takes the following inputs:
 C. If C=1, shift left, else hold current values.
 Z. If shifting left, Q0=Z. Otherwise ignore Z.
[30]
3.Consider the following state-transition diagram:
X
!X
A
!X
B
!X
C
X
X
There is one output, Z, which is 0 when in state A and 1 in states B and C.
Using standard logic notation, write the logic equations for the next_state and output
logic for the above state-transition diagram. For the states, you are to use an encoding
of Q[2:0] where A=001, B=010, and C=100. Finally, any unused state encodings
should be treated as don’t cares. [40]
Q2*=
Q1*=
Q0*=
Z=