BPM Signal Processing
T. Straumann, M. Cecere, E. Medvedko, P. Krejcik
SLAC
B. Lill
ANL
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Overview for Stripline BPMs
Requirements/Engineering Constraints
Status
Current Frontend Design
Timeline for next 12 months
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Objective
High precision/resolution BPM Electronics
5um resolution (R ~ 12mm)
drift < 5um/h
low bunch charge: 0.2..1nC
Stripline sensitivity: V = (a-b)/(a+b) = 2 r / R
dynamic range > 60dB + 20dB
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Engineering Constraints
SNR expressed as position noise (LINAC Stripline; 150MHz)
dB[ r/1um ] = NF – dB[ q/1nC ] - ½ dB[ BW/1MHz ]
8dB
> NF + 14dB(.2nC) – 10dB (10MHz)
noise figure including cable losses
stripline signal level based on estimation
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Baseband vs. Mixer
Baseband
•
Simpler
Mixer
•
More signal at higher freq.
•
Cheaper
•
Proven solution
•
Use existing cables (?)
•
ADC performs better at IF
Only marginally meets
resolution requirements
Oct. 24-27, 2005
LCLS-Week
LO generation + distribution
New cables in LINAC
needed
LCLS Control Group
Lcls-controls@slac.stanford.edu
System Overview
Calibration scheme
does not require extra
cables
Direct digitization
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Status
VME Digitizers + basic driver software available
Echotek
Joerger
SIS
New card ordered (13ENOB, 130MSPS, 700MHz input BW)
First frontend design + prototype (E. Medvedko)
Engineer hired (M. Cecere)
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Frontend
f0 =150MHz (enough signal, ADC still well performing)
Low noise, 10MHz BW
Low distortion
Alias suppression
Build Prototype
Test (noise, stability, out-of band performance, linearity)
Final Design
Interface (form factor, control signals, status monitors)
Calibration
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
BPM Analog Front End
Baseband Design
Signal
from
BPM or
Hybrid
BPF#2
BPF#1
LNA
Frequency Selection
Filter
Low Noise Amplifier
Oct. 24-27, 2005
LCLS-Week
ADC
Band Pass
Filter
Undersampling
ADC
Final Amplifier
LCLS Control Group
Lcls-controls@slac.stanford.edu
Baseband Design
Component Selection Criteria
BPF#2
BPF#1
LNA
ADC
Freq./BW determine SNR
Sharp Rolloff (Anti-
>= 119MSPS
Low Insertion Loss
alias)
High Dynamic Range
Good OOB rejection
Flat Passband
BW>= 200MHz
Oct. 24-27, 2005
LCLS-Week
Low NF
High Gain*BW
Low Distortion
Low Distortion
Moderate Gain
@ High Output Level
LCLS Control Group
Lcls-controls@slac.stanford.edu
Timeline (Injector only)
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Calibration Bench Test
Measurement setup (not worse than required stability!!)
Test stability of calibration (splitters, BPM striplines)
Cross-talk issues?
Repeatability
Multiplexing (t/f)
Final design, integration
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
LCLS Cavity BPM Overview
RF BPM system current status
Planning for prototype testing
Planning for 8 LTU BPMs electrically identical to those in the
undulator.
Planning for 33 undulator BPMs
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Miteq X-Band Low Noise Receiver
Existing product line
WR 75 Waveguide Interface
Low Noise Figure (2.7 dB)
Prototype delivery date 12/10/05
Budgetary price for prototype $6500.00 (for 3 channels)
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Prototype Receiver Specification
Parameter
Specification Limit
Condition
RF Frequency
11.364 GHz
20.0 Celsius
Dx, Dy, Intensity
Input Peak Power
50 watts peak
No damage (limiter protection)
LO Frequency
11.424 GHz
20.0 +/- 0.2 Celsius
(2856 MHz*4)
1nC, 1mm offset, 200fs BL
LO Power Range
+10 dBm Max.
Provide LO for 3 down converters
IF Frequency
60 MHz Min.
20.0 +/- 0.2 Celsius
Noise Figure Dx and DY
2.7 dB Max.
20.0 +/- 0.2 Celsius
Noise Figure Intensity (reference)
4.0 dB Max.
20.0 +/- 0.2 Celsius
LO to RF Isolation
40 dB Min.
20.0 Celsius
LO to IF Isolation
45 dB Min.
20.0 Celsius
Output Power
+14 dBm
1 dB compression
Conversion Gain
25 dB typical
20.0 Celsius
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Long Lead Item Status
Receiver Prototype del. 12/10/05
Local oscillator del. 11/24/05
Waveguide del. 12/1/05
Waveguide calibration kit del. 12/9/05
CPI Vacuum windows 11/30/05
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
BPM System Test Approach
Phase I
Injector Test Stand ITS
Install single X-Band
Cavity and modified offthe-shelf down converter
receiver
Mount BPM on Piezo
two-axis translation stage
Oct. 24-27, 2005
LCLS-Week
Phase II
Bypass line test with PC
gun
Install three X-Band
Cavities BPMs
Bypass line test with PC
gun to start June 06
LCLS Control Group
Lcls-controls@slac.stanford.edu
Injector Test Stand ITS Beam
Parameters
Charge- 1 nC singlebunch
Bunch length- ~ 3 - 4 ps
FWHM for ps laser
Spot size on final screen
at 5.5 MeV
~ 0.75 mm rms, ps laser
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Phase I Data Acquisition Design Approach
Instrument three channel down converters with Struck SIS3301-105 ADCs 14-bit
 Single VME board will provide the data acquisition for 8
channels
 Epics driver complete
Digitize horizontal, vertical position and Intensity 0 to 1 volt
range
Fit Data to decaying exponential at 60 MHz
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Phase I Testing Objectives
 Test prototype Cavity BPM, down converter, and data
acquisition
 Generate preliminary compliance table to specification
 Gain operational experience to determine if translation stage
is useful, what are optimum operating parameters
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Phase I Schedule Milestones
Design and develop prototype Cavity BPM
Prototype non vacuum
Nov 05
Build single Cavity BPM
Dec 05
Cold Test
Dec 05
Install cavity BPM into ITS and Test
Jan 06
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Phase II Schedule Milestones
Refine design and develop First Article Cavity BPM and support hardware
Jan 06
Build 3 Cavity BPMs
Mar 06
Cold Test
May 06
Install cavity BPM into APS PAR/Booster bypass line and Test
June 06
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Phase II Testing Objectives
 First Article Prototypes evaluated
 Test three BPM separated by fixed TBD distance to determine
single-shot
 Complete test matrix
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
LTU and Undulator Planning
Receiver and LO housed in
shielded enclosure below
girder 20 watt power
dissipation maximum
Presently BPM output on wall
side
BPM output flexible
waveguide section allows
movement for alignment
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
BPM Mounting
BPM connects directly to
the girder.
Mechanical translation
stage used for alignment
BPM and Quad can be
pre-aligned independently
with respect to each other
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Undulator Planning
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Backup slides
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Baseband Design
Components
BPF#2
BPF#1
Cable
NF = 2-4dB
LNA
NF = 2-4dB
fo= 150MHz
BW = 10MHz
Lark Engineering
MS140-20-3CC
Insert. Loss = 5.8dB
-------------------------TTE filters
KB3T-150M-10M-50-3A
Insert. loss = 4.1dB
-------------------------Microwave Filter Co.
3MB10-150/10-SF/SF-1
Insertion loss = 3dB
Oct. 24-27, 2005
LCLS-Week
ADC
NF = 3dB
Sirenza
SGA-6589
G = 26dB
NF = 3.0dB
OIP3 = 33dBm
------------------Sirenza
SGA-4363
G = 18dB
NF = 3.1dB
OIP3 = 29dBm
Alias image
@ 30MHz
TI OPA847
GBW = 3.9GHz
Distortion -105dBc
Sawtek
854916
fo= 150MHz
BW = 10MHz
Insert. loss = 11dB
LTC2208
130MSPSmax
16-bit
700MHz BW
fsamp=119MHz
Req. jitter < 350fs
--------------------AD6645
105MSPSmax
14-bit
200MHz BW
fsamp=102?
Req. jitter < 600fs
LCLS Control Group
Lcls-controls@slac.stanford.edu
Baseband Design
Frequency Response
50.00
SystemInput
Final output
0.00
C
oax1
BPF1(1
50M
H
z)
-50.00
BPM signal
C
oax2
dBm
Input signal
-100.00
Cable losses
LN
A1
BPF2(1
50M
H
z)
O
pAm
p1
-150.00
O
pAm
p2
O
pAm
p3
-200.00
BPF3(1
50M
H
z)
-250.00
0
50
100
150
200
250
300
Frequency MHz
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Mixer Based BPM
Block Diagram
43MHz
400-800MHz
BPM
or
Hybrid
LNA
119MHz
RF
ADC
IF
LO
xN
Minicircuits
ZFM-2
1 – 1000 MHz
Conv Loss = 5.8dB
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Mixer Based Design
Frequency Response
50.00
S
yste
m
Input
C
o
a
x1
B
P
F1
(4
0
0
M
H
z)
C
o
a
x2
LN
A1
B
P
F2(4
0
0
M
H
z)
M
ix1
O
pa
m
p1
0.00
-50.00
mixer
dBm
LP
F1
(4
0
M
H
z)
O
pa
m
p2
BPM signal
O
pa
m
p3
O
pa
m
p4
-100.00
After coax
C
o
m
p1
2
C
o
m
p1
3
C
o
m
p1
4
C
o
m
p1
5
-150.00
C
o
m
p1
6
C
o
m
p1
7
C
o
m
p1
8
C
o
m
p1
9
C
o
m
p2
0
C
o
m
p2
1
-200.00
-250.00
0
C
o
m
p2
2
100
200
300
400
500
600
Frequency MHz
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
C
o
m
p2
3
C
o
m
p2
4
Software Tasks
Evaluation / test software
BPM Processor
Processing algorithm
Real-time tasks:
data acquisition and processing
timing
history buffers
Calibration
Integration (SLC-aware IOC, timing, feedback)
Slow controls (gain, calib, status monitors, alarms)
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Integration; Hardware
Clock generation and distribution
Timing; triggers/gates
Calibration signal generation and distribution
Controls: gain, calib. mux
Power
Status monitors
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Integration; Software
Timing
SLC-aware layer
Shot-to-shot feedback
High-level applications (EPICS database)
Naming
Real-time
Sysadmin; infrastructure; network
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
PDRO local oscillator
11.424 GHz
(119 MHz x 96)
Phase lock to 119 MHz
ref 0 dBm +/- 3 dB
+13 dBm output power
In-Band Spurs <70 dBc
Phase noise depends on
119 MHz reference
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Noise Estimates
Sensitivity:
-58 dBm/0.2nC/1m
Minimum bit size: 16
bits/micron@ 0.2nC
Assumes 2 gain ranges for
75 dB
Noise floor <200 nm rms
Oct. 24-27, 2005
LCLS-Week
Parameter
Value
Thermal noise
-174 dBm/Hz
IF Bandwidth
20 MHz
Noise in-band
-101 dBm
Receiver 1 dB
compression
+14 dBm
Receiver gain
25 dB
Receiver noise figure
2.7 dB
LCLS Control Group
Lcls-controls@slac.stanford.edu
APS Test Objectives
Develop a cavity BPM that
meets system requirements
and can be manufactured
economically
Develop simulation model that
correlates to prototype data
Transition from prototyping to
production
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
ITS Installation
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu
Cost Savings
Reduce the dipole cavity
outputs from 4 ports to 2
ports
Terminate the unused
ports in vacuum
Eliminate 2 transitions, 2
windows, waveguide, 2
magic tees
Prove resolution and
offset performance
Oct. 24-27, 2005
LCLS-Week
LCLS Control Group
Lcls-controls@slac.stanford.edu