IMPLEMENTATION OF STEREO SOUND ENHANCEMENT ON FPGA
Pranav Harishkumar Sheth
B.E., Charotar Institute of Technology Changa, India, 2005
PROJECT
Submitted in partial satisfaction of
the requirements for the degree of
MASTER OF SCIENCE
in
ELECTRICAL AND ELECTRONIC ENGINEERING
at
CALIFORNIA STATE UNIVERSITY, SACRAMENTO
SPRING
2010
IMPLEMENTATION OF STEREO SOUND ENHANCEMENT ON FPGA
A Project
by
Pranav Harishkumar Sheth
Approved by:
__________________________________, Committee Chair
Jing Pang, Ph.D.
__________________________________, Second Reader
Preetham Kumar, Ph.D.
____________________________
Date
ii
Student: Pranav Harishkumar Sheth
I certify that this student has met the requirements for format contained in the University
format manual, and that this project is suitable for shelving in the Library and credit is to
be awarded for the Project.
__________________________, Graduate Coordinator
Preetham Kumar, Ph.D.
Department of Electrical and Electronic Engineering
iii
________________
Date
Abstract
of
IMPLEMENTATION OF STEREO SOUND ENHANCEMENT ON FPGA
by
Pranav Harishkumar Sheth
The main objective of this project is to understand the concept of stereo sound
enhancement techniques and implement a stereo sound enhancement algorithm on Altera
FPGA board. The algorithm I have implemented is based on the concept of taking spatial
information in audio components and enhanced it using attenuation, delay and filter
techniques. I have implemented the algorithm in Matlab with FIR band pass filter and
with moving average filter. I have verified the filters functionality with different orders of
filter. I have implemented the algorithm in verilog and simulated it using Synopsys-VCS
tool. After successful results in verilog simulation, I have implemented the algorithm on
Altera FPGA (Cyclone II 2C35) DE2 Board. I have used onboard audio Codec for audio
to digital conversion and SDRAM for data storage.
_______________________, Committee Chair
Jing Pang, Ph.D.
_______________________
Date
iv
ACKNOWLEDGMENTS
I would like to thank, Dr. Jing Pang for assigning me very interesting project on sound
processing. I explore digital sound processing from scratch though she helped me to learn
from basic and provide me valuable technical information. She always encouraged me to
work hard and achieved desired result. I really appreciate her help throughout entire
project.
I also want to thank Dr. Preetham Kumar for reviewing my project report as a second
reader.
Finally, I want to thank my parents and friends for their support and encouragement
throughout my master’s program. Without their guidance and support, this would not be
possible.
v
TABLE OF CONTENTS
Page
Acknowledgments......................................................................................................... v
List of Tables ............................................................................................................ viii
List of Figures ............................................................................................................. ix
Chapter
1. INTRODUCTION .....................................................................................................1
1.1 Background ................................................................................................. 1
1.2 Introduction ................................................................................................ 1
2. STEREO SOUND ENHANCEMENT TECHNIQUES ........................................... 3
2.1 Stereo Sound Enhancement Techniques and Their Effects ........................ 3
2.1.1 Effect of Intensity of the Signal .......................................................3
2.1.2 Effect of Insertion a Delay ...............................................................4
2.1.3 Effect of Phase Shift ........................................................................5
2.1.4 Effect of Frequency..........................................................................6
2.2 Stereo Sound Enhancement Algorithm ....................................................... 6
2.2.1 Spatial Sound Enhancement ............................................................6
2.2.2 Stereo Sound Enhancement Algorithm Architecture .......................8
2.2.3 Attenuation .......................................................................................9
2.2.4 Digital FIR Filter............................................................................10
2.2.5 Moving Average Filter...................................................................18
3. SOFTWARE DESIGN ..........................................................................................20
3.1 Design with FIR Band Pass Filter..............................................................20
3.1.1 Block Diagram ...............................................................................20
3.1.1.1 Sound file to digital samples & digital samples
to sound file conversion .....................................................21
3.1.1.2 Test Bench .........................................................................22
3.1.1.3 Subtraction .........................................................................23
vi
3.1.1.4 Attenuation .........................................................................23
3.1.1.5 Filter ...................................................................................23
3.1.1.6 Final Addition ....................................................................24
3.1.2 Signals used for Verilog Simulation ..............................................25
3.1.3 Simulation Result ...........................................................................26
3.2. Design with Distributed Arithmetic Filter ................................................27
3.2.1 LUT ................................................................................................28
3.2.2 Top LUT ........................................................................................29
3.2.3 Multiplication of Signed Binary Numbers .....................................29
3.2.4 Filter with LUT ..............................................................................31
3.2.5 Perl Script.......................................................................................32
4. HARDWARE DESIGN ........................................................................................ 33
4.1 Block Diagram for FPGA Implementation ................................................33
4.2 Stereo Top Module ....................................................................................34
4.3 Simulation Result ......................................................................................37
5. CONCLUSION AND FUTURE WORK ................................................................38
5.1 Conclusion .................................................................................................38
5.2 Future work ................................................................................................38
Bibliography ............................................................................................................... 39
vii
LIST OF TABLES
Page
1.
Table 1 Signals for Verilog Simulation ..............................................................25
2.
Table 2 Signed Multiplication Illustrations ........................................................30
3.
Table 3 Output Signals for Hardware Implementation .......................................35
viii
LIST OF FIGURES
Page
1
Figure 1 Effect of Intensity of Signal in Stereo Sound Enhancement .....................3
2
Figure 2 Effect of Insertion a delay in Signal in Stereo Sound Enhancement .........4
3
Figure 3 Effect of Phase Shift in Stereo Sound Enhancement.................................5
4.
Figure 4 Spatial Sound Enhancement Algorithm ....................................................7
5.
Figure 5 Stereo sound enhancement algorithm ........................................................8
6.
Figure 6 Effect of Attenuation .................................................................................9
7.
Figure 7 Block diagram for FIR filter with delay ..................................................10
8.
Figure 8 Frequency Responses for a Band Pass Filter with Passband from 20Hz to
20kHz ...................................................................................................................11
9.
Figure 9 Frequency Responses for a Band Pass Filter with Passband from 2kHz to
20kHz .....................................................................................................................13
10.
Figure 10 Frequency Responses for a Band Pass Filter with Passband from 400Hz
to 8kHz ...................................................................................................................14
11.
Figure 11 Frequency Responses for a Band Pass Filter with Passband from 4kHz
to 10kHz .................................................................................................................16
12.
Figure 12 Spectrum Result of a Band Pass Filter with Filter order 8th and 32nd ....17
13.
Figure 13 Block Diagram of a Moving Average Filter..........................................18
14.
Figure 14 Block Diagram for Verilog Simulation of Stereo Sound Enhancement
Algorithm ..............................................................................................................21
15.
Figure 15 Verilog Simulation Result .....................................................................26
16.
Figure 16 Architecture of Filter with LUT ............................................................32
17.
Figure 17 Block Diagram for Hardware Implementation ......................................33
ix
18.
Figure 18 Finite State Machine Diagram for Stereo Top Module .........................34
19.
Figure 19 Simulation Result for Hardware Implementation..................................37
x
1
Chapter 1
INTRODUCTION
1.1 Background
In digital media, quality of stereo sound is more enjoyable than mono sound. Stereo
sound is produced from more than one channel. There are several ways to mix two mono
sound channels to produce stereo sound. One method of stereo sound enhancement is
achieved by widening the stereo sound filed, so listener can enjoy clear and noiseless
sound with great feeling. This stereo sound field can be widened with proper location of
loudspeakers in the room to feel the stereo sound effect.
1.2 Introduction
This project focuses on the principle concepts of stereo sound enhancement. If we modify
phase, intensity and frequency of the sound in appropriate way, we can produce
significant amount of stereo sound effect. In this project, the stereo sound enhancement
algorithm is implemented in Matlab to verify the quality of the sound enhanced by the
algorithm. This algorithm can be implemented with different types digital FIR filters. In
this project moving average filter and bandpass filter with different orders are simulated
in Matlab. Based on the Matlab simulation, a band of pass filter of second order is
designed and simulated in Verilog. A distributed arithmetic filter of 32nd order is
implemented in verilog, after successful result of initial verilog design. This distributed
arithmetic filter uses look up table design approach. There are several constraints need to
2
be considered while implementing a design on FPGA. These constraints are logic
complexity and available hardware resources (size of FPGA, I/O & Memory), speed of
the execution and cost. Both designs are implemented on Altera FPGA board. If we
implement the algorithm with 32nd order FIR filter with multipliers and adders, it
consumes more hardware on FPGA. An algorithm with a distributed arithmetic filter with
a look up table approach is a realistic design. This filter provides good frequency
response because of higher filter order. This design consumes less hardware resources on
FPGA and it provides good stereo sound quality.
3
Chapter 2
STEREO SOUND ENHANCEMENT TECHNIQUES
This chapter will discuss about stereo sound enhancement principles. It will discuss about
stereo sound enhancement algorithm, digital FIR filter and moving average filter. In this
chapter, digital FIR filter’s Matlab simulations is presented with different filter orders
and cut off frequencies.
2.1 Stereo Sound Enhancement Techniques and Their Effects
There are several techniques by which stereo sound can be enhanced and the quality will
be improved according to the requirement. As the stereo sound has generally two
channels, we can achieve desired stereo sound effect by controlling few parameters
such as intensity of the signal, insertion a delay, phase shift, and frequency.
2.1.1 Effect of Intensity of the Signal:
Figure1. Effect of Intensity of Signal in Stereo Sound Enhancement [1]
4
The stereo sound effect can be generated by varying sound sources from different
channels. This effect can be realized by increasing the volume (intensity) of one channel.
The sound source in one channel, which reaches to the listener stronger is dominant. In
the diagram (a) above, left and right channel have same intensity so the person will feel
that the sound is coming from direction A. When left channel intensity is increased
compared to right channel the person will feel that sound is coming from left direction
[1].
2.1.2 Effect of Insertion a Delay:
Figure 2. Effect of Insertion a delay in Signal in Stereo Sound Enhancement [1]
If specific amount of delay is provided to the arrival of one channel then noticeable
amount of stereo sound effect is achieved. A delay is generated, when one loudspeaker of
5
one channel is placed away from the listener. Instead of altering the distance of
loudspeaker, same result can be produced if one channel is played with a delay. In the
diagram (b), the right channel has been delayed so listener will feel that, the sound is
coming from the left channel. The delay of 20miliseconds to 50miliseconds can play
significant role in stereo effect. It is advisable that the delayed channel should have
higher gain to keep the effect that channel in stereo sound [1].
2.1.3 Effect of Phase shift:
Figure 3 Effect of Phase Shift in Stereo Sound Enhancement [1]
According to figure (a), when both speakers are “in phase” it feels like the sound is
coming from A. Now, when phase of one channel is reversed it feels like sound is coming
from ‘B’. In figure (b), intensity of the left channel speaker will be reduced which will
create more stereo effect. When both channels loudspeakers are pushing out the sound in
6
one direction, it is called “in phase” and a listener feels the sound is coming from the
center. The “out of phase” means right channel’s loudspeaker is pushing out and left
channel’s loudspeaker is retracting. [1]
2.1.4 Effect of Frequency:
If we placed higher frequency components on one loudspeaker and low frequency on
another loudspeaker, it will create stereo effect. We can use more than one filter to gain
certain amount of frequency components. In that case, filter’s cutoff frequency plays
important role. The sharp cutoff frequency can reduce important part of audio signal.
Thus, type of filter and its frequency range will improve or worse the stereo sound effect
[1].
2.2 Stereo Sound Enhancement Algorithm
An algorithm is a circuit used to enhance the stereo sound. This algorithm is worked as
post processing of sound, which happens before playing the actual stereo sound. This
circuitry is fixed inside the stereo playback system. Any stereo playback system requires
two input channels and two output channels. Both input channels are processed through
this algorithm. Two loudspeakers are used as an output media to play output channels [2].
2.2.1 Spatial Sound Enhancement
The spatial sound enhancement algorithm exaggerates mono components available in two
input channels. For example, a common component of two input channels provides a
7
substantial mono component (M). Input channels can be expressed by these equations;
left channel (L = M+Li) and right channel (R = M+Ri). In these equations, Li and Ri are
specific sound components of their own channel’s and M is common component. The
difference of input channels (L – R) is equal to (Li - Ri). If we add (L – R) in to L will
give us Lo = M+2Li-Ri. This mathematical equation says that there is significant boost in
the output left channel (Lo) compared to original left channel. Likewise, if we subtract
(L-R) from R than we will get Ro = M+Li-2Ri. The inverted components (-Ri and -Li)
generates diffused sound. We can control these inverted components to reduce diffused
sound. If we provide some sophisticated filter to the new output channels and play, the
sound will create stereo sound effect [2].
Figure 4 Spatial Sound Enhancement Algorithm [3]
8
Algorithm shown in Figure 4 measures dissimilar components between two channels and
inserts the enhanced version of the dissimilar components in the output. If input channels
are very similar, there is less amount of dissimilar component, which needs good amount
of enhancement to produce stereo effect. On the other hand, if there is less difference in
input channels, then it needs less amount of enhancement. Both low pass and band pass
filters are used in parallel to filter the original sound. Filtered output gain is controlled
after input sound difference is measured. The final stereo sound will be signal dependent
[3].
2.2.2 Stereo Sound Enhancement Algorithm Architecture
RIGHT CHANNEL
LEFT CHANNEL
Stereo Sound
Source
LEFT CHANNEL
-
L-R
Delay
(0-50ms)
Attenuation
(0-30db)
RIGHT CHANNEL
-
R-L
Delay
(0-50ms)
Attenuation
(0-30db)
+
FINAL LEFT CHANNEL
Digital FIR
Filter
+
FINAL RIGHT CHANNEL
Digital FIR
Filter
Figure 5 Stereo Sound Enhancement Algorithm
This algorithm has two input channels (left channel & right channel). According to the
diagram, first stage is differentiator block, which will produce (L-R) and (R-L) signals.
9
These signals are passed through the delay block. In the delay block, the signal is delayed
up to 50milisecond to create stereo sound effect. The delayed signals are attenuated for
(0-30db). Once the signal is attenuated then it is passed through the digital FIR filter
block. A digital FIR filter will remove unwanted attenuated signal. The frequency range
for this filter is from 20Hz to 12000Hz. The final output signal (Left channel/ Right
channel) is addition of original signal and processed signal. The final stereo sound can be
listened with two channels. The final sound has significant amount stereo sound effect.
2.2.3 Attenuation
Figure 6 Effect of Attenuation
The intensity of the sound weakens when it passed through different materials. In sound
processing the original sound intensity is reduced, to achieve certain amount of gain before it is
10
processed, which helps to maintain the sound original components. In figure 6, original input
channel is attenuated by 30db. You can notice that sound intensity is reduced in the second
diagram.
2.2.4 Digital FIR Filter
Digital FIR filter enhances the signal by performing mathematical operation on the
signal. The equation of Nth order digital FIR Filter is written as under [4].
……….(1) [4]
In equation 1 N is filter order, y(k) is the filtered signal a(n) is the coefficient of a
sample and x(k-n) is the input signal [4].
Figure7. Block diagram for FIR filter with delay [4]
Figure 7 represents FIR filter with delay. Where Z-1 is the amount of delay applied to
each signal [4]. A band pass filter is simulated for stereo sound enhancement algorithm.
Digital FIR filter performance can enhanced by varying filter order and cut off frequency.
There are several tests performed to chose filter order and cut off frequency for better
stereo sound effect.
11
Figure 8 Frequency Responses for a Band Pass Filter with Passband from 20Hz to 20kHz
12
Figure 8 represents frequency response for 8th and 32nd order band pass filter with
passband from 20hz to 20kHz. In above figures, filter parameters are selected to design a
band pass filter, though its frequency response is similar to low pass filter. As per third
figure, 32nd order filter has sharper cut off frequency than the 8th order filter. In third
figure frequency components near to cut off frequency are suppressed more than the
figure 1. This test concludes that 32nd order filter provides better frequency response than
8th order filter. In this test filter passband frequency is 20Hz to 20Khz. This frequency
range human can easily listen. This frequency band cannot produce sufficient stereo
sound effect.
13
Figure 9 Frequency Responses for a Band Pass Filter with Passband from 2kHz to 20kHz
Figure 9 represents frequency response for 8th and 32nd order band pass filter with
passband from 2kHz to 20kHz. In above figure, 8th and 32nd filter has frequency response
for band pass filter compared to first test. In first figure, 8th order filter has less frequency
component suppression at cut off frequency. As compared to first figure 32nd order filter
has sharp cut off frequency response. This test conclude that 32nd filter order filter with
passband frequency 2kHz to 20kHz has good bandpass frequency response. These filter
parameters can be used for the stereo sound enhancement design. In comparison of figure
8th and 9th, figure 9th has better frequency response. Although this frequency band has
higher frequency range 20kHz at which stereo sound effect can be very minimum.
14
Figure 10 Frequency Responses for a Band Pass Filter with Passband from 400 Hz to
8kHz
15
Figure 10 represents frequency response for 8th and 32nd band pass filter with frequency
band 400 Hz to 8kHz. In this figure 32nd order filter has better frequency response than
the 8th order filter. In 8th order filter frequency response at cut off frequency there is good
suppression of frequency components. Although, 32nd order filter has better suppression
of frequency components compared to 8th order filter. Filter with this frequency band and
with filter order 32nd has very good frequency response compared to first two test. This
filter parameter can definitely used for left channel. The stereo sound algorithm with
these filter parameters can produce good amount stereo effect.
16
Figure 11 Frequency Responses for a Band Pass Filter with Passband from 4kHz to
10kHz
In figure 11 frequency response of 8th and 32nd order filter with passband from 4kHz to
10khz is shown. Above figure shows that filter with 32nd order has very good frequency
response compared to 8th order filter. The 32nd order filter suppressed frequency
components at lower cut off frequency as well as higher cut off frequency. Filter with this
frequency band can produce a good amount of stereo sound. This frequency band can
used for right channel. Results from above four tests conclude that 32nd order filter should
be used for optimum output. Filter’s frequency band more than 20kHz and less than
400Hz is not good to gain desire stereo sound effect. Thus, frequency band 400Hz to
8khz is used for left channel and 4kHz to 10kHz is used for right channel.
17
Figure 12 Spectrum Result of a Band Pass Filter with Filter order 8th and 32nd
Figure 12 represent spectrum result when a band pass filter is implemented in stereo
sound enhancement algorithm. For this simulation, left channel cut off frequency is
400Hz to 8kHz and for right channel is 4kHz to 8kHz. A 32nd order filter give good
frequency response and better quality of sound compared to lower order filter. There was
18
no sound component in the original sound file so it shows a small blue color block at the
end of every signal.
2.2.5 Moving Average Filter
The moving average filter is a simplest digital FIR filter. The filtered sample is average
of few previous or next samples of an input signal. The equation below represents
moving average filter equation. In this equation x[] represents the input signal y[]
represents output signal and M is called ‘tap’ implemented for that filter. If the filter
order is N=2, then bi = N+1 [5].
…….(2) [5]
Equation (2) is the representation of (second order/3-tap) moving average filter [5].
……(3)[5]
Figure 9 is a block diagram of 2nd order moving average filter. [5]
Figure 13 Block Diagram of a Moving Average Filter [5]
19
Moving average filter can be used, when there is a need of fixed shape frequency
response. For example, there are 5 points in rise shape of the original signal. All points
have same amount of noise. In this situation, we need to apply equal amount filter
treatment to all points. We can use either different coefficients or same coefficients for all
points to reduce the same amount of noise. If we use different coefficient values, it will
reduce noise according to coefficient value. Thus, we cannot get fixed shape frequency
response. However, moving average filter apply same coefficient value to all points so
we can get fixed shape frequency response.
20
Chapter 3
SOFTWARE DESIGN
This chapter will discuss about verilog implementation of stereo sound enhancement
algorithm. Initially, an algorithm is implemented with 2nd order FIR filter. Based on the
initial design architecture, algorithm is implemented for 32nd order FIR filter with lookup
table. In verilog, all design must consider signed arithmetic operation. Multiplication of
two signed binary numbers for verilog implementation is discussed in this chapter. In
addition, architecture, design flow and simulation results are explained in this chapter.
3.1 Design with FIR Band Pass Filter
3.1.1 Block Diagram
The block diagram of a stereo sound enhancement algorithm for verilog simulation is
shown below. I have omitted a delay block for verilog implementation.
21
Figure 14 Block Diagram for Verilog Simulation of Stereo Sound Enhancement
Algorithm
3.1.1.1 Sound file to digital samples & digital samples to sound file conversion
As verilog simulation needs data in binary format, I converted an input sound file in to
binary samples. I designed a Matlab code to convert sound (.wav) file in to 16-bit binary
samples in two separate channels (left channel & right channel). These 16-bit binary
samples are stored in two input text files (leftchannel.txt & rightchannel.txt). These
binary samples are passed through all stages of an algorithm. All processed samples are
collected from final stage and stored in to two output text files (final_lchannel.txt &
22
final_rightchannel.txt). The output stereo sound (.wav) file is generated from the output
text files using a Matlab code.
3.1.1.2 Test Bench
The test bench module is to test the design. All design modules named subtraction,
attenuation, filter, & final addition are instantiated inside the test bench. This test bench
generates clock and reset signals which will traverse across all design modules. Stereo
sound processing requires left channel and right channel processing in real time. One
sample from both channels has to be processed in same clock. Delayed sound in any
channel will create unexpected output. Therefore, testbench design initializes two
instances of each design modules except subtraction module. Each channel processing
requires one design instance. It is very important that all samples must pass through all
modules and processed serially. Stereo processing is multi stage operation; original
sample will be subtracted followed by attenuation. A band pass filter will filter attenuated
output and feed its output to the final addition module. Algorithm’s accuracy is
maintained by this strict process order. This multi stage design will require a pipeline
implementation for efficient processing. All modules input and output signals are
synchronized with handshaking signals for accurate transmission of samples. For
example, ‘ipflag’ handshaking signal will notify subtraction module that valid input
samples are available for processing. Handshaking signals of all modules are
synchronized with clock. All design modules are designed based on signed arithmetic.
23
3.1.1.3 Subtraction
Ipflag signal indicates valid left channel and right channel samples are available for the
subtraction module. This design considers signed binary subtraction of input samples.
Subtraction results will be stored in flip-flop synchronized with pipeline clock.
3.1.1.4 Attenuation
This module attenuates subtraction’s output by 20db. It divides all samples by 16 to
provide 20db attenuation. Division of binary numbers is performed by right shift
operation. In order to maintain signed values design must perform 4-bit right signed
arithmetic shift. For positive sample value, 4-bit right shift is performed on 15-bit data.
3.1.1.5 Filter
A second order band pass filter is designed to check the functionality of the stereo sound
enhancement algorithm. The digital FIR filter equation is implemented in this module
[Yn = K1*Xn + K2*X(n-1)]. Yn is a filtered sample. K1 and K2 are second order band
pass filter’s coefficients considered from Matlab simulation. Xn is the sample need to be
filtered and X(n-1) is the previous sample. Xn and X(n-1) are output from the attenuation
module. In this design coefficient are considered as 6-bit. Output of this module will be
23-bit.
24
3.1.1.6 Final Addition
In this module, 23-bit filtered sample is added with its 16-bit original sample. Output of
this module is stored in two text files. An output stereo sound file is generated from this
text files.
25
3.1.2 Signals used for Verilog Simulation
Signal
lorig
rorig
ip_flag
Sub_newlchannel
Description
16-bit signed left channel input samples available from
leftchennl.txt file.
16-bit signed right channel input samples available from
right channel.txt file.
1-bit handshaking signal indicates valid samples available
for subtraction module
16-bit left channel output from subtraction module
Sub_newrchannel 16-bit right channel output from subtraction module
att_ipvalid
att_out_lc
1-bit handshaking signal indicates valid subtracted samples
available for attenuation modules
16-bit left channel output from attenuation module
att_out_rc
16-bit right channel output from attenuation module
lc_iready
lc_filtered
1-bit handshaking signal indicates valid attenuated samples
available for filter module
16-bit left channel output from attenuation module. This
signal is X(n-1).
16-bit right channel output from attenuation module. This
signal is X(n-1).
23-bit right channel output from attenuation module
rc_filtered
23-bit right channel output from attenuation module
lc-oready
lc_final_data
1-bit handshaking signal indicates valid filtered samples
available for final addition modules
24-bit right channel output from attenuation module
rc_final_data
24-bit right channel output from attenuation module
lprev
rprev
Table 1 Signals for Verilog Simulation
26
3.1.3 Simulation Result
Figure 15 Verilog Simulation Result
Figure 13 shows verilog simulation waveform of stereo sound enhancement algorithm
with 2nd order band pass filter. In the diagram above, you can see the original 16-bit data
sample left data (FFEE) and right data (FFFA) read from separate text files. The ipflag is
the first handshaking signal, which starts the subtraction process in subtraction module.
The sub_newlchannel and sub_newrchannel are the final output of subtraction module.
The subtraction process is done within one clock cycle. The att_ipvalid signal generates
after one clock edge of ipflag, which acknowledges the sample is ready for attenuation.
The sample is attenuated in one clock cycle and then lc_iready signal acknowledges that
sample is ready for filter process. Once the sample is filtered after one clock cycle, then
27
signal lc_oread synchronizes the sample for final addition stage. After final addition, 24
bit data from lc_final_data and rc_final_data signals are stored in text files.
3.2 Design with Distributed Arithmetic Filter
In the above design, 2nd order band pass filter was used to verify efficiency of the stereo
sound enhancement algorithm. One way to improve the efficiency of algorithm is by
increasing the filter order. This design implementation is based on 32nd order filter.
The FIR Filter equation is written below [6].
N 1
Yn   K nX n  K 0X 0  K 1X 1    K N  1K N  1 …..(4)
n 0
In the equation 4, Yn is filtered data, K[n] is a coefficient and X[n] is the input data. N is
a filter order. In our design, X[n] is 16-bit data. So we can consider X[n] as per below
equation [6].
B 1
X n   X b n 2 b …..(5)
b 0
In equation 5, Xb is bth bit of binary data. Now replacing X[n] in the equation 4 with will
give this result [6].
N 1
B 1
n 0
b 0
Yn   K n X b n 2 b …..(6)
If we simplify equation 6 we will get this equation
Yn  K 0X B 1 0  K 1X B1 1   K N  1X B 1 N  1  2 B1
28
 K 0X B 2 0  K 1X B 2 1   K N  1X B 2 N  1  2 B 2
…….(7)

 K 0X 0 0  K 1X 0 1   K N  1X 0 N  1  2 0
We can write equation 7 in generalize form.
B 1
N 1
b 0
n 0
Yn   2 b  K n X b n …….(8)
As per the equation 7 and 8, multipliers and adder are required to implement digital FIR
filter equation. As filter order is increased number of multipliers will increase, thus which
requires more area on hardware. It creates significant amount of computational delay
when filter order is high. To overcome this issue we can use lookup table approach.
According to equation 8, we can calculate K[n] and Xb[n] manually and answer will be
stored in a table, which is known as lookup table. This design follows same architecture
of 2nd order filter. Three modules named as LUT, Top_LUT, and filter_with_LUT will
replace filter module of above design [6].
3.2.1 LUT
This module is combinational a logic which will generate 8-bit multiplication answer for
given two 4-bit inputs. Multiplication result of two 4-bit inputs yields 256(28) possible
answers. A multiplexer is implemented for all possible conditions. Multiplexer select
lines are two 4-bit inputs. According to the selection of input lines, the multiplexer output
will be latched.
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3.2.2 Top LUT
This module performs multiplication of 16-bit input sample and 4-bit coefficient. Four
instance of LUT design will require to perform multiplication task. According to figure
14, answer of the second nibble is left shifted by 4 bits, third nibble is left shifted by 8
bits, and fourth nibble answer is shifted by 12 bits. Shifted data (A1,A2,A3 &A4) will
summed together to produce final answer (Y1).
3.2.3 Multiplication of Signed Binary Numbers:
Signed arithmetic must consider following three conditions for multiplication operation.
1. Two Negative operands
2. Two positive operands
3. One positive and one negative operand
Illustrations in table 2 will discuss design flow for all above conditions and authenticate
LUT approach is suitable for both signed and unsigned multiplication.
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Input
(Xn)
16-bit
Sign
(+)
Coefficien
Description
t
(K)
4-bit
sign
(-)
Take complement of K
Result of
operation
4
Multiply complemented K with Xn
40
Perform XOR(^) operation among sign bits. If
answer is equal to 1 final answer sign is (-)
otherwise (+)
Take complement of the multiplication answer
(-)
Take complement of Xn
10
Multiply complemented Xn with K
40
Perform XOR(^) operation among sign bits. If
answer is equal to 1 final answer sign is (-)
otherwise (+)
Take complement of the multiplication answer
(-)
-40
(-)
Take complement of Xn
-10
Decimal
0n-4
/
Hex
0xC
Decimal
0n-10
/
Hex
0Xfff6
Take complement of K
-4
Perform XOR(^) operation among sign bits. If
answer is equal to 1 final answer sign is (-)
otherwise (+)
Multiplication answer is the final answer
(+)
(+)
Decimal
0n10
/
Hex
0x000A
(+)
Decimal
0n4
/
Hex
0x4
Multiply input with coefficient
40
Perform XOR(^) operation among sign bits. If
40
Decimal
0n10
/
Hex
0x000A
Decimal
0n-4
/
Hex
0xC
(-)
(+)
Decimal
0n-10
/
Hex
0Xfff6
Decimal
0n4
/
Hex
0x4
(-)
answer is equal to 1 final answer sign is (-)
otherwise (+)
Table 2 Signed Multiplication Illustrations
40
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3.2.4 Filter with LUT
According to equation 4, this design requires 32 samples to implement 32nd order filter. It
stores and considers 31 previous samples along with current sample. Each sample will
require 32 products. All of these products will sum together which will give one filtered
sample. FIFO approach is used to keep 31 previous samples. Current sample will always
stored on the FIFO header. These samples will be flushed after 32 clock cycles.
Attenuated samples will feed FIFO. Each FIFO member will be passed as a input to the
TOP_LUT along with it coefficient pair. Therefore, at every clock edge 32 products will
yield from 32 Top_LUT instances. An adder circuit will add all these 32 products and
exhibits 20-bit answer. Top_LUT and adder are combinational logic and thus filter
process can be done in same clock. The figure 15 presents architecture of a
filter_with_LUT design. According to diagram Xn is input sample from attenuation block
which is stored in FIFO. Top_LUT will create Yn =(Xn*K). The filtered output of Xn
will be Yn = Yn + Y(n-1) +….+ Y(n-31).
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Figure 16 Architecture of Filter with LUT
3.2.5 Perl Script
PERL is acronym for Practical Extraction and Report Language. In my LUT module, I
have to write 28 case statement. It is humanly very difficult to write 256 lines of a code
with different conditions. I designed a PERL script, which will generate 256 case
statements. As script, generated statements consider all the conditions and there was no
error in 256 case statements. These case statements will be stored in a text file. I can
insert those case statements in my verilog code from a text file.
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Chapter 4
HARDWARE DESIGN
This chapter will discuss implementation of stereo sound enhancement algorithm on
Altera DE-2 Board. It will describe block diagram and stereo_top_module for FPGA
implementation.
4.1 Block Diagram for FPGA Implementation:
Figure 17 Block Diagram for Hardware Implementation
According to figure 16 line in and line out ports are available on Altera DE2 board. A
input sound(.wav) file is supplied in to via line in port. Output sound file can listened via
line out port. A codec chip has ADC and DAC. After codec configuration, ADC will
convert input sound file in to 16-bit binary samples in two channels. These binary
samples are stored at SDRAM location 0h to 1f_ffffh. These samples are feed to the
stereo sound enhancement algorithm from SDRAM. Output of an algorithm is stored at
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SDRAM location 20_0000h to 3f_ffffh. These output samples are fetched to DAC, which
will convert binary samples to analog sound.
4.2 Stereo Top Module
Figure 18 Finite State Machine Diagram for Stereo Top Module
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Codec converts audio file in to 16-bit binary samples in two channels (left channel &
right channel). Left channels samples are stored at even address of SDRAM and right
channel samples are stored at odd address of SDRAM. Stereo_top_module reads samples
from SDRAM and processes the samples in five stages. Finite state machine of major
output signals and state descriptions of the stereo_top_module is explained below.
az_read_n
1-bit SDRAM control signal for read operation (When ‘0’ read)
az_write_n
1-bitSDRAM control signal for write operation (When ‘0’ write)
read_addr
21-bit read address index
write_addr
21-bit write address index
Table 3 Output Signals for Hardware Implementation
State S0: Initially, SDRAM address pointer is at 22'h3f_ffff location. In this state
read_addr is incremented by 1. The read index of SDRAM will be at ‘0’ now, where first
sample of left channel is stored.
State S1: Left Channel Read State: In this state signal az_read_n is 0, so left channel
will be read from 0th address of SDRAM. After completion of the state machine once,
every time consecutive left channel samples will be read from even address during this
state.
State S2: The read index of SDRAM will be at ‘0’. In this state read address of SRAM is
incremented by 1. The read index of SDRAM will be at 1st address, where first sample of
right channel is stored.
36
State S3: Left Channel Read State: In this state signal az_read_n is 0, so right channel
will be read from odd address of the SDRAM. After completion of the state machine
once, every time consecutive right channel samples will be read from odd address during
this state.
State S4: Wait state: The control signals az_read_n and az_write_n are inactive. Wait
state for data to get stable.
State S5: Subtraction: In this state, left channel and right channel samples are available,
thus subtraction process is executed.
State S6: Attenuation: In this state, result of subtraction is available so attenuation
process is executed.
State S7: Filter: In this state, result of attenuation stage is available, so data is filtered.
State S8: Final Addition: In this state, original samples are added to the filtered output
samples.
State S9: Hold State: Initially, SDRAM write index is at 22'h1f_ffff. In this state write
index is incremented by 1. So write index will be at address 22’h20_0000.
State S10: Left Channel Write State: In this state, the control signal az_write_n is 0, so
processed left channel sample is stored at 22’h20_0000 address. After completion of state
machine once, every time consecutive left channel samples are stored at even address
during this state.
State S11: Hold State: In this state, SDRAM write index is at 22'h20_0000. The
SDRAM write index is incremented by 1.
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State S12: Right Channel Write State: In this state, the control signal az_write_n is 0,
so the processed right channel sample is stored at 20_0001h address. After completion of
state machine once, every time consecutive right channel samples are stored at even
address during this state.
4.3 Simulation Result
Figure 19 Simulation Result for Hardware Implementation
The Figure 15 represents simulation waveforms for hardware implementation. In figure
15, left channel sample is read from SDRAM address 22’h000536 and right channel
sample is read from SDRAM address 22’h000537. In state 6, left channel and right c
channels samples are subtracted. After subtraction, samples are attenuated in state s7.
Once attenuation is finished samples are filtered in state8. In state 9, filtered left channel
and right channel sample are added with the original samples. Final left channel and right
channel sample is stored in SDRAM in state 10 and state 12.
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Chapter 5
COCLUSION AND FUTUREWORK
5.1 Conclusion
Stereo sound enhancement is an interesting and challenging field. I learned concepts of
stereo sound enhancement. I have successfully designed and simulated digital FIR filters
in Matlab and Verilog. I learned interfacing of SDRAM with FPGA and Codec. An
algorithm implementation and troubleshooting in verilog was very challenging.
Verification of digital samples at intermediate stages in Verilog was tough. I have
successfully implemented stereo sound enhancement algorithm on Altera FPGA board
with good sound quality.
5.2 Future work
Algorithm’s output can improve by implementing more than one filter. There are several
stereo sound enhancement techniques are discussed which can modify an algorithm for
optimum output. Onboard SDRAM can store 16-bit data. My design has 26-bit output. A
new design can implement which can store 26-bit data on SDRAM.
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BIBLIOGRAPHY
1. Thomas D. Rossing, ‘The Science of Sound’, Addison-Wesley Pub. Co., 1990
2. Maher Robert C., “Old and New Techniques for Artificial Stereophonic Image
Enhancement”, Proc. of the 101st Audio Engineering. Soc. Convention, Preprint
4371, November, 1996.
3. Maher Robert C., "Single-ended Spatial Enhancement using a Cross-coupled
Lattice Equalizer," Applications of Signal Processing to Audio and Acoustics,
1997. 1997 IEEE ASSP Workshop on , vol., no., pp.4 pp., 19-22, Oct 1997
4. “Distributed Arithmetic Filter” Xilinx Datasheet, version 9, April 2005
5. “Finite impulse response” retrieved from world wide web
http://en.wikipedia.org/wiki/Finite_impulse_respons
6. Wang Sen; Tang Bin; Zhu Jim, "Distributed Arithmetic for FIR Filter Design on
FPGA," Communications, Circuits and Systems, 2007. ICCCAS 2007.
International Conference on , vol., no., pp.620-623, 11-13 July 2007
7. "WM8731/WM8731L Portable Internet Audio CODEC with Headphone Driver
and Programmable Sample Rates", Wolfson Microelectronics Production
Datasheet, Rev 4.3, August 2006.