GLAST LAT Project
March 24, 2003
GLAST Large Area Telescope:
Gamma-ray Large
Area Space
Telescope
Tracker Subsystem
WBS 4.1.4
2A: Electronics Design and Status
Robert Johnson
Santa Cruz Institute for Particle Physics
University of California at Santa Cruz
Tracker Subsystem Manager
johnson@scipp.ucsc.edu
2A
Tracker Peer Review, WBS 4.1.4
1
GLAST LAT Project
March 24, 2003
TKR Electronics Requirements
•
•
2A
Details of the requirements are in released LAT documents:
– LAT-SS-17
Level-3 Performance requirements
– LAT-SS-134
Level-4 Mechanical & Thermal requirements
– LAT-SS-152
Level-4 Electronics requirements
The major challenges are
– Low power: <168 W of conditioned power
• Less than 0.29 W per MCM or 190 W/channel
• The flight design achieves 0.25 W per MCM!
– Low noise occupancy: (noise trigger rate <500 Hz)
• The trigger requires occupancy less than 5/100,000 ch/trigger
• Readout and onboard processing requires <1/10,000 ch/trigger
• The beam-test/balloon flight tracker achieved much better…
– Compact packaging: bring signals around the tray corner
– Manufacturing and QC: 884,736 channels, >98% functional
– Reliability: design, redundancy, testing
Tracker Peer Review, WBS 4.1.4
2
GLAST LAT Project
March 24, 2003
Some Detailed Requirements
• Internal charge injection for calibration and test, with pulseheight control and arbitrary selection of channels.
• Threshold uniformity: <15 mV rms across 64 channels.
• Threshold control per GTFE chip by an internal DAC.
• Dead time & Readout speed: less than 10% at 10 kHz cosmic rate.
• TOT: measure up to 4 MIPs.
• Non-destructive readback of configuration registers.
• Error checking: event alignment; command & data parity.
• Layer-OR jitter <250 ns for a charge deposit > 0.5 MIP.
• Reliability:
– Redundant readout paths.
– Redundant power paths.
– Protection against power shorts.
• Radiation hardness: 4 kRad TID; >37 MeV/mg/cm2 SEL thresh
• Passive cooling; temperature monitoring.
2A
Tracker Peer Review, WBS 4.1.4
3
GLAST LAT Project
March 24, 2003
Tracker Readout Architecture
Emphasis on compactness, minimum of wiring, and redundancy:
•
•
•
•
Serial, LVDS readout and control lines on flat flex-circuit cables.
Either of the two communications cables can fail without affecting the other.
Two readout and control paths for every 64-channel front-end chip.
Any single chip can fail without preventing the readout of any other.
24 64-channel amplifier-discriminator chips for each detector layer
• Trigger output = OR
of all 1536 channels
in a layer.
GTRC
Control signal flow
GTRC
Control signal flow
GTRC
• Read command
moves data into 1 of
2 GTRC buffers.
• Token moves data
from GTRCs to TEM.
GT FE
GT FE
GTRC
Nine detector layers are read out on each side of each tower.
Data flow to FPGA
on DAQ TEM board.
2A
GTRC
GTRC
2 readout
controller chips
for each layer
9-99
8509A22 Tracker Peer Review, WBS 4.1.4
Data flow to FPGA
on DAQ TEM board.
4
Control signal flow
• Upon trigger (6-fold
coincidence) data
are latched into a 4event-deep buffer in
each front-end chip.
Data flow
GLAST LAT Project
March 24, 2003
A2
A1
A0
NSDATA_IN
A3
TREQ_IN
LEFT
GTFE
RD_IN
NTREQ
GTRC
CTRLREG
TACKB
NSCMD
SCMD_OUT
A2
A1
A0
CLKB
RESETB
NSDATA_IN
A3
NTOKEN_OUT
NRESET
TOKEN
CLK
NSDATA
NTACK
TREQ_IN
LEFT
GTFE
RD_IN
NTREQ
GTRC
CTRLREG
TACKB
NSCMD
SCMD_OUT
CLK
NRESET
NSDATA
NTACK
TOKEN
• Block diagram of the ends of two
readout layers and their connections
to the TEM
– Clock, Command, Trigger, and
Reset are bussed to the GTRC
chips
– Token and Data daisy-chain up
and down the 9 layers
– Each layers sends its Layer-OR
directly to the TEM
– The TEM communicates only
with the GTRC chips, always by
serial LVDS.
– The GTRC communicates with
24 GTFE chips on the MCM.
NTOKEN_OUT
Tracker Readout Architecture
CLKB
RESETO
RESETB
TEM
2A
Tracker Peer Review, WBS 4.1.4
5
GLAST LAT Project
March 24, 2003
MCM Readout Module Configuration
•
•
•
•
•
•
•
Detector
8-layer polyimide PWB
Top edge thickened and machined to a 0.64
mm radius
Bias circuit
1-layer flex circuit (“pitch adapter”)
bonded over the radius
Tray Structure
Fully encapsulated wire bonds
Conformal coating
High-thermal
2 Omnetics nano connectors
conductivity
transfer
adhesive
Steel mounting screws + adhesive
GTRC, 1 of 2
Machined corner
radius with flex
circuit bonded
around the curve
Readout IC
TMCM,
attached by
screws
GTFE, 1 of 24
359.0mm
24.58mm
18.0mm
Connector, 1 of 2
Grounding Screws
3 Total
2A
Mounting Screws, 1 of 8
Tracker Peer Review, WBS 4.1.4
6
GLAST LAT Project
March 24, 2003
MCM PWB Layout Concept
• Low-noise environment for
the amplifier chips
• 8 layers are used for good
analog/digital separation plus
low-impedance ground and
power planes.
• Analog and digital traces are
well separated and never wrap
around each other.
• Power planes and split
analog/digital GND planes
• Complete planes are also used
for the SSD bias and
AVDD2low impedance path
to the decoupling caps for the
SSD signal return.
1.
2.
3.
4.
5.
6.
7.
8.
Digital traces; SMT parts; ASICs
Digital busses
Split digital/analog power
Split digital/analog ground
Analog ground
Analog traces from ASICs to the
SMT parts
AVDD2 (analog 1.5V)
Detector bias
Stackup and arrangement
of conductors in the PWB
R, C, etc.
IC
Digital Traces
Digital Pwr/Gnd
Analog Pwr
Analog Gnd
Analog Traces and Planes
2A
Tracker Peer Review, WBS 4.1.4
7
GLAST LAT Project
March 24, 2003
Pitch Adapter
• 1-layer Kapton flex circuit
• Ni + Au plating for wire bonding
• Precision tooling holes (not
shown)
• Circuit & traces are trimmed to
length after bonding to the PWB
(see Presentation 6E)
Bias HV
ASIC Side
SSD Side
(228 m pitch)
“ground”
2A
Tracker Peer Review, WBS 4.1.4
8
GLAST LAT Project
March 24, 2003
F.E. Readout Chip (GTFE)
•
•
•
Schematics-based design, using standard cells for logic.
Standard-cell I/O pad ESD protection.
Manual layout of the analog channel, I/O cells, memory, global routing.
•
•
Automated place-and-route of the logic blocks.
Design verification: Spice and gate level simulations; DRC; LVS; simulation
of the final extracted netlist in Nanosim.
Trigger and Data mask registers
Standard-cell auto route
Control logic, command decoders
Standard-cell auto route
Calibration mask and capacitors
4-deep event memory (addressed by TEM)
Custom layout
2 custom DACs
Cap
64 amplifier-discriminator channels.
2A
I/O pads and protection structures
Tracker Peer Review, WBS 4.1.4
9
GLAST LAT Project
March 24, 2003
GTFE Block Diagram
64
• 64 amplifier-discriminator
channels
• 7-bit threshold DAC
• Calibration mask register
• 7-bit calibration DAC
• Trigger mask register and trigger
layer-OR
• Data mask register
• 4-deep event buffer
• Pair of redundant command
decoders
• Pair of redundant trigger
receivers
• Leftward readout register
• Rightward readout register
• LVDS I/O cells
ANALOG INPUTS
FROM SILICON STRIPS
CALIB. MASK & READOUT REGISTER
CALIBRATE STROBE
PREAMPLIFIERS
CALIB
DAC
SHAPERS
THRESH
DAC
DISCRIMINATORS
M
U
X
64
7
7
CTRLREG
(TRI STATE)
TRIGGER MASK & READOUT REGISTER
S
ADDRESSED
SEL
DAC REGISTER
EVENT_TRIG
FAST-OR
64
TRIGGER FROM PREVIOUS GTFE
1
64
DATA MASK & READOUT REGISTER
WRITE STROBE
L1T
READ CMD
WRITE
CONTROL
2
EVENT_DATA
64
64
MODE
REG
EVENT_OR 2
1
LEFT/RIGHT
D
C
Q
D
C
Q
DEAF
MODE
W_ADDR
67 X 4
EVENT BUFFER
2
R_ADDR
DATA HIT
READ
CONTROL
64
LOAD
DATA READ SHIFT REGISTER
DATA
FROM
PREVIOUS
GTFE
A
DATA OUT
OUT
B S
DATA HIT
LEFT
COMMAND SELECT
CMDR
CMDL
CLKL
LOAD/READ TRIGGER MASK
CALIBRATE STROBE
LOAD/READ DAC REGISTER
LOAD/READ MODE REGISTER
LOAD/READ CALIBRATE MASK
LEFT COMMAND
DECODER
RIGHT COMMAND
DECODER
CLKR
RESET
2A
Tracker Peer Review, WBS 4.1.4
10
GLAST LAT Project
March 24, 2003
Readout Controller Chip (GTRC)
• All digital
• Tanner standard-cells, except for
• LVDS I/O cells.
• SEU hardened configuration
register.
• RAM (64 hits, 2 buffers)
• Design in VHDL; synthesis, auto place
and route.
• Verification: VHDL sim; DRC; LVS;
Nanosim of extracted netlist.
NTOKEN_OUT
NSDATA_IN
I/O
EVENT
MEMORY
0
EVENT
READOUT
CONTROL
EVENT
MEMORY
1
GTFE
READOUT
CONTROL
RD_IN
TOT
NTREQ
FASTOR
I/O
TREQ_IN
I/O
NTACK
TRIGGER
TACKB
REGISTER
READBACK
CONTROL
CTRLREG
NSCMD
SCMDOUT
CLK
CLKB
CMD
DECODER
NRESET
CONTROL
REGISTER
RESETB
I/O
NSDATA
TOKEN
2A
Tracker Peer Review, WBS 4.1.4
11
GLAST LAT Project
March 24, 2003
Readout Cables
• Standard-technology 4-layer Kapton flex
circuits
• 8 unique layouts (with identical
schematics)
• Require 36-inch panels for manufacture
• Power traces/planes, LVDS signals, and
thermistor loops
• Procurement specification: LAT-PS-01132
Thermistor
Location
Solder pads
for nanoconnector
4 Termination
resistors
Thru-holes for Micro-D connector
EM cable manufactured by Parlex
2A
Tracker Peer Review, WBS 4.1.4
12
GLAST LAT Project
March 24, 2003
Electronics Cooling
• Low IC power density (20 MHz clock):
– GTFE chip: 7.8 mW for 0.33 cm2  0.024 W/ cm2
– GTRC chip: 32 mW for 0.12 cm2  0.26 W/cm2
• Total MCM power of 0.25 W is spread by the PWB over about 100
cm2 along the tray edge  2.4 mW/cm2. The 8-layer board has
several full copper planes to spread the heat.
• A 5-mil 3M high-thermal-conductivity transfer adhesive lies between
the MCM and carbon-carbon tray closeout.
• The carbon-carbon carries the heat to the sidewall through a 20 cm
long boss and 10 fasteners into the tower sidewalls.
• The 1.5 mm thick K13D/YS90 sidewalls carry the heat to the bottom
of the tower.
• Copper straps carry heat from the sidewalls into the Grid.
• SSDs stay below 30°C operational. The ICs will be only a few
degrees warmer.
2A
Tracker Peer Review, WBS 4.1.4
13
GLAST LAT Project
March 24, 2003
Example EM Tray
• The bias circuit is a 2-layer Kapton flex circuit.
• Top layer: 16 wire-bond pads (Ni-Au plating) + HV bias traces
and bulls-eye pads for conductive adhesive.
• Bottom layer: hatched “ground” plane.
Encapsulated
ASICs
Bias Circuit
Handle for
assembly fixtures
MCM
Thermal Boss
Connector Saver
2A
Tracker Peer Review, WBS 4.1.4
14
GLAST LAT Project
March 24, 2003
Grounding & Shielding
LAT RF SHIELD
SPACECRAFT
DIST-GLT ASSY.
28 VOLTS
MIL-1553
POWER ASSY.
SIU
FILTER
BOX
ENCLOSURE
SSR
FILTER
FILTER
T
HSKP
GRID COMMON
EPU
FILTER
FILTER
FILTER
SPACECRAFT
GROUND
SUBSYSTEM
COMMON
LAT
Overview
TEM ASSY.
TKR/CAL_FE
FILTER
FILTER
ACD ASSY
FILTER
BONDING
STRAP
( ONE PLACE )
2A
GRID
OUTER SHIELD
FILTER
ACD_FE
CABLE
Tracker Peer Review, WBS 4.1.4
15
GLAST LAT Project
March 24, 2003
Tracker Grounding & Shielding
Aluminum covering
on all 6 sides
Conductive
tape on joints
Zillion screws
tie the
sidewalls into
the trays
Cu thermal straps provide the
conduction path to the Grid
2A
8 cables ground the 19 trays
& electronics to the TEM
Tracker Peer Review, WBS 4.1.4
16
GLAST LAT Project
March 24, 2003
Tray Grounding & Shielding
• The bias circuit includes a hatched “gnd” plane (actually 1.5 V) that
corresponds to the amplifier voltage reference. It separates the
SSDs from the structure and couples closely to the 120 V bias on the
backs of the SSDs.
• The MCMs have separate analog and digital ground planes with
separate returns to the TEM, but they are coupled together on each
MCM by an SMT jumper.
• 3 long screws tie each MCM ground into the aluminum core
Multi-Chip Module (MCM)
C.C.F. Close-Out
Aluminum HexCell
C.F. Laminate
Bias Plane
Silicon Strip Detectors
Mounting Screws
Wire bonds & Right Angle Interconnect
2A
Tracker Peer Review, WBS 4.1.4
17
GLAST LAT Project
March 24, 2003
Tray Grounding & Shielding
• The 1.5 V analog supply (AVDDA) feeds the source of the input FET
and is thus the small-signal reference of the detector system.
• It couples to the SSD bias via HV capacitors on the MCM and
through the capacitance of the bias circuit.
• This provides the small-signal current return path of the detector
system.
• All voltage supplies occupy planes on the MCM and are coupled to
ground via numerous ceramic and tantalum capacitors on the MCM.
2A
Tracker Peer Review, WBS 4.1.4
18
GLAST LAT Project
March 24, 2003
EMI/EMC
• The Tracker will be well shielded:
– All transmitted signals are LVDS and digital (very low radiation and
excellent noise rejection). In addition, power and ground reference
planes are always directly under or over the signal pairs.
– Aluminum foil (over carbon-fiber) covering all 6 tower module sides.
– Conductive tape around the corners to connect the sides.
• SSD strips are the sensitive nodes, but
– They are well shielded from any radiation.
– Only a very local reference is needed (the amplifiers are millimeters from
the strips with well identified, short current return paths).
– The local grounding around the SSDs is critical for noise performance.
• EM emissions will be tested from the qual unit, but we expect it to
satisfy requirements easily (433-RQMT-0005). Preliminary
measurements on the BTEM showed no measurable emission, even
with the aluminum shielding walls removed.
2A
Tracker Peer Review, WBS 4.1.4
19
GLAST LAT Project
March 24, 2003
EMI/EMC
• Primary document 433-RQMT-005
• Radiated Emissions (RE101, RE102)
– 20% of total emissions are allocated to subsystems outside LAT
RF shield
• ACD, Tracker, Heaters
– 60% of total emissions are allocated to subsystems inside LAT
shield
• Radiated Susceptibility (RS101,RS103)
– All subsystems must meet Section 5.3 of 433-RQMT-005
• Conducted Emissions (CE101, CECM)
– Only the T&DF subsystem is affected and must meet
requirements
• Conducted Susceptibility (CS101, CS116)
– Only the T&DF subsystem is affected and must meet
requirements
2A
Tracker Peer Review, WBS 4.1.4
20
GLAST LAT Project
March 24, 2003
BTEM EMI Test
No measurable EMI detected, clock on or
off, even with the tower shield removed.
Spectrum
Analyzer
BTEM with
Shield removed
Electric field
antenna
Magnetic field
antenna
2A
Tracker Peer Review, WBS 4.1.4
21
GLAST LAT Project
March 24, 2003
Prototype Electronics Performance
• See LAT-TD-1090. Reviewed at TKR ASIC review Dec 6, 2002.
• Analog tests with “mini-MCM” plus full-length ladder (384 channels)
– Gain and noise from charge-inject/threshold scans
– Noise measurements from trigger-rate threshold scans
– Noise occupancy from random triggers
– Noise injection from digital readout
– Gain versus number of channels pulsed
– Pulse shapes and Time-Over-Threshold
• Functional tests with full MCMs (no SSDs attached)
– All digital functionality
– Power consumption
See Presentation 3B for
– Voltage and timing margins
more recent results on
– DAC calibrations
Engineering-Model trays.
– Thermal cycling
• Radiation Testing
2A
Tracker Peer Review, WBS 4.1.4
22
GLAST LAT Project
March 24, 2003
Threshold Dispersion
The RMS
dispersion, with
or without SSDs
connected, is
below 8 mV,
better than the
requirements.
100
80
Hit Efficiency
The dispersion is
independent of
the number of
channels
simultaneously
pulsed.
G Chip, with 32 Channels Pulsed Simultaneously
60
No load on inputs.
40
20
0
0
10
20
30
40
50
60
Threshold DAC Setting
2A
Tracker Peer Review, WBS 4.1.4
23
GLAST LAT Project
March 24, 2003
Trigger Rates
Trigger Rate per Chip (64 Channels)
106
Rate (Hz)
10
5
104
1.3 fC=1/4 MIP
103
102
Three ladders
G0
connected
G1 to
mini-MCMs
G2
were tested.
F3
These are the
F21
results for
F22
Ladder-0
Long TOT pulses; look
like cosmic rays
101
100
0
1
2
3
Threshold/Gain (fC)
2A
Tracker Peer Review, WBS 4.1.4
24
GLAST LAT Project
March 24, 2003
Noise Occupancy
Our first direct measurement of noise occupancy with the new electronics system.
Ladder 0, 80V bias, 1.3 fC
threshold, 1.5 million
triggers.
Noise Hits
6
4
2
0
0
100
200
300
Channel Number
2A
Tracker Peer Review, WBS 4.1.4
25
GLAST LAT Project
March 24, 2003
MCM Power Consumption
AVDDA
1.5 V
AVDDB
2.5 V
No Clock
77.4 mW
39.3 mW
20 MHz
77.4 mW
39.3 mW
DVDD
2.5 V
address 5
82.8 mW
134.3 mW
MCM Power (W)
2A
DVDD
2.5 V
address 0
Allocation
MCM Address > 0
0.251
MCM Address = 0
0.255
Tower
9.05
10.5 W
16 Towers
145
168 W
Tracker Peer Review, WBS 4.1.4
138.5 mW
26
GLAST LAT Project
March 24, 2003
ASIC Review Action Items
•
•
•
•
•
•
•
•
•
•
2A
Test full trays
Test noise 1 channel at a time
Noise occupancy vs threshold (deviation from gaussian noise)
Noise versus threshold
Efficiency vs threshold
Test FIB ICs with ladder
Test at high rates
Wafer probing system (see Presentation 5D)
Approved parts (see Presentation 5B)
Procurements (see Presentation 5A)
Tracker Peer Review, WBS 4.1.4
27
GLAST LAT Project
March 24, 2003
Actions from ASIC Review
• Measurements with complete trays (EM mini-tower)
– Four trays, with a total of 6 SSD planes have been tested.
– Initially there were noise problems that were solved by fixing the
grounding
• Grounding of the Al core via long screws in the MCM (always has
been a Level-IV specification).
• Grounding of the metallic tray service/storage box.
– Now the noise and gain are consistent with what has been seen on the
mini-MCMs connected to single ladders.
Aluminum handle (part of
service box), also grounded to
the core.
Long grounding screw in platedthrough hole. (Conformal coat
had to be scraped off.)
2A
Tracker Peer Review, WBS 4.1.4
28
GLAST LAT Project
March 24, 2003
Actions from the ASIC Review
• Example Layer-OR counting rate from 1 GTFE chip on a mini-tower
tray (OR of 64 channels).
Threshold scan FE 21
100000
10000
Counting rate (Hz)
1000
100
10
1
0,1
0,01
0
10
20
30
40
50
60
Threshold DAC
2A
Tracker Peer Review, WBS 4.1.4
29
GLAST LAT Project
March 24, 2003
Actions from ASIC Review
• Make threshold scans on G and F version chips pulsing only one
channel per chip at a time.
– Pulsing only one channel, the noise sigma was about the same
for G and F versions.
– This confirmed the suspicion that the higher noise sigma seen in
the F chip was related to crosstalk effects when multiple channels
were pulsed.
• Measure noise occupancy versus threshold and determine at which
threshold the occupancy deviates from gaussian noise.
– The resulting plots give noise sigmas consistent with
expectations.
– Deviations from the exponential curve at low threshold are due to
saturation from the time-over-threshold. We cannot see any
evidence of spurious pickup.
2A
Tracker Peer Review, WBS 4.1.4
30
GLAST LAT Project
March 24, 2003
Example Noise Rate Plot
OR of 64 Channels. With a gain of 75 mV/fC the fitted ENC is 1710 electrons.
GTFE3
18
16
14
ln(rate)
12
10
ln(rate)
8
Fit
6
4
2
0
-2 0
1
2
3
4
5
Thr**2 (fC**2)
2A
Tracker Peer Review, WBS 4.1.4
31
GLAST LAT Project
March 24, 2003
Single-Channel Noise Rates
• Only one channel at a time is enabled in the trigger mask, and the
Layer-OR rate is measured by a frequency counter at each threshold
setting.
• Two channels from the first chip are shown below.
• Fitted noise ENC: 1580 electrons and 1542 electrons respectively.
• No evidence of excess noise down to as low as 0.5 fC threshold.
Channel 31, Chip 0, Ladder 11
14
14
12
12
10
10
8
8
ln(rate)
ln(rate)
Channel 0, Chip 0, Ladder 11
6
4
2
4
2
0
-2
6
0
0
0.5
1
1.5
2
2.5
3
-2
0
0.5
Thr**2 (fC**2)
2A
1
1.5
2
2.5
Thr**2 (fC**2)
Tracker Peer Review, WBS 4.1.4
32
3
GLAST LAT Project
March 24, 2003
Actions from ASIC Review
Averaged Chip Noise vs Threshold Setting
2000
1500
Chip
Chip
Chip
Chip
1000
0
1
2
3
Error bars shown for Chip 0 are the
RMS spreads of the 64 channels
Chips 0, 2, and 3 are FIB’ed ICs
500
10
14
18
22
26
30
Threshold
2A
Tracker Peer Review, WBS 4.1.4
33
GLAST LAT Project
March 24, 2003
Actions from ASIC Review
• Study the how the efficiency varies with threshold.
– This was studied by the Bari group by Monte Carlo.
– See LAT-TD-1128. The simulation is for single muons.
2A
Threshold (MIP)
0 degrees
40 degrees
0.25
99.9
99.9
0.30
98.5
96.0
0.35
98.2
94.0
0.40
97.7
92.4
0.45
96.3
90.8
0.50
92.0
89.5
Tracker Peer Review, WBS 4.1.4
34
GLAST LAT Project
March 24, 2003
Actions from the ASIC Review
• Test the system at high rates
– This was done with a ladder, mini-MCM, and SLAC EGSE.
– Self trigger, using the Layer-OR, and lower the thresholds on a
subset of channels to achieve high trigger rates.
– No new problems were found.
– Below is a  source profile at low and high trigger rates.
4
3.5
Source(100 Hz) + noise (1 kHz)
Source (100 Hz)
Counting rate (Hz)
3
2.5
2
1.5
1
0.5
0
64
128
Strip number
2A
Tracker Peer Review, WBS 4.1.4
35
GLAST LAT Project
March 24, 2003
Prelim. Results on the Flight ASICs
• GTFE V-G3: 1 wafer was diced without prior probe testing:
– 14 ICs were mounted on mini-MCMs and 4 on a full-size MCM (also
populated with 20 older-version GTFE chips).
– All 18 randomly selected chips worked 100%.
– No evidence of the comparator instability that plagued the previous version
(all 18 chips show identical behavior, with stable Layer-OR outputs even at
the minimum threshold setting).
– The timing margin on the register read-back was corrected:
• All 4 chips on the full-size MCM load and read correctly at VDD=2.5V up to
28 MHz (old versions fail at 23 MHz).
• All 4 chips also load and read correctly at VDD=2.25V and 20 MHz.
– One mini-MCM was connected to a full-size ladder. Noise performance is
similar to the previous versions.
• GTRC V-6: 1 wafer was diced without prior probe testing
– Tested with probe card & test suite, as well as on mini-MCM and full MCM
– All functionality is correct.
– Timing margin improved: data readout works up to 30 MHz at 2.5V
2A
Tracker Peer Review, WBS 4.1.4
36
GLAST LAT Project
March 24, 2003
GTFE Version-G3 Noise Fits
• Example noise rate vs. threshold for a
channel connected to an SSD strip.
Channel 12
14
12
• Distribution of fitted noise values, for a
fitted average gain of 74 mV/fC.
1638 electrons
8
6
4
GTFE G3
2
0
0
0.5
1
1.5
25
2.5
2
Thr**2 (fC**2)
3
20
Avg.=1634 e
15
10
5
50
19
00
18
50
16
00
15
50
13
00
12
0
50
10
90
0
75
0
60
0
45
0
30
15
0
0
0
-2
Frequency
ln(rate)
10
Noise
2A
Tracker Peer Review, WBS 4.1.4
37