GLAST LAT Project
Gamma-ray Large
Area Space
Telescope
DOE/NASA Peer Critical Design Review, March 19-20, 2003
GLAST Large Area Telescope:
Electronics, Data Acquisition &
Instrument Flight Software
Peer Critical Design Review
March 19-20, 2003
Gunther Haller
Stanford Linear Accelerator Center
Manager, Electronics, DAQ & FSW
LAT Chief Electronics Engineer
haller@slac.stanford.edu
(650) 926-4257
G. Haller
4.1.7 Elex Overview-Management V6
1
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
CDR Agenda
Day 1 - March 19 (all times PST)
G. Haller
Section 1: Electronics, DAQ, FSW Overview
8:00 – 8:40
Section 2: Management
8:40 – 9:20
Section 3: System Engineering
9:20 – 10:30
BREAK
10:30 – 10:45
Section 4: Electronics
10:45 – 12:00
LUNCH
12:00 – 13:00
Section 5: Instrument Software Overview
13:00 – 13:30
Section 6: Instrument Software I
13:30 – 14:45
BREAK
14:45 – 15:00
Section 7: Instrument Software II
15:00 – 15:30
Section 8: Instrument Software III
15:30 – 16:15
Discussion
16:15 – 17:00
4.1.7 Elex Overview-Management V6
2
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
CDR Agenda (Con’t)
Day 2 - March 20
G. Haller
Section 9: Mechanical & Thermal
8:00 – 9:00
Section 10: Power - EMI
9:00 – 9:30
Section 11: Monitoring & Thermal Control
9:30 – 10:00
BREAK
10:00 – 10:10
Section 12: EEE Parts
10:10 – 10:40
Section 13: Manufacturing
10:40 – 11:10
Section 14: Summary
11:10 – 11:20
Discussion/Closeout
11:20 – 12:00
Adjourn
12:00
4.1.7 Elex Overview-Management V6
3
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Review Board Team
• Hartmut Sadrozinski/UCSC
• Al Vernacchio/GSFC
• Fred Huegel/GSFC
• John Fox/SLAC
• Steve Smith/SLAC
•
•
•
•
•
Bob Jackobsen/LBL
Rick Schnurr/GSFC
Lowell Klaisner/SLAC
Steve Scott/GSFC
Ron Zellar/GSFC
G. Haller
Chairman
Co-Chairman - GLAST
Deputy Project Manager
Electrical Engineering
Electrical Engineering Applied Physics
Electrical Engineering –
System Engineering
Software
Software
LAT Chief Engineer
Systems Engineering
Software
4.1.7 Elex Overview-Management V6
4
GLAST LAT Project
Gamma-ray Large
Area Space
Telescope
DOE/NASA Peer Critical Design Review, March 19-20, 2003
GLAST Large Area Telescope:
Electronics, Data Acquisition &
Flight Software
Overview
Gunther Haller
Stanford Linear Accelerator Center
Manager, Electronics, DAQ & FSW
LAT Chief Electronics Engineer
haller@slac.stanford.edu
(650) 926-4257
G. Haller
4.1.7 Elex Overview-Management V6
5
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Overview Outline
•
•
•
•
•
•
•
•
Overview of LAT and Electronics
Level III Requirements Summary
Meeting Key Requirements
Flowdown – Requirements to Design
Design Evolution
Optimization
Technical Heritage
Status of July DPDR Recommendation Items
G. Haller
4.1.7 Elex Overview-Management V6
6
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Overview of LAT
• Precision Si-strip Tracker (TKR)
18 XY tracking planes. Single-sided
silicon strip detectors (228 mm pitch)
Measure the photon direction;
gamma ID, ~880,000 channels.
• Hodoscopic CsI Calorimeter(CAL)
Array of 1536 CsI(Tl) crystals in 8
layers. Measure the photon energy;
image the shower.
• Segmented Anticoincidence Detector
(ACD) 89 plastic scintillator tiles.
Reject background of charged
cosmic rays; segmentation removes
self-veto effects at high energy.
• Electronics System Includes flexible,
robust hardware trigger and software
filters.

ACD
[surrounds
4x4 array of
TKR towers]
e+
Tracker
e–
Calorimeter
DAQ Electronics
Systems work together to identify and measure the flux of cosmic gamma
rays with energy 20 MeV - >300 GeV.
G. Haller
4.1.7 Elex Overview-Management V6
7
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
LAT Electronics
ACD
TKR Front-End Electronics (MCM)
ACD Front-End Electronics (FREE)
CAL Front-End Electronics (AFEE)
TKR
16 Tower Electronics Modules
– DAQ electronics module (DAQ-EM)
– Power-supplies for tower electronics
CAL
Global-Trigger/ACD-EM/Signal-Distribution Unit*
Spacecraft Interface
Unit
– Spacecraft
Interface Board
(SIB): Spacecraft
interface, control
& data
– LAT control CPU
– LAT
Communication
Board (LCB): LAT
command and
data interface
3 Event-Processor Units (2+1 spare)
– Event processing CPU
– LAT Communication Board
– SIB
EPU-1
EPU-2
Pw r Dist. Box
spare
spare
GASU
spare
spare
spare
SIU-P
SIU-R
EPU-3
Power-Distribution Unit (PDU)*
– Spacecraft interface,
power
– LAT power distribution
– LAT health monitoring
* Primary & Secondary Units shown in one chassis
G. Haller
4.1.7 Elex Overview-Management V6
8
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Specification Tree
Mission
Science
Requirements
Document
LAT IOC/MOC/
SSC Interface
Control
Documents
Mission System
Specification
Interface
Rqmts
Ground System Rqmts
Science
Rqmts
LAT-SC Interface
Requirements
Document
Mission
Rqmts
Interface
Rqmts
LAT
LAT Performance
Specification
LAT-SS-00010
LAT
Environmental
Specification
LAT-SS-00778
LAT IOC
Performance
Specification
LAT-SS-00015
LAT-SC Interface
Control
Documents
LAT
Subsystem
Mechanical
Subsystem
Specification
LAT-SS-00115
Trigger & Dataflow
Subsystem
Specification
LAT-SS-00019
TKR Subsystem
Specification
LAT-SS-00017
ACD Subsystem
Specification
LAT-SS-00016
G. Haller
Radiator Design
Specification
LAT-SS-00394
TCS Performance
Specification
LAT-SS-00715
X-LAT Plate
Design
Specification
LAT-SS-01240
Grid Box Design
Specification
LAT-SS-00775
ACD Design
Specification
LAT-SS-00352
LAT Trigger
Specification
LAT-SS-00284
Power
Subsystem
Specification
LAT-SS-00136
SAS
Subsystem
Specification
LAT-SS-00020
CAL Subsystem
Specification
LAT-SS-00018
LAT Flight SW
Specification
LAT-SS-00399
LAT TKR Design
Specification
LAT-SS-00134
LAT Dataflow
Specification
LAT-SS-00285
LAT Readout
Electronic
Specification
LAT-SS-00152
Tower Power
Supplies
Specification
LAT-SS-01537
LOF
Subsystem
Specification
LAT-SS-00021
SAS Design
Specification
LAT-SS-00505
CAL Design
Specification
LAT-SS-00210
LAT Operations
Facility
Specification
LAT-SS-01783
Design
Specification
4.1.7 Elex Overview-Management V6
9
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Level III Key Requirements Summary
Electronics
Ref: LAT-SS-00019
Adjust Input timing resolution
TACK latency
Timing Jitter
Dead-time contribution
Event Deadtime Report
<100 ns
Trigger acknowledge output
< 1.3 ms
< +/- 50 ns
< 5 ms
Acknowledge blocking
Dead time cause
< 500 ns
Event Data Contribution
Diagnostics Mode
Test
Test/Demonstration
Test
Test
Test
Test/Demonstration
Test/Demonstration
Test
Test/Demonstration
Test/Demonstration
50 ns
Meet Requirement
< 1.3 usec
< 50ns
< 200 nsec
Meet Requirement
Meet Requirement
< 500 ns
Meet Requirement
Meet Requirement
Verify commanding interface
GRB response
Test/Demonstration
Test/Demonstration
Meet Requirement
Meet Requirement
Readout and overwrite protection
Filtering functions
Pointing & coordinate system
Dead-time for average orbit condition < 5%
Test/Demonstration
Test/Demonstration
Test/Demonstration
Test/Demonstration
Meet Requirement
Meet Requirement
Meet Requirement
< 5% for T&DF
Monitoring & calibration
< 0.25 m3
< 188 kg
Test/Demonstration
Inspection
Inspection
Meet Requirement
< 0.25 m3
< 188 kg
< 142 W (dayly average)
< 330 W (peak, average over 1 sec)
Test
Test
< 142 W (daily average)
< 330 W (average over 1 sec)
Control System
Event Data
Volume
Mass
Power
G. Haller
4.1.7 Elex Overview-Management V6
10
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Level III Key Requirements Summary (2)
Power System
Ref: LAT-SS-00136
Parameter
Input Power
Telemetry
Output Power
G. Haller
Requirement
28 VDC +6/- 6V
< 1000 Watts peak
< 650 Watts (daily average)
Impedance
Primary/Redundant input power source
Switching
8 primary power circuits of 14 A
Control
Telemetry monitoring internal voltage,
current, and temperature
Supply power to Tower Electronics
Supply power to EPU
Supply power to SIU
Supply power to GASU
Verification
Expected Performance
Test
Test/Analysis
Test/Analysis
Analysis
Analysis
Test
Analysis
Test
Test
22 V to 37 V DC
< 750 W
< 650 W
tbd
Meet Requirement
Meet Requirement
2 to 5 circuits
Meet Requirement
Meet Requirement
Test
Test
Test
Test
Meet
Meet
Meet
Meet
Requirement
Requirement
Requirement
Requirement
4.1.7 Elex Overview-Management V6
11
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Flowdown – Requirements to Design
Parameter
Requirement
Constraint
Characteristics Needed
Design
Trigger
Adjust Input timing
resolution
TACK latency
Timing Jitter
Dead-time contribution
Event Deadtime Report
<100 ns
Power
< 1.3 us
< +/- 50 ns
< 5 us
< 500 ns
Mass
Volume
Complexity
Reliability
Readout and overwrite protection
Power
Efficient Event Assembly
Filtering functions
Dead-time for average orbit
condition < 5%
Buffering for burst up to 20,000
photon events
Mass
Volume
Complexity of hardware versus
software
Reliability
Hardware/Firmware system
Central Trigger
Decision Block
(Global Trigger,
located in GAS
Unit)
Dataflow
Event buffering in Front-end
electronics, TEM, GASU
Central Event Builder
Hardware event assembly
(Hardware, located
in GAS Unit)
Processor for filtering
PowerPC Processor Farm
Error Recovery
G. Haller
4.1.7 Elex Overview-Management V6
12
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Evolution of DAQ Design
Proposal Design:
•
•
•
•
•
No global trigger, ability to reduce hardware trigger rate from tracker marginal
Data router to move partial event fragments into central processor
Event building in software
16 processors, one on each tower to process data
Communication to TKR/CAL/ACD systems very unique
Current Design:
•
•
•
•
•
G. Haller
Global trigger, ability to reduce hardware trigger rate from tracker
Event building in hardware
Data switch to move complete event fragments from hardware event builder to
processor
2 processors for event processing
Communication to TKR/CAL/ACD systems unified
4.1.7 Elex Overview-Management V6
13
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Optimization – Summary
• Serial LVDS (Low-Voltage-Differential-Swing) protocol with
Data, Clock, Reset, Return-Data to each front-end system and
between DAQ modules (see LAT-TD-00606)
• Buffering of event data fragments at each module stage to
meet dead-time requirements
– TKR front-end -> TEM -> Event-Builder -> LAT
Communication Board -> CPU -> Spacecraft Solid-State
Recorder
• Flow-control between buffer stages to meet non-overwriting
and data consistency requirements
• Utilization of ASIC’s to meet volume, power, and cost
constraints
G. Haller
4.1.7 Elex Overview-Management V6
14
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Heritage
• Similar data-acquisition system was used on balloon flight
(TEM, one event-processing CPU, one spacecraft-interfaceequivalent control CPU)
• Electronics components: mostly components with flightheritage (FPGA’s, LVDS converters, memories)
• ASIC technology same as for tracker, calorimeter, ACD
systems
• Trigger, dataflow, event assembly, and event filter processing
very similar to past high-energy physics experiments
G. Haller
4.1.7 Elex Overview-Management V6
15
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Summary of July Delta-PDR Review
• “The electronics including software was already baselined at
the January PDR review”
• “Work with GSFC branch to qualify poly-switches for use in the
LAT electronics”
– Approved
• “Ensure that FPGA design practices adhere to GSFC
guidelines and recommendations for space-flight applications”
– Working with Rich Katz at GSFC to review LAT FPGA
designs. In process of sending designs to GSFC for review
G. Haller
4.1.7 Elex Overview-Management V6
16
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Summary of July Delta-PDR Review (Con’t)
• “Determine the need date for processor down-select based on
software design impact”
– Have selected BAE RAD750
• “Finalize the flight-software management plan and test plan”
– Flight software management plan (LAT-MD-00104-02)
entered into cyberdocs 6 November 2002
– Flight software test plan (LAT-TD-00786-01) entered into
cyberdocs 10 June 2002
G. Haller
4.1.7 Elex Overview-Management V6
17
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Summary of July Delta-PDR Review (Con’t)
• “Identify solution path to replace the functionality that would
have been provided by SCL COTS tool in the flight software.
Coordinate with I&T and mission operations”
– I&T has adopted a low level toolset (Python, Qt, XML,
MySQL) to implement the EGSE side of the I&T test
environment. FSW provides the hardware drivers for the
embedded system. Code already exists and is running on
test stands to replace the SCL register manipulation model.
FSW has adopted the I&T low level toolkit for its Test
Executive.
G. Haller
4.1.7 Elex Overview-Management V6
18
GLAST LAT Project
Gamma-ray Large
Area Space
Telescope
DOE/NASA Peer Critical Design Review, March 19-20, 2003
GLAST Large Area Telescope:
Electronics, Data Acquisition &
Flight Software
Management
Gunther Haller
Stanford Linear Accelerator Center
Manager, Electronics, DAQ & FSW
LAT Chief Electronics Engineer
haller@slac.stanford.edu
(650) 926-4257
G. Haller
4.1.7 Elex Overview-Management V6
19
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Management Outline
•
•
•
•
•
•
•
•
•
•
•
•
•
Team Leads
Team Partners
Contingency (Mass, Power, Cost)
Organization Chart
Work Flow
Testing Overview
Fabrication Plan
Schedule & Critical Path
Cost
Procurements
Configuration Management
Issues and Concerns
Summary
G. Haller
4.1.7 Elex Overview-Management V6
20
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Team Leads
•
•
•
•
•
•
•
Gunther Haller
– Project Manager Electronics, DAQ, Instrument Software
– Chief Electronics Engineer
– PCMS Schedule & Cost Lead
JJ Russell
– Instrument (Flight) Software Lead
Mike Huffer
– Data-Acquisition System Lead
Dave Nelson
– Mechanical & Thermal Engineering Lead
– I&T Lead
– Power/EMI System Lead
Jobe Noriel
– Packaging Engineering Lead
Jerry Clinton
– Manufacturing Lead
Nick Virmani/Darren Marsh
– Mission/Quality Assurance
G. Haller
4.1.7 Elex Overview-Management V6
21
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Team Partners
• Naval Research Lab
– Spacecraft interface board (Silver Engineering)
– Instrument flight software (Boot Code, SC Interface)
– CAL front-end electronics
• University of Santa-Cruz
– Tracker front-end electronics
• Goddard Space Flight Center
– ACD front-end electronics
G. Haller
4.1.7 Elex Overview-Management V6
22
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Contingency Handling
•
•
•
All contingency (Power, Mass, Cost) is held at LAT project level
Change requests to LAT Change Control Board are required to
account for variance
4.1.7 Changes which required increase in cost, mass, power:
Change Request #
Description
Status
LAT-XR-01242
Flight Software
Labor Increase
(SLAC)
Approved
LAT-XR-01753
Flight Software
Labor Increase
(NRL)
Approved
G. Haller
4.1.7 Elex Overview-Management V6
23
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Organization Charts
Electronics, DAQ & Flight Software
G. Haller
SU-SLAC
WBS 4.1.7
Reliability
D. Nelson
SU-SLAC
WBS 4.1.7.2
Quality Assurance
D. Marsh/N. Virmani
SU-SLAC/NRL
WBS 4.1.7.2
DAQ
M. Huffer
SU-SLAC
WBS 4.1.7.4/4.1.7.5
Enclosures/Harness
M .Freytag
SU-SLAC
WBS 4.1.7.7/4.1.7.8
Power System
D. Nelson
SU-SLAC
WBS 4.1.7.6
Instrument Software
J. Russell
SU-SLAC
WBS 4.1.7.9
GSE & Operation
M. Huffer
SU-SLAC
WBS 4.1.7.A
Instrument I&T
G. Haller
SU-SLAC
WBS 4.1.7.C
Front-End Elex
G. Haller
SU-SLAC
Tracker Elex
WBS 4.1.4
CAL Elex
WBS 4.1.5
ACD Elex
WBS 4.1.6
G. Haller
Section 7.4 Elec, DAQ, Flt SW Overview
4.1.7 Elex Overview-Management V6
24
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Development Testing LAT System
Power-PC
Processor
Flight
Software
28-V Power Supply
COM-card 1: LAT
Communication
Module
COM-card 2:
Trigger Module
TEM DAQ
Assembly
Tower Power
Supply
Assembly
(1.5V/2.5V/3.3V/
0-100V/0-150V)
•
•
•
•
•
•
•
Processor: Motorola Power-PC
Flight Software
LAT COM engineering modules for
– LAT Communcation
– Trigger
TEM DAQ Assembly
TEM Power-Supply Assembly
28-V Supply
LAT-TD-00861
G. Haller
4.1.7 Elex Overview-Management V6
25
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Testing Plan
•
•
•
ASIC’s are 100% acceptance
tested before assembly on
boards
– Radiation performance is lot
tested for single event
effects and total ionizing
radiation.
Function/Performance is tested
at the board level
Qualification and acceptance
tests including performance,
vibration, EMI/EMC, and thermal
vacuum are performed at the
component sub-assembly (box)
level.
G. Haller
4.1.7 Elex Overview-Management V6
26
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Fabrication Plan
•
•
•
•
•
•
•
ASIC’s
– Design: SLAC
– Fabrication: Agilent
– Packaging: ASAT
Printer-Circuit Boards
– Design:
• Spacecraft Interface Board: Silver
Engineering
• All other DAQ custom modules: SLAC
– Fabrication: qualified vendor
– Parts procurements: SLAC
– Assembly: qualified vendor
Enclosures
– Design: SLAC
– Fabrication: qualified vendor
Module Assembly (PCB’s/cables/enclosure)
– Design: SLAC
– Assembly: qualified vendor
Tower Power Supplies
– Circuit & board design, fabrication,
assembly: qualified vendor
– Enclosure design: SLAC
– Assembly: qualified vendor
Harness
– Design: SLAC
– Assembly: qualified vendor
Installation at SLAC
G. Haller
4.1.7 Elex Overview-Management V6
27
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Work Flow
GCCC,
GTCC
ASICs
TEM DAQ Board
TEM DAQ Enclosure
TEM PS Board
TEM Power Supply Enclosure
GLTC
ASIC
GASU DAQ Board
GASU Enclosure
GLTC
ASIC
PDU DAQ Board
PDU Enclosure
SIB Board
GLTC
ASIC
LCB Board
CPU Board
TEM DAQ
Assembly
Acceptance
Test
First layer
DAQ
modules
TEM
Assembly
TEM PS
Assembly
Acceptance
Test
GASU
Assembly
Acceptance
Test
PDU
Assembly
Acceptance
Test
SIU
Assembly
Acceptance
Test
EPU
Assembly
Acceptance
Test
Harness
Acceptance
Test
LAT
Integration
1st stage
Second
layer DAQ
modules
LAT
Integration
2nd stage
Add
Harness
LAT
Integration
3rd stage
PS Board
Crate Enclosure
Software
G. Haller
Acceptance
Test
4.1.7 Elex Overview-Management V6
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GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Key Milestones
G. Haller
4.1.7 Elex Overview-Management V6
29
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Key Milestones
G. Haller
4.1.7 Elex Overview-Management V6
30
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Critical Path
• TEM DAQ Assembly
– Flight TEM DAQ PC Board fab and loading Feb 04
• Requires flight TEM ASICs
• Tower Power Supplies
– Flight assemblies by March 04
• Is out for RFP, expected back March 25
– Depends on vendor response
G. Haller
4.1.7 Elex Overview-Management V6
31
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Cost by Fiscal Year
• W.B.S. 4.1.7 without contingency
FY00
in K$
FY01
in K$
FY02
in K$
FY03
in K$
FY04
in K$
FY05
in K$
Total
in K$
692
930
1,727
7,013
4,097
1,281
15,737
G. Haller
4.1.7 Elex Overview-Management V6
32
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Cost Contingency and Schedule
•
•
Status below is as of Jan 31-03
Item
In k$
Budget at Complete (a)
15,737
Contingency at Start*
2,830
Budgeted Cost for Work Scheduled (b)
4,206
Budgeted Cost for Work Performed
4,148
Actual Cost for Work Performed
4,238
Cost Variance
-90
-2.1% of (b)
Schedule Variance
-48
-1.1% of (b)
18% of (a)
Software-specific contingency: see Instrument Software
presentation
*contingency is held at project level
G. Haller
4.1.7 Elex Overview-Management V6
33
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
4.1.7 Electronics
FTEs
Manpower Plan
G. Haller
4.1.7 Elex Overview-Management V6
34
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Procurements
•
•
•
•
Long-Lead Procurements
– Tower power supplies (RFP close March 25)
– Processor (RFP in April)
– Voltage regulators (after CDR)
Major Upcoming Procurements Near-Term (< 4 months)
– FPGA’s
– Connectors
– MOS Transistors
– DC/DC Converters & Filters
– ASIC’s
Major Upcoming Procurements Long-Term (>4 months)
– Enclosures
– Harness
Minor Upcoming Procurements
– Miscellaneous electrical components
G. Haller
4.1.7 Elex Overview-Management V6
35
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Configuration Management and Information
Technology
• SLAC CM System
– Cyberdocs (web-based document storage): Electronically
stored documents, drawings, procedures, Work-OrderAuthorization (WOA’s)
– Risk Item Database
– Document Library
• Electronics, DAQ, Flight Software web-site
– http://www-glast.slac.stanford.edu
– Website is used to share information and store draft
documents,
– Directly access CM documents stored in cyberdocs
G. Haller
4.1.7 Elex Overview-Management V6
36
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Issues and Concerns
• Schedule is very tight
– Critical path has little room for delay
• Dependency on delivery of procured items
G. Haller
4.1.7 Elex Overview-Management V6
37
GLAST LAT Project
DOE/NASA Peer Critical Design Review, March 19-20, 2003
Summary
• Technically the electronics and instrument software are on
track
• Schedule and budget plan are fully in PCMS down to level 7
since PDR, both are on track
• Critical path and contingency analyzed
• No unusual risks besides risks of any high-energy physics
experiment and space flight instrument
• Testing, fabriation, and workflow plans in place
• Experienced management and technical team
G. Haller
4.1.7 Elex Overview-Management V6
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