GLAST LAT Project
Gamma-ray Large
Area Space
Telescope
CDR/CD-3 Review, May 12-15, 2003
GLAST Large Area Telescope:
Electronics, Data Acquisition &
Flight Software
Gunther Haller
Stanford Linear Accelerator Center
Manager, Electronics, DAQ & FSW
LAT Chief Electronics Engineer
haller@slac.stanford.edu
(650) 926-4257
LAT-PR-01967
4.1.7 Electronics, DAQ, FSW 1
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Outline
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Management & System Engineering
Components & Assemblies
Thermal & Mechanical
Verification & Test
Fabrication
Risks
Budget & Schedule
LAT-PR-01967
4.1.7 Electronics, DAQ, FSW 2
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Management & System Engineering
LAT-PR-01967
4.1.7 Electronics, DAQ, FSW 3
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Organization Charts
Electronics, DAQ & Flight Software
G. Haller
SU-SLAC
WBS 4.1.7
Reliability
D. Nelson
SU-SLAC
WBS 4.1.7.2
Quality Assurance
D. Marsh/N. Virmani
SU-SLAC/NRL
WBS 4.1.7.2
DAQ
M. Huffer
SU-SLAC
WBS 4.1.7.4/4.1.7.5
Enclosures/Harness
M .Freytag
SU-SLAC
WBS 4.1.7.7/4.1.7.8
Power System
D. Nelson
SU-SLAC
WBS 4.1.7.6
Instrument Software
J. Russell
SU-SLAC
WBS 4.1.7.9
GSE & Operation
R. Claus
SU-SLAC
WBS 4.1.7.A
Instrument I&T
G. Haller
SU-SLAC
WBS 4.1.7.C
Front-End Elex
G. Haller
SU-SLAC
Tracker Elex
WBS 4.1.4
CAL Elex
WBS 4.1.5
ACD Elex
WBS 4.1.6
LAT-PR-01967
4.1.7 Electronics, DAQ, FSW 4
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
LAT Electronics
ACD
TKR Front-End Electronics (MCM)
ACD Front-End Electronics (FREE)
CAL Front-End Electronics (AFEE)
16 Tower Electronics Modules (TEM)
TKR
–
–
CAL
DAQ electronics module (DAQ-EM)
Power-supplies for tower electronics
Global-Trigger/ACD-EM/SignalDistribution (GAS) Unit*
Spacecraft Interface
Unit (SIU) (1+1
spare)
– Storage Interface
Board (SIB):
EEPROM Storage,
Spacecraft
MIL1553
interface, control
& data
– LAT control CPU
– LAT
Communication
Board (LCB): LAT
command and
data interface
LAT-PR-01967
3 Event-Processor Units (EPU) (2+1
spare)
– Event processing CPU
– LAT Communication Board (LCB)
– Storage Interface Board (SIB)
EPU-1
EPU-2
Pw r Dist. Box
spare
spare
GASU
spare
spare
spare
SIU-P
SIU-R
EPU-3
Power-Distribution Unit (PDU)*
– Spacecraft interface,
power
– LAT power distribution
– LAT health monitoring
* Primary & Secondary Units shown in one chassis
4.1.7 Electronics, DAQ, FSW 5
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Evolution and Heritage of DAQ Design
Current Design:
– Global trigger, ability to reduce hardware trigger rate from tracker
– Event building in hardware
– Data switch to move complete event fragments from hardware event
builder to processor and to spacecraft
– 2 processors for event processing
– Communication to TKR/CAL/ACD systems unified
Heritage:
– Similar data-acquisition system was used on balloon flight (TEM, one
event-processing CPU, one spacecraft-interface-equivalent control CPU)
– Electronics components: mostly components with flight-heritage (FPGA’s,
LVDS converters, memories)
– ASIC technology same as for tracker, calorimeter, ACD systems
– Trigger, dataflow, event assembly, and event filter processing very similar
to past high-energy physics experiments
LAT-PR-01967
4.1.7 Electronics, DAQ, FSW 6
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Data-Acquisition (DAQ) System Overview
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•
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Configuration, triggering, event-flow
control and readout, monitoring, and
supply of power to
– 16 Calorimeter and Tracker
towers with a total of ~850,000
tracker channels and ~3,000
calorimeter channels
– 12 ACD front-ends with a total of
208 ACD channels
Interface to spacecraft for control,
data, monitoring, and power
Trigger system (hardware selection
of possibly interesting events)
Event filtering
Housekeeping
Operational thermal control
LAT-PR-01967
Spacecraft
LAT
VCHP
Heater
Control
4.1.7 DataAcquisiton
(DAQ) System
C
A
L
T
K
R
Tower 0
C
A
L
T
K
R
Tower 1
C
A
L
T
K
R
Tower 15
A
C
D
A
C
D
A
C
D
0
1
11
4.1.7 Electronics, DAQ, FSW 7
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
DAQ Technical Budget Summary
Technical Resources
• DAQ Mass (Contingency is held at the project level)
– Sub-system allocation: 220 kg
– Detailed estimate: 199.3 kg
• DAQ Power (Contingency is held at the project level)
– Subsystem allocation: 327.5 W
– Detailed estimate: 326.2 W
• CPU Cycles
– Allocation: 2 CPU’s
– Detailed estimate: < 1 CPU
LAT-PR-01967
v9
4.1.7 Electronics Overview
8
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
LAT Electronics Hierarchy
•
•
•
SC
SC Science
Commanding
Data
Tower Electronics Module
– Interface to calorimeter and tracker on each tower
– Monitoring
– Combination of sub-system trigger signals to
primitives
– Event buffering
GAS Unit
– Command-response unit receives and distributes
command, clock, and data
– Global trigger unit generates LAT-wide readout
decision signals based on trigger primitives from
TEM’s and ACD
– Event-builder unit builds complete LAT events out of
asynchronous event-fragments; Forward complete
events to dynamically selected target EPU’s or
spacecraft (SC science interface)
– ACD electronics module tasks much like TEM for
TKR/CAL
EPU: Event processor unit runs filter algorithm to reduce
10kHz input event rate down to 30 Hz (with two EPU’s)
•
SIU: Spacecraft interface unit controls LAT and contains
command interface to spacecraft
•
Instrument software
– runs on EPU and SIU processors only
•
There are
– 2 prim EPU’s, 1 redundant EPU (not shown)
– 1 prim SIU, 1 redundant SIU (not shown)
– 1 prim GAS, 1 redundant GAS (not shown)
– 1 prim PDU (not shown), 1 redundant PDU (not shown)
LAT-PR-01967
EPU 0
EPU 1
SIU
GAS Unit
Event
Builder
TEM 0
C
A
L
T
K
R
Command
Response
Unit
Global
Trigger
TEM 1
C
A
L
T
K
R
v9
TEM 15
C
A
L
T
K
R
ACD Electronics
Module
A
C
D
A
C
D
A
C
D
0
1
11
4.1.7 Electronics Overview
9
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
LAT Power Distribution
•
•
•
•
•
•
SIU’s are powered directly by
spacecraft on dedicated feeds
Rest of LAT electronics is powered via
SC main feed to PDU
– Prime and redundant SC feeds
connected to prime and redundant
PDU circuits
PDU controls power to towers, to
GASU, and to EPU’s
– Either PDU circuit can supply
power to clients
GASU switches power to ACD
– Prime and redundant GASU circuit
can supply power to ACD
TEM’s switch power to TKR/CAL
– No redundancy in tower power
system
Heater power circuit not shown
LAT-PR-01967
SC Main
Feed P
EPU
P0
EPU
P1
SC SIU P
Feed
SC Main
Feed R
SC SIU R
Feed
SIU
P
EPU
R
PDU
Board P
SIU
R
PDU
Board R
PDU
Power Distribution
ACD PS
P
TEM
0
PS
Brd
DAQ B
DAQ B
C
A
L
T
K
R
GASU
DAQ P
C
A
L
T
K
R
GASU
DAQ R
ACD PS
R
TEM
14
TEM
1
PS
Brd
Power Distribution
Prime
Redundant
GASU
A
C
D
A
C
D
A
C
D
0
1
11
v9
TEM
15
PS
Brd
PS
Brd
DAQ B
DAQ B
C
A
L
T
K
R
C
A
L
T
K
R
4.1.7 Electronics Overview
10
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
LAT Electronics (Signals)
•
•
•
•
•
•
•
TKR: Tracker
CAL: Calorimeter
ACD: Anti-Coincidence
Detector
TEM: Tower Electronics
Module
EPU: Event Processor Unit
SIU: Spacecraft Interface
Unit
GAS Unit: Global TriggerACD-Signal Distribution
Unit
From SC P/R
1 PPS/GRB
Alert
To SC P
Science Data
Filtering Software
EPU
P0
EPU
P1
EPU
R
SIU
P
SIU
R
Command/
Control/Monitor
Software
GAS
Board P
GAS
Board R
GAS Unit
Command Response Unit
Global Trigger
Event Builder
ACD Electronics Module
TEM 0
C
A
L
T
K
R
Command Response Unit
Global Trigger
Event Builder
ACD Electronics Module
Prime
Redundant
TEM 7
C
A
L
T
K
R
TEM 8
A
C
D
0
LAT-PR-01967
To SC P/R
MIL1553/
Discretes
To SC R
Science Data
A
C
D
A
C
D
1
C
A
L
T
K
R
TEM 15
C
A
L
T
K
R
11
v9
4.1.7 Electronics Overview
11
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Example: Control Path
•
•
•
•
Control from either SIU to
either GASU CommandResponse Unit (CRU)
Control from either GASU
CRU to each TEM
Control from TEM to
CAL/TKR
Use “Look-At-Me”
command to switch
between redundant
receivers
EPU
P0
EPU
P1
EPU
R
SIU
P
Command/
Control/Monitor
Software
GAS
Board P
GAS
Board R
GAS Unit
Command Response Unit
Global Trigger
Event Builder
ACD Electronics Module
TEM 0
C
A
L
T
K
R
Command Response Unit
Global Trigger
Event Builder
ACD Electronics Module
Prime
Redundant
TEM 7
C
A
L
T
K
R
TEM 8
A
C
D
0
LAT-PR-01967
SIU
R
A
C
D
A
C
D
1
C
A
L
T
K
R
TEM 15
C
A
L
T
K
R
11
v9
4.1.7 Electronics Overview
12
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Example: Event Path
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•
•
•
•
Sub-system event-data
fragments from CAL/TKR to
TEM
Tower-event assembly and
transmission to GASU
Event-Builder (P and R)
LAT event assembly and
transmission to EPU (all
EPU’s)
Event-filtering and
transmission of CCSDS
coded data to GASU (P and
R)
GASU transmits data to SC
C&DH data ports (P and R)
(Event-Data
goes/comes
from all EPU’s,
only EPU P1
shown)
EPU
P0
To SC C&DH P
Event-Data Port
EventFiltering
EPU
P1
Raw
Data
EPU
R
SIU
P
SIU
R
Filtered
Data
GAS
Board P
GAS
Board R
Command Response Unit
Global Trigger
Event Builder
ACD Electronics Module
Prime (P)
Redundant (R)
Command Response Unit
Global Trigger
Event Builder
ACD Electronics Module
GAS Unit
TEM 0
C
A
L
T
K
R
TEM 7
C
A
L
T
K
R
TEM 8
A
C
D
0
LAT-PR-01967
To SC C&DH R
Event-Data Port
A
C
D
A
C
D
1
C
A
L
T
K
R
TEM 15
C
A
L
T
K
R
11
v9
4.1.7 Electronics Overview
13
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Datapath & Building Events
Tower
Front-End
Latch
on
trigger
Assemble
TEM
Event
~50,000 TKR
GTFE MEM Cells
With 2 Events
Digitize
on
trigger
GASU Event
Builder
TEM
Cable
TKR FIFO
With 1 Event
EPU
LCB->
Processor ->
LCB
Assemble
LAT
Event
SW
Filter
CAL ADC
Data
Trigger
Data
CAL-TRG FIFO
With 3 Events
GASU Event
Builder
Spacecraft
From
other
TEM’s
FIFO for each
Tower
LAT-PR-01967
v9
4.1.7 Electronics Overview
14
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Summary of July Delta-PDR Review
•
•
•
•
•
“Work with GSFC branch to qualify poly-switches for use in the LAT
electronics”
– Approved
“Ensure that FPGA design practices adhere to GSFC guidelines and
recommendations for space-flight applications”
– Working with Rich Katz at GSFC to review LAT FPGA designs. Submitted
designs in April 03.
“Determine the need date for processor down-select based on software design
impact”
– Have selected and placed order for BAE RAD750
“Finalize the flight-software management plan and test plan”
– Flight software management plan (LAT-MD-00104-02) and Flight software
test plan (LAT-TD-00786-01) released and in cyberdocs
“Identify solution path to replace the functionality that would have been
provided by SCL COTS tool in the flight software. Coordinate with I&T and
mission operations”
– I&T has adopted a low level toolset (Python, Qt, XML, MySQL) to
implement the EGSE side of the I&T test environment. FSW provides the
hardware drivers for the embedded system. Code already exists and is
running on test stands to replace the SCL register manipulation model.
FSW has adopted the I&T low level toolkit for its Test Executive.
LAT-PR-01967
v9
4.1.7 Electronics Overview
15
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Peer-CDR Review RFA Status
RFA #
1
6
7
8
8
12
14
15
16
17
20
23
24
26
RFA
Status
GBM Signal Use
Change Control of Docs
SIIS 1PPS Timing Accuracy
SIIS Redundancy
Population of SIB in EPU/SIU
retracted/merged with other RFA
retracted/merged with other RFA
Event Builder Switch
Error Handling in RAD750
RAD750 Exchange Info
Hardware Protection of ACD PMT
SPICE Analysis of Power
Grounding Diagram
TEM Mechanical
Accepted
Accepted
Accepted
Pending
Accepted
Accepted
Accepted
Accepted
Accepted
Accepted
Accepted
Accepted
Accepted
Accepted
RFA’s #2, 3, 4, 5, 10, 11, 13, 18, 19, 21, 22, 25: see FSW presentation
LAT-PR-01967
v9
4.1.7 Electronics Overview
16
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Specification Tree
Mission
Science
Requirements
Document
LAT IOC/MOC/
SSC Interface
Control
Documents
Mission System
Specification
Interface
Rqmts
Ground System Rqmts
Science
Rqmts
LAT-SC Interface
Requirements
Document
Mission
Rqmts
Interface
Rqmts
LAT
LAT Performance
Specification
LAT-SS-00010
LAT
Environmental
Specification
LAT-SS-00778
LAT IOC
Performance
Specification
LAT-SS-00015
LAT-SC Interface
Control
Documents
LAT
Subsystem
Mechanical
Subsystem
Specification
LAT-SS-00115
Trigger & Dataflow
Subsystem
Specification
LAT-SS-00019
TKR Subsystem
Specification
LAT-SS-00017
ACD Subsystem
Specification
LAT-SS-00016
Radiator Design
Specification
LAT-SS-00394
TCS Performance
Specification
LAT-SS-00715
X-LAT Plate
Design
Specification
LAT-SS-01240
Grid Box Design
Specification
LAT-SS-00775
LAT-PR-01967
ACD Design
Specification
LAT-SS-00352
LAT Trigger
Specification
LAT-SS-00284
Power
Subsystem
Specification
LAT-SS-00136
SAS
Subsystem
Specification
LAT-SS-00020
CAL Subsystem
Specification
LAT-SS-00018
LAT Flight SW
Specification
LAT-SS-00399
LAT TKR Design
Specification
LAT-SS-00134
LAT Dataflow
Specification
LAT-SS-00285
LAT Readout
Electronic
Specification
LAT-SS-00152
Tower Power
Supplies
Specification
LAT-SS-01537
LOF
Subsystem
Specification
LAT-SS-00021
SAS Design
Specification
LAT-SS-00505
CAL Design
Specification
LAT-SS-00210
v9
LAT Operations
Facility
Specification
LAT-SS-01783
Design
Specification
4.1.7 Electronics Overview
17
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Level III Key Requirements Summary
Electronics
Ref: LAT-SS-00019
Adjust Input timing resolution
TACK latency
Timing Jitter
Dead-time contribution
Event Deadtime Report
<100 ns
Trigger acknowledge output
< 1.3 s
< +/- 50 ns
< 5 s
Acknowledge blocking
Dead time cause
< 500 ns
Event Data Contribution
Diagnostics Mode
Test
Test/Demonstration
Test
Test
Test
Test/Demonstration
Test/Demonstration
Test
Test/Demonstration
Test/Demonstration
50 ns
Meet Requirement
< 1.3 usec
< 50ns
< 200 nsec
Meet Requirement
Meet Requirement
< 500 ns
Meet Requirement
Meet Requirement
Verify commanding interface
GRB response
Test/Demonstration
Test/Demonstration
Meet Requirement
Meet Requirement
Readout and overwrite protection
Filtering functions
Pointing & coordinate system
Dead-time for average orbit condition < 5%
Test/Demonstration
Test/Demonstration
Test/Demonstration
Test/Demonstration
Meet Requirement
Meet Requirement
Meet Requirement
< 5% for T&DF
Monitoring & calibration
< 0.25 m3
< 188 kg
Test/Demonstration
Inspection
Inspection
Meet Requirement
< 0.25 m3
< 188 kg
< 142 W (dayly average)
< 330 W (peak, average over 1 sec)
Test
Test
< 142 W (daily average)
< 330 W (average over 1 sec)
Control System
Event Data
Volume
Mass
Power
LAT-PR-01967
v9
4.1.7 Electronics Overview
18
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Flowdown – Requirements to Design
Parameter
Requirement
Constraint
Characteristics Needed
Design
Trigger
Adjust Input timing
resolution
TACK latency
Timing Jitter
Dead-time contribution
Event Deadtime Report
<100 ns
Power
< 1.3 us
< +/- 50 ns
< 5 us
< 500 ns
Mass
Volume
Complexity
Reliability
Readout and overwrite protection
Power
Efficient Event Assembly
Filtering functions
Dead-time for average orbit
condition < 5%
Buffering for burst up to 20,000
photon events
Mass
Volume
Complexity of hardware versus
software
Reliability
Hardware/Firmware system
Central Trigger
Decision Block
(Global Trigger,
located in GAS
Unit)
Dataflow
Event buffering in Front-end
electronics, TEM, GASU
Central Event Builder
Hardware event assembly
(Hardware, located
in GAS Unit)
Processor for filtering
PowerPC Processor Farm
Error Recovery
LAT-PR-01967
v9
4.1.7 Electronics Overview
19
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
External/Internal Interfaces
•
•
All external DAQ interfaces released with the exception of final spacecraft
interface
All internal interfaces released
External Interfaces
Interface
Document
Internal Interfaces
Status
Interface
Document
Status
LAT-TD-00605
Released
Calorimeter
LAT-SS-00238
released
Tower
Electronics
Module
Tracker
LAT-SS-00176
released
TEM PowerSupply Unit
LAT-SS-01281
Released
GAS Unit
LAT-SS-00363
released
Mechanical/
Thermal
LAT-SS-01794
released
LAT-SS-01544
LAT-TD-00639
LAT-TD-01545
LAT-TD-01546
LAT-TD-01547
Released
ACD
Spacecraft
GSFC-433-IRD
in progress at
GSFC but
content stable
SIU/EPU
LAT-SS-01539
Released
PDU
LAT-SS-01542
Released
VCHP Control
Unit
LAT-SS-00715
Released
LAT-PR-01967
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4.1.7 Electronics Overview
20
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Redundancy at Assembly Level
•
•
•
•
•
•
FMEA and Reliability Analysis: see System Engineering presentation
Spacecraft Interface Unit (SIU)
– 1 prime and 1 redundant , either one can run the LAT electronics,
including any combination of PDU P and R, GASU P and R, EPU P
and R
• Note that SC science interface, 1 PPS, and GRB signal are
connected to GASU, not to SIU
Event Processor Unit (EPU)
– 2 prime and 1 redundant , each can be used in any combination of
PDU P and R, GASU P and R, SIU P and R
GAS Unit (GASU)
– 1 prime and 1 redundant , each can be used in any combination of
PDU P and R, EPU P and R, SIU P and R
Power Distribution Unit (PDU)
– 1 prime and 1 redundant , each can be used in any combination of
GASU P and R, EPU P and R, SIU P and R
Tower Electronics Module (TEM)
– 16 prime and 0 redundant , each can be used in any combination
of GASU P and R, EPU P and R, SIU P and R
LAT-PR-01967
v9
4.1.7 Electronics Overview
21
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Components & Assemblies
• Design
• Mechanical
• Thermal
• As an example, TEM assembly is presented in more detail
LAT-PR-01967
v9
4.1.7 Electronics Overview
22
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Tower Electronics DAQ Module
•
TKR (8 cables)
CAL (4 cables)
CAL
Cable
ASIC
TKR
Cable
ASIC
Control, Event &
HSK Signals
Power
Trigger
Power to
TEM Elex
Trigger
Controller
Common
Controller
LAT-PR-01967
Power from TEM
PS Module
Trigger signals
to/from Global
Trigger on GAS Unit
Control & HSK
signals from/to SIU,
Event data to EPU,
all via GAS Unit
Main DAQ module, one on each tower
– Controls and reads out data from
TKR MCM and CAL AFEE front-end
electronics
– Zero-suppresses CAL event data
– Buffers events in cable ASIC FIFO’s
– Assembles CAL and TKR event
fragments to tower event
– Transmits data to GASU
– Contains monitoring and low-rate
science circuits
– LVDS interface to front-end
electronics and GASU
– Hardware with software controlled
configuration and mode registers
• CAL ICD: LAT-SS-00238
• TKR ICD: LAT-SS-00176
• TEM ICD: LAT-SS-00363
v9
4.1.7 Electronics Overview
23
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Tower Electronics DAQ Module (Con’t)
•
•
•
•
Engineering Model with full
functionality and interfaces as flight
has been used extensively in 18
copies in the field, controlled and
readout with real-time software from
the FSW group, and I&T software
from the I&T group
Not just tested in TEM test-setup at
SLAC, but more importantly fully
integrated in set-ups with real subsystem electronics
– at NRL and at SLAC with CAL
electronics
– In Italy and at SLAC with TKR
electronics
– At SLAC, NRL with DAQ
electronics
Flight Model with 8 GTCC and 4
GCCC ASICs, plus 2 ACTEL’s:
design finished, layout complete,
ready for fabrication
LAT-TD-00605
LAT-PR-01967
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4.1.7 Electronics Overview
24
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Tower Electronics Module GCCC ASIC
•
•
•
•
•
•
•
TEM interface to calorimeter AFEE
– Configuration and readback data
– Trigger and event data handling
– Log suppression algorithm
– Event buffers
Contains
– Two 64x16 FIFO’s
– Three 128x16 FIFO’s
– Core Logic (generated from synthesized VHDL
code)
– LVDS drivers/receivers
VHDL code compiled into XILINX FPGA, is used on
TEM’s which are operating with CAL electronics
First ASIC prototype (GCCC1) came back from
fabrication end of March 03
DAQ tests show full functionality, performance up to 40
MHz (nominal f=20 MHz)
– Need more testing with full set of calorimeter AFEE
boards
– Need to perform radiation tests
If ASIC is ok, have full flight production in hand
LAT-TD-01549
LAT-PR-01967
CORE
FIFO
LVDS IO
GCCC
v9
4.1.7 Electronics Overview
25
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Tower Electronics Module GTCC ASIC
•
•
•
•
•
•
•
TEM interface to tracker MCM’s
– Configuration and readback data
– Trigger and event data handling
– Data reformatting
– Event buffers
Contains
– Two 64x16 FIFO’s
– Three 128x16 FIFO’s
– Core Logic (generated from synthesized
VHDL code)
– LVDS drivers/receivers
VHDL code compiled into XILINX FPGA, is used on
TEM’s which are operating with TKR electronics
First ASIC prototype (GTCC1) came back from
fabrication end of March 03
DAQ tests show full functionality, performance up
to 40 MHz (nominal f=20 MHz)
– Need more testing with full set of TKR MCM
boards
– Need to perform radiation tests
If ASIC is ok, have full flight production in hand
LAT-TD-01550
LAT-PR-01967
LVDS IO
FIFO
CORE
GTCC
v9
4.1.7 Electronics Overview
26
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Design & Verification for GCCC/GTCC
VHDL
Simulation
Netlist
Manual: Schematic of
IO, LVDS
Automatic: Layout, Place&Route
Automatic: Generate
Schematic
Layout: Add IO and LVDS. Result:
Complete Chip Layout
Compare
Simulation:
Spice
Full Chip
Schematic
Netlist w/o Parasitics
Netlist with Parasitics
Netlist
Full-Chip
Compare/Verific
ation
Full-Chip Simulation
with Synopsys
Full-Chip Simulation
with Synopsys
Stress &
Timing
Analysis
Fabrication
Flight-Model
Status 4/03
LAT-PR-01967
Test
v9
4.1.7 Electronics Overview
27
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
TEM Drawing Tree
2
3
Tower Electronics
Module
LAT-DS-01481
Tower Electronics
Module DAQ
Assembly, TEM
Power Supply
LAT-DS-01643
LAT-DS-01482
TEM Box Base
Specification, TEM
Power Supply Assy.
LAT-DS-00554
LAT-DS-01651
TEM Box Lid
TEM Connector Plate
Box Base, Power
Supply Assy.
Box Lid, Power
Supply Assy.
LAT-DS-00555
LAT-DS-01026
LAT-DS-00995
LAT-DS-00996
TEM Connector Pin
Flange Screw
Bracket A
Bracket B
LAT-DS-01031
LAT-DS-01487
LAT-DS-01027
LAT-DS-01028
Bracket C
Bracket D
LAT-DS-01029
LAT-DS-01030
Specification, TEM
Power Supply CCA.
Interface Control
Document, Power
Supply CCA
Circuit Card
Assembly, TEM DAQ
Specification, TEM
DAQ
Test Procedure, TEM
DAQ
LAT-DS-01646
LAT-DS-01644
LAT-DS-01645
Specification, TEM
DAQ CCA
LAT-DS-01647
Test procedure, TEM
Power Supply Assy.
LAT-DS-01652
Test Procedure, TEM
DAQ CCA
LAT-DS-01648
Printed Wire Board,
TEM DAQ CCA
LAT-DS-01649
Schematic Diagram,
LAT_DS_01650
LAT-DS-01537
LAT-DS-01281
LAT-PR-01967
v9
4.1.7 Electronics Overview
28
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
TEM Assembly Drawing (Example)
LAT-PR-01967
v9
4.1.7 Electronics Overview
29
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Tower Electronics Module (TEM)
PSU
TEM – PSU Stack
Tower Electronics Module
LAT-PR-01967
v9
4.1.7 Electronics Overview
30
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
TEM Temperature Profile
GCCC ASIC
GTCC
ASIC
ACTEL
FPGA
LAT-PR-01967
v9
4.1.7 Electronics Overview
31
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
TEM Component Thermal Data
•
TEM Cooling; Hottest single component
– PWB mounted flat to 2 mm 6061 Aluminum
• FPGA 3.1 OC J/C for ½ watt
– Polyimide PWB 0.33 W/m-K
• Using 9 cm2 footprint
• 2.7 OC for ½ watt
– CV2943 1.2 W/m-K
• 0.23 OC for ½ watt
FPGA
10 mil CV2943
62 mil PWB
10 mil CV2943
2 mm Aluminum
– Temperature rise from edge of TEM box to center of TEM box
• 2.1 OC
• Total Delta T for FPGA Junction Temperature
• = XLAT interface + SIU + PSU+ TEM + TEM Center + FPGA
– Delta T = 5.2+3.1+2.7+0.23+2.1 = 13.33 OC
LAT-PR-01967
v9
4.1.7 Electronics Overview
32
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Tower Power Supply Module
•
TKR enable
TKR Bias
Set
CAL enable
28
V
TKR
1.5V
Filter
TKR
2.5V
Filter
CAL Bias
Set
TKR 1.5V
TKR 2.5V
Analog
Filter
TKR 2.5V
Digital
TRK 0150V
Filter
TKR Bias 0150V Adj.
CAL
3.3V
Filter
CAL 3.3V
Analog
Input
filter
Engineering model tower
power supply built and used
in EGSE test-stands at
SLAC, NRL, GSFC, Italy
– Flight like interfaces and
functionality
Filter
CAL
3.3Digial
CAL 0100V
Filter
CAL Bias 0100V Adj.
DAQ
3.3V
Filter
DAQ 3.3V
A
Thermister A
B
Thermister B
•
•
•
•
LAT-PR-01967
Built 1.5V supply with mostly
flight-components
Supplies went out for RFP,
responses are being
evaluated
Statement of Work: LAT-SS01537
ICD: LAT-TD-01281
v9
4.1.7 Electronics Overview
33
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
SIU/EPU Crate Electronics
•
•
•
•
•
Storage Interface Board (SIB)
– EEPROM
– MIL1553 Communication with spacecraft*
– Power Control of PDU/GASU power switches in PDU*
– Power Control of VCHP switches in heater box*
LAT Communication Board (LCB)
– Communication with GASU
• Commanding
• Read-back, house-keeping & event data
Power Supply Board (PSB)
– 28V to 3.3V/5V conversion
– LVDS-CMOS conversion of spacecraft discretes*
– System clock to GASU
CPU Board
Backplane (passive)
VCHP
Heater Box
BackPlane
SIB
Heater
Control*
Power
Control*
PDU
PCI
Interface
EEPROM
Spacecraft
MIL1553
MIL1553*
LCB
CommandResponse
GASU
PCI
Interface
FIFO
Event Data
GASU
Spacecraft
Discretes
PSB
LVDS Convertion
Spacecraft
Power
28-V DC/
DC
Power-On
Reset
GASU
3.3V/5V
System
Clock
CPU
Discrete I/O
PCI
Interface
Power PC
* Only used in SIU crate
LAT-PR-01967
v9
4.1.7 Electronics Overview
34
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
LCB and SIB
•
•
•
•
•
•
•
•
•
LAT Communication Board (LCB)
PCI-interface engineering model in
operation since early 03 (has PMC
connector)
Flight Model has cPCI connector: design
finished, layout close to complete
ICD: LAT-TD-00860
Storage Interface Board (SIB)
Designed/implemented by Silver
Engineering (Dennis Silver, Greg Clifford)
under contract by NRL (Kent Wood, Michael
Lovellette)
– Driver by Dan Wood (NRL)
Engineering model has been in test since
mid 02
Flight Model adds npn transistors for
heater control
– Schematic updated, waiting for layout
modification
ICD: LAT-SS-01539
LAT-PR-01967
v9
4.1.7 Electronics Overview
35
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Power Allocation Example: SIB
AT 33MHZ CPCI BUS SPEED
SIC
OPERATE STATE
EEPROM UPDATE STATE
OPERATE STATE
CURRENT (ma)
TYPICAL
MAX
3.3V
227
423
5V
79
79
3.3V
275
471
POWER (WATTS)
TYPICAL
5V
158
1.1
158
1.8
CURRENT (ma)
TYPICAL
MAX
3.3V
5V
3.3V
FPGA, RT54SX32S-1CQ208B (PCI)
153
178
Pullup Resistors pulled low
1
7
1
OMR9601CSCK (2.5V Reg) (EST)
8
10
SUMMIT DXE **
30
EEPROM (8) ***
32
32
SRAM (2), HLX6228TSR
6.8
ACQ245 (8)
0.64
0.64
AC138 (2)
0.16
0.16
AC273 (2)
0.16
0.16
ACT74
1.2
Transistor Drive On, 50% typ, 100%max
21.6
43.2
OSC
22.5
Misc
10
10
10
POR X2
1
TOTALS
227
79
275
**Assume 1553 at 1% duty cycle (which is nearly the same as idle)
***Assume EEPROMs not in write cycle
MAX
1.7
2.3
CURRENT (ma)
TYPICAL
MAX
EEPROM UPDATE
5V
7
100
8
1.6
30
10
1
158
3.3V
5V
3.3V
FPGA, RT54SX32S-1CQ208B (PCI)
153
178
Pullup Resistors pulled low
1
7
1
OMR9601CSCK (2.5V Reg) (EST)
8
10
SUMMIT DXE **
30
EEPROM (8) ***
228
228
SRAM (2), HLX6228TSR
6.8
ACQ245 (8)
0.64
0.64
AC138 (2)
0.16
0.16
AC273 (2)
0.16
0.16
ACT74
1.2
Transistor Drive On, 50% typ, 100%max
21.6
43.2
OSC
22.5
Misc
10
10
10
POR X2
1
TOTALS
423
79
471
**Assume 1553 at 1% duty cycle (which is nearly the same as idle)
***Assumes One EEPROM in write cycle
5V
7
100
8
1.6
30
10
1
158
Courtesy of Dennis Silver, Silver Engineering
LAT-PR-01967
v9
4.1.7 Electronics Overview
36
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Processor
•
•
BAe750 compact PCI board
• 750 class Power-PC
• 240 MIPS at 133 Mhz,
• Less Than 12W
• 128 Mbytes main memory
• 256 Kbytes SUROM
• VxWorks real-time operating system
– LAT ordered prototype, was received
Spring 02
– Since then used for software
development at NRL
• Boot-code
• Bench-mark for LAT filtering code
• Test with SIB MIL1553 prototype
– Same board selected/ordered by GLAST
spacecraft contractor
Order placed April 03,
– < 6 months delivery of 3 prototype
boards
– 12 months for flight articles
– Weekly telecon has started with SAI &
BAE
LAT-PR-01967
v9
4.1.7 Electronics Overview
37
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
GAS Unit (Signal Distribution and Trigger)
•
•
•
•
•
Uses GLTC ASIC to receive LVDS signals
and to logically mask and combine 228
ACD trigger signals
Global Trigger controller (LAT-TD-01545)
– Combines trigger inputs from TKR,
CAL, ACD and makes trigger
decision
– Distributes trigger message with
target CPU for event, time-stamp,
event-number, and trigger type to
sub-systems
– Total time from particle in detector
to receipt of trigger accept signal: 2
sec
Command Response Unit (LAT-SS00416/0606)
– Distributes control from SIU to
TEM’s, GLT, ACD EM, EB
– Transmits readback data from TEM’s,
GLT, ACD, EB to EPU’s
Hardware with software controllable
configuration & mode registers
One prime and one redundant DAQ
board
LAT-PR-01967
Command-Response
Trigger
EPU
P0
EPU
P1
EPU
R
SIU
P
SIU
R
GAS
Board P
Global
Trigger
P
GAS
Board R
CMDResp.
Unit P
GAS Unit
Event
Builder
P
ACD EM
P
TEM 0
C
A
L
T
K
R
Control,
Commanding
Event
Builder
R
TEM 8
T
K
R
A
C
D
0
v9
Global
Trigger
R
ACD EM
R
TEM 7
C
A
L
CMDResp.
Unit R
A
C
D
A
C
D
1
C
A
L
T
K
R
TEM 15
C
A
L
T
K
R
11
4.1.7 Electronics Overview
38
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
GAS Unit (ACD EM & Event Data)
•
•
•
ACD EM (LAT-SS-00363/00639)
– Controls and reads out data from
ACD front-end electronics
– Buffers events
– Assembles 12 ACD event fragments
into ACD event
– Transmits data to EB
– Contains monitoring circuits
Event Builder (LAT-TD-01546)
– Receives event fragments from
TEM’s, AEM, and GLT at up to 10
KHz rate
– Builds LAT event and transmits to
EPU’s/SIU’s at up to 10 KHz rate
– Receives CPU data, forwards to
• other CPU’s, or
• to SC (science data interface)
Hardware with software controllable
configuration & mode registers
To SC P
Science
Data
Filtering Software
EPU
P0
EPU
P1
EPU
R
SIU
P
SIU
R
GAS
Board P
Global
Trigger
P
GAS
Board R
CMDResp.
Unit P
GAS Unit
Event
Builder
P
ACD EM
P
TEM 0
C
A
L
T
K
R
Event
Builder
R
Prime
Redundant
C
A
L
T
K
R
CMDResp.
Unit R
TEM 8
A
C
D
v9
Global
Trigger
R
ACD EM
R
TEM 7
0
LAT-PR-01967
To SC R
Science
Data
A
C
D
A
C
D
1
C
A
L
T
K
R
TEM 15
C
A
L
T
K
R
11
4.1.7 Electronics Overview
39
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
GAS Unit & GLTC ASIC
•
•
•
•
•
Engineering Model with partial functionality and interfaces
as flight has been used in several copies in the field,
controlled and readout with real-time software from the
FSW group, and I&T software from the I&T group
ACD EM at SLAC and GSFC, with real ACD front-end
electronics
Trigger input signal received and trigger accept message
generated via SLAC COM-module (either CAL, TKR, and
ACD programmed)
Model with 14 GLTC and 9 ACTEL’s: in fabrication
GLAST LVDS Translator Chip (GLTC) ASIC
– LVDS receivers for ACD veto and CNO trigger signals
– Maskable logical-OR function of ACD trigger signal
– Handles 18 input signal channels
– Contains
• Core Logic (generated from synthesized VHDL code)
• LVDS receivers
– First version ASIC was received in Dec 02
– Fully working, is flight design
– Flight quantity is on shared LAT wafer-run back from fab
March 03, in testing
• Need radiation testing
– LAT-TD-0148
LAT-PR-01967
v9
4.1.7 Electronics Overview
40
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
GASU Stress Model
FEM Model Analysis Approach
- Plate, Brick and Beam Elements
- Pinned Boundary Conditions
- Model Weight 31.4 lbs. (14.3 kg)
- First Mode 136.3 Hz
- Machined Aluminum 6061-T6
- Ultimate Strength
42000 psi
- Simplified Approach to Application of
Dynamic Load Factor defined by Miles Equation
- Applied Maximum Response at QUAL Level uniformly to
each of the three orthogonal axes
- 3s Load Levels used to account for peak excitation.
- Ignored Mass Participation Effects and Non-uniform Distribution
of acceleration loads throughout the structure.
- Q = 10
- Safety Factor of 1.4 x Ultimate Strength
- Applied 3s DLF 134.52 Grms (44.84 Grms peak)
GASU ASSEMBLY SUMMARY
Load Axis
Maximum Stress
psi
Allowable
psi
Margin
X
Y
Z
4054
3692
11380
30000
30000
30000
6.40
7.13
1.64
LAT-PR-01967
v9
4.1.7 Electronics Overview
41
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
GASU Stress Model
X-Axis Load Case
Displaced Shape and Stress Contour
Maximum Stress
Natural Frequency
First Mode 136.3 Hz
Y-Axis Load Case
Displaced Shape and
Stress Contour
Maximum Stress
Z-Axis Load Case
Displaced Shape and Stress Contour
Maximum Stress
LAT-PR-01967
v9
4.1.7 Electronics Overview
42
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
PDU Power Distribution
•
•
•
•
•
•
•
Discrete signal from SIU selects which SC
main power to use
28V/3.3V PDU converter is powered when SC
Main feed is powered
Discrete signal from SIU turns on power to
GASU prime or redundant DAQ board
PDU FPGA controls power switches for TEM’s,
EPU’s, and ACD supplies in GASU
Power switches are implemented with PMOS
transistors
ICD: LAT-SS-01542 and LAT-SS-01543
Status: layout complete, ready for fabrication
SC Main
Feed P
SC Main
Feed R
Prime
Redundant
SIU
P
PDU
Prime
Board
SC Feed Select
PDU
Redundant
Board
LC Filter
SIU
R
GASU
Power
Switches
Filter
28V/3.3V
Converter
TEM/EPU
Power
Switches
PDU FPGA
Control
GASU P
DAQ
Power
Supplies
GASU R
DAQ
Power
Supplies
16 Towers,
3 EPU’s,
ACD
Supplies
0
LAT-PR-01967
v9
1
11
4.1.7 Electronics Overview
43
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
DAQ Thermal & Mechanical
• Thermal and Mechanical Analysis documented in LAT-TD02138
LAT-PR-01967
v9
4.1.7 Electronics Overview
44
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Thermal
•
•
•
•
•
•
•
TEM
3.4 watts
TEM Power Supply (PS) 11.7 watts
GASU
24.9 watts
PDU
18.1 watts
EPU
24.3 watts
SIU
27.2 watts
Stackups
– TEM, TEM PS, EPU -> 39.4 watts
– TEM, TEM PS, SIU -> 42.3 watts
– TEM, TEM PS, PDU -> 33.2 watts
– TEM, TEM PS, GASU ->27.5 watts
LAT-PR-01967
•
•
Assumptions
Thermal boundaries for DAQ
– -40C to +55C for Qualification
– Uniform thermal connection to
X-LAT plates
– Only thermal conduction
considered
– No thermal conduction to
calorimeter base plates.
– 100 OC maximum Si junction
temp
Thermal Resistances/Conductance's
– Al 6061
154 W/m-K
– Polyimide 0.33 W/m-K
– CV2943 adhesive 1.26*W/m-K
– Wedge-Lok 0.14 OC/W, 2 each 6”
– Actel FPGA 6.2 OC/W J-C
– Thermal Via, 12 mil, 2*103 OC/W
each
• 3.4 OC/W for an array of
64X8
v9
4.1.7 Electronics Overview
45
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
SIU/EPU Stackup
Only show SIU/EPU stack-up as an
example in this presentation, results are
also available for other LAT cases
SIU 27.2 W/ EPU 24.3W
PSU 11.7 W
TEM 3.4 W
TEM, TEM-PSU, and SIU/EPU/EMPTY Stack
10x Typical
•
•
•
LAT-PR-01967
Top & bottom covers are 0.08 in Al
Side walls are 0.15 in 6061 Al
Temperatures
– TEM = 0.2 OC Rise
– PSU = 0.7 OC Rise
• Thermal resistance for box below
• -> 0.11K/watt
– SIU = 2.0 OC Rise
• Thermal resistance for box below
-> 0.17K/watt
– Total temp rise
• 0.2 + 0.7+(3.4*.11)+2+(11.7*.17) =
5.2 OC Rise
v9
4.1.7 Electronics Overview
46
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
TEM-PSU-EPU/SIU
FEM Model Analysis Approach
- Plate, Brick and Beam Elements
- Model Weight 28.1 lbs. (12.77 kg)
- First Mode Natural Frequency = 238 Hz
- Machined Aluminum 6061-T6
* Ultimate Strength
42000 psi
- Modal Survey Run
Applied QUAL Level Random Vibration Spectrum
- Results Show Combined Effects of Random Excitation
- 3s Load Levels Used to Account for Peak Excitation.
- Damping = .05 (5 %)
- Safety Factor of 1.4 x Ultimate Strength
- 14.14 Grms Input Level
- Ti 6Al-4V Standoffs
- Ti 6Al-4V M6x1 Socket Head Cap Screw Mounting Bolts
* Ultimate Strength 160ksi
STRESS SUMMARY
- Maximum Stresses are produced in the Titanium Standoffs
- Stress Summary shows Standoff Stresses and Margins
STRESS SUMMARY
Load Case
QUAL
Units
s max d max
psi
inch
14.14
14.14
14.14
Grms
Grms
Grms
31073
31073
17059
Y
Y
Z
10.464
0
8.5
Allowable MARGIN
psi
RANDOM
X
Y
Z
STATIC
Load Case
Worst Combination
LAT-PR-01967
v9
.002
.002
.002
s max d max
15676
.002
114286
114286
114286
2.678
2.678
5.699
Allowable MARGIN
114286
6.291
4.1.7 Electronics Overview
47
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Harness
•
•
•
•
•
•
Almost exclusively point-to-point cables
Connectors are Micro-D and Sub-D
Cables are shielded-twisted pair, 24 AWG
Installation in layers (see I&T); assembly drawings close to complete
Designed and fitted on 1:1 LAT model
Assembled by qualified vendor
LAT-PR-01967
v9
4.1.7 Electronics Overview
48
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Verification & Test
LAT-PR-01967
v9
4.1.7 Electronics Overview
49
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Verification Matrix (Doors Example Page)
ID
TDF L3 Performance Specification
VM
TDF3-7
The Level 1 Trigger (L1T) system shall be used to detect an interesting event and provide a
signal to the detector subsystems to capture and read out the event data.
Demo
TDF3-105
The trigger (TRG) system shall determine whether the event is interesting based on trigger
input signals received from the detector systems.
Demo
TDF3-9
The L1 trigger system shall accept trigger inputs from the ACD, TKR, CAL and dataflow
subsystems.
Demo
TDF3-11
The L1 trigger system shall time-align trigger inputs from the ACD, TKR, CAL and dataflow
subsystems to a precision better than 100 ns.
Test
TDF3-13
The L1 trigger system shall implement multiple overlapping triggers to allow cross-trigger
monitoring.
Test
TDF3-15
The L1 trigger logic shall generate a trigger acknowledge signal (L1TACK) and a trigger type
(e.g. CNO) for distribution to the subsystems.
Demo
TDF3-17
The L1 trigger logic shall generate the Trigger Acknowledge output with a latency of less than
1.3 mus.
Test
TDF3-106
The latency from the time the particle traverses the LAT to when the input signals need to be
recorded at the earliest shall be 2 ms.
Test
TDF3-19
The L1 trigger contribution to the overall trigger jitter shall be less than ± 50 ns.
Test
TDF3-107
The overall trigger jitter for the LAT shall be ± 200 ns.
Test
TDF3-51
LAT-PR-01967
The dataflow system shall reduce the event rate accepted by the L1T to an output rate
commensurate with the spacecraft interface as specified in 433-IRD-0001, keeping events
meeting the science objectives.
v9
Verif.
Demo
4.1.7 Electronics Overview
50
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Test Matrix
Applies to each board and assembly. In this slide the tests at each level are listed
Sine Sweep
Random Vib
Acoustic
Pressure Profile
Mass Property
Interface Verification
EMI/EMC
ESD Compatibility (Grnding)
Functional/Performance
Thermal Vacuum
Thermal Balance
Thermal Cycle
Humidity
Backout
Radiation
Inspection
Comments
Sine Burst
Environmental/Other
-
-
-
-
-
-
M
TA
-
-
TA
-
-
TA
M
A
A
I
C Board
1
E
C Board
1
Q
-
-
C Chassis
1
Q
A
A
C Pow er Supply
1
Q
-
-
C Board
17
F
-
C Chassis
17
F
-
C Pow er Supply
17
F
S Box
1
S Box
16
S Box
1
-
-
-
-
M
TA
-
-
TA
-
-
TA
M
A
A
I
A
A
-
-
M
TA
-
-
TA
-
-
TA
M
A
A
I
-
-
-
-
M
TA
-
-
TA
-
-
TA
M
A
A
I
-
-
-
-
-
M
TA
-
-
TA
-
-
TA
M
A
-
I
-
-
-
-
-
M
TA
-
-
TA
-
-
TA
M
A
-
I
-
-
-
-
-
-
M
TA
-
-
TA
-
-
TA
M
A
-
I
Q
TQ
TQ
TQ
TQ
A
A
M
TQ
TQ
TQ
TQ
TQ
A
-
M
A
-
I
F
TA
-
-
TA
-
-
M
TA
-
-
TA
TA
A
-
M
A
-
I
4 cycle T/V
S
TA
-
-
TA
-
-
M
TA
-
-
TA
TA
A
-
M
A
-
I
8 cycle T/V
Assem bly Level
S= Subsystem
C=Component
LAT-PR-01967
Electrical
Static Load
Unit Type
Component (ITEM)
Mechanical
Quantity
Assembly Level
Hardware
Unit Type
PF=Proto Flight
F=Flight
S=Spare
Q=Qual
E=Engineering / VerificationModel
Verification Method
T=Test
A=Analysis
M=Measurement
I=Inspection
Buy-Tested at supplier
Buy-Tested at supplier
QS=Qual by Similarity
TQ=Test, Qual Levels
TA=Test, Acceptance Levels
v9
4.1.7 Electronics Overview
51
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Testing Plan
•
•
•
ASIC’s are 100% acceptance
tested before assembly on
boards
– Radiation performance is lot
tested for single event effects
and total ionizing radiation.
Function/Performance is tested
at the board level
Qualification and acceptance
tests including performance,
vibration, EMI/EMC, and thermal
vacuum are performed at the
component sub-assembly (box)
level.
Vibration test to qual levels of EM
TEM passed
LAT-PR-01967
v9
4.1.7 Electronics Overview
52
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Verification & Test
Model Development
Hardware
Design
Software
Design/Develop
•
Fab
Test
Develop/Test
Formal Test
Release to I&T
Hardware and software development closely integrated
– Design of hardware versus software complexity optimized continuously
– Software runs with LAT engineering model electronics
– Continuous hardware versus software verification
– Full system including sub-system electronics from and at other institutions
– Independent verification process
• Exchange of hardware and software ->
–
–
–
–
–
ACD hardware, TKR hardware, CAL hardware
DAQ hardware
Flight software, I&T software
ACD Scripts, TKR scripts, CAL scripts, DAQ scripts
No integration at flight- LAT integration stage of components which have not
operating fully integrated in earlier stages
• Exception is spacecraft, since simulator is only simulating and is not real
hardware/software
LAT-PR-01967
v9
4.1.7 Electronics Overview
53
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Verification & Test (Con’t)
Development Cycles
EM 1
Release to I&T
EM2
Release to I&T
FU
•
•
•
Release to sub-systems
Release to sub-systems
Release to I&T
Three development cycles
– Engineering Model 1
• Single tower, single CPU
– Engineering Model 2
• Multiple tower, single CPU
– Flight Model
• Multiple towers, multiple CPU’s
Peer-Reviews after end of each development cycle
In addition regular LAT reviews (Manufacturing Readiness Review, etc)
LAT-PR-01967
v9
4.1.7 Electronics Overview
54
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Verification & Test: Example TEM & FSW
Power-PC
Processor
Flight
Software
28-V Power
Supply
LCB: LAT
Communication
Module
Transition-card:
Trigger Module
TEM DAQ
Assembly
Tower Power
Supply
Assembly
(1.5V/2.5V/3.3V/
0-100V/0-150V)
•
•
•
•
•
•
•
•
TKR Engineering
Tower with TEM
Processor: Motorola Power-PC
Flight Software
PMCIA LAT Communication Board for
– LAT Communication
Transition Board
– Trigger
TEM DAQ Assembly
TEM Power-Supply Assembly
28-V Supply
LAT-TD-00861
LAT-PR-01967
v9
4.1.7 Electronics Overview
55
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Verification & Test: RAD750/SIB
•
•
•
3u-cPCI BAE RAD750
processor prototype
6u-cPCI Storage Interface
Board (Silver Engineering)
– MIL1553 interface
SIB
Flight Software
– Boot code development
– SIB board code
driver/interface
– Benchmark of event
filtering performance
CPU
Courtesy of Dan Wood, NRL
LAT-PR-01967
v9
4.1.7 Electronics Overview
56
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Verification & Test: Front-End Data Simulator
One of 16
Towers
7
PC (one for 2 TEM’s)
0
T
C
P
I
P
•
•
•
•
•
H
a
r
d
D
i
s
k
PCI Bridge Card
PCI Bridge Card
PCI Bridge Card
TEM
High-Speed
Serial
Connection
P
C
I
CAL FrontEnd Data
Simulator
P
C
I
TKR FrontEnd Data
Simulator
PCI Bridge Card
System uses 9 PC’s
– 8 PC’s for 16 TEM’s
– 1 PC for ACD
Data transported to towers via high-speed data link; PCI bridge to
local bus on simulator
Data Simulators interface to TEM like CAL and TKR sub-system
electronics
– CAL and TKR simulator board identical except code in
FPGA’s
– Patch cable connect simulator to CAL and TKR TEM
connectors
Can operate TEM or LAT with data generated from simulations
Data simulator board fabricated and loaded, in test
LAT-PR-01967
Data into TEM
like CAL and
TKR subsystem
electronics
v9
Moselle
PCI bridge
4.1.7 Electronics Overview
57
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Verification & Test: Testbed
•
•
•
•
•
•
•
•
Full DAQ set with EM2 hardware (each with identical interfaces and
functionality as flight)
Incremental built according to plan (complete testbed Feb04)
All DAQ modules including 16 TEM’s
Harness like flight
TKR and CAL front-end electronics for 1 tower, front-end simulator
boards for other 15 towers
Full set of ACD EM2 electronics
Excellent hardware and software testbed
Spectrum Astro SC interface simulator (SIIS) for
–
–
TKR and CAL
Electronics Simulators
TEM DAQ Modules
TEM Power Supplies
Power, Control & Data Handling (C&DH)
Present plan is for SIIS to only provide primary interface
• Work in progress
EPU-1
EPU-2
Pwr Dist. Box
spare
spare
GASU
spare
spare
ACD
spare
SIU P
SIU R
SC
simulator
EPU-3
12 ACD Electronics
Cards
LAT EGSE
Spectrum Astro SIIS
LAT-PR-01967
v9
4.1.7 Electronics Overview
58
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Fabrication
LAT-PR-01967
v9
4.1.7 Electronics Overview
59
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Fabrication Plan
•
•
•
•
•
•
•
ASIC’s
– Design: SLAC
– Fabrication: Agilent
– Packaging: ASAT
Printer-Circuit Boards
– Design:
• Storage Interface Board: Silver
Engineering
• All other DAQ custom modules: SLAC
– Fabrication: qualified vendor
– Parts procurements: SLAC
– Assembly: qualified vendor
Enclosures
– Design: SLAC
– Fabrication: qualified vendor
Module Assembly (PCB’s/cables/enclosure)
– Design: SLAC
– Assembly: qualified vendor
Tower Power Supplies
– Circuit & board design, fabrication,
assembly: qualified vendor
– Enclosure design: SLAC
– Assembly: qualified vendor
Harness
– Design: SLAC
– Assembly: qualified vendor
Installation at SLAC
LAT-PR-01967
v9
4.1.7 Electronics Overview
60
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Spares Plan
Item
Need for
Flight
Qual
Flight
Spares
Spare
PCI boards
Tower DAQ Module Assembly
16
1
2*
n/a
Tower Power Supply Module Assembly
16
1
1*
n/a
GASU Assembly (contains prime and redundant unit)
1
1
0*
n/a
PDU Assembly (contains prime and redundant unit)
1
1
0*
n/a
SIU Assembly
2
1
0*
CPU/SIUSIB/PSB/LCB
EPU Assembly
3
0**
0*
EPU-SIB
* Qualification Models are flight spares
** EPU does not have separate qualification since crate is the same as SIU crate
LAT-PR-01967
v9
4.1.7 Electronics Overview
61
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Parts List & Procurements
•
Almost all DAQ EEE components approved
– Main remaining components
• ASICs need radiation test of flight lot before approval
•
Long-Lead Procurements
– Tower power supplies (RFP’s in, responses in evaluation)
– Processor (order placed)
– Voltage regulators (after CDR)
Major Upcoming Procurements Near-Term (< 4 months)
– FPGA’s
– Connectors
– MOS Transistors
– DC/DC Converters & Filters
– ASIC’s
Major Upcoming Procurements Long-Term (>4 months)
– Enclosures
– Harness
•
•
LAT-PR-01967
v9
4.1.7 Electronics Overview
62
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Work Flow
GCCC,
GTCC
ASICs
TEM DAQ Board
TEM DAQ Enclosure
TEM PS Board
TEM Power Supply Enclosure
GLTC
ASIC
GASU DAQ Board
GASU Enclosure
GLTC
ASIC
PDU DAQ Board
PDU Enclosure
SIB Board
GLTC
ASIC
LCB Board
CPU Board
TEM DAQ
Assembly
First layer
DAQ
modules
Acceptance
Test
TEM
Assembly
TEM PS
Assembly
Acceptance
Test
GASU
Assembly
Acceptance
Test
PDU
Assembly
Acceptance
Test
SIU
Assembly
Acceptance
Test
EPU
Assembly
Acceptance
Test
Harness
Acceptance
Test
LAT
Integration
1st stage
Second
layer DAQ
modules
LAT
Integration
2nd stage
LAT
Integration
3rd stage
PS Board
Crate Enclosure
Software
LAT-PR-01967
Acceptance
Test
v9
4.1.7 Electronics Overview
63
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Work Authorization and Manufacturing
Flow
• All manufacturing tasks will be performed on approved
Assembly and Inspection Data Sheets (work orders)
• Order parts per LAT procedures
• Kitting per LAT procedures
• End-item assembly parts are issued to assembly work orders
and sent to assembly supplier(s)
• Assembly and test instructions
• End items are received into project stores as they are received
from the assembly supplier
• End items are issued to test work order for acceptance testing
• Upon completion of acceptance testing, end items are returned
to project stores where are ready for issue to I&T
• More detail, see appendix
LAT-PR-01967
v9
4.1.7 Electronics Overview
64
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Issues, Risk & Mitigation Plans
LAT-PR-01967
v9
4.1.7 Electronics Overview
65
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Technical Issues and Status
• No known technical issues in respect to functionality and
performance except potentially
– TEM GTCC and GCCC ASICs
• Need radiation testing
LAT-PR-01967
v9
4.1.7 Electronics Overview
66
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Risk
• No single DAQ system failure can degrade LAT Electronics
capabilities below minimum science requirements
• Failure in SIU, PDU, or GASU can require use of the respective
redundant unit
• Failure in one of the two EPU’s can require use of the
redundant EPU unit. A second failure will reduce the available
EPU CPU power by a factor of 2
• Failure in TEM power-supply or TEM DAQ module can lead to
– Loss of a full tower (most of the assembly is single string)
– Loss of the calorimeter or parts of it
– Loss of the tracker or parts of it
LAT-PR-01967
v9
4.1.7 Electronics Overview
67
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Electronics Risk Summary
ID #
Risk Rank
Risk Description
•Flight-Software schedule is tight
• Depends on execution of LAT software development approach.
Elec/224
Moderate
• Delays in incremental review process may impact cost & schedule
Risk Mitigation
•Detailed software development plan, schedule and review
points established (3/24/03).
• Early integration of software to target hardware via EM
plan (Sept 03)
• Extensive use of test bed (Feb 04 and beyond)
• Tower Power Supplies Cost & Schedule depend on bids received
in response to RFP
• Proposals may exceed allocated schedule & funding
Elec/221
Moderate
• Assess schedule problem
• Determine cost impact to maintain schedule
• Negotiate with vendor to minimize impact
• Develop minimum impact re-plan & pursue CCB approval
• Two types of Tower Electronics Module ASICs submitted 1/18/03.
• 3 month turn around results in late reaction required if flaw is found
upon delivery and test resulting in schedule and cost impact
Elec/223
LAT-PR-01967
Low
• Protect schedule for additional ASIC run.
• Evaluate work arounds to mitigate late delivery of flight
ASICs and recover schedule margin.
• If untenable ASIC flaws occur, implement worst case
backup (FPGAs)
v9
4.1.7 Electronics Overview
68
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Cost & Schedule
LAT-PR-01967
v9
4.1.7 Electronics Overview
69
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
CCB Actions Affecting 4.1.7
Change Request # Description
Status
LAT-XR-01159-01
Move Procurements from FY04 Approved,
to FY03
$0K
LAT-XR-01242-01
Flight Software Labor Increase
(SLAC) (due to accounting
change, no net labor increase)
Approved,
$739K
LAT-XR-01753-01
Flight Software Labor Increase
(NRL)
Approved,
$300K
LAT-XR-01752-02
SLAC/HEPL Labor Escalation
Rates
Approved
-$105K
LAT-PR-01967
v9
4.1.7 Electronics Overview
70
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
4.1.7 Key Deliverable Milestones
Activity
Description
FY 04
FY 05
JAN FE B MAR AP R MAY JUN JUL AUG SE P OCT NOV DE C JAN FE B MAR AP R MAY JUN JUL AUG SE
OCT
P
4.1.7 Electronics
Flight TEM Assy 3,4-Elec to I&T
Flight TEM PS Assy 3,4-Elec to I&T
Flight TEM Assy 5,6-Elec to I&T
Flight TEM PS Assy 5,6-Elec to I&T
Flight TEM Assy 7,8-Elec to I&T
Flight TEM PS Assy 7,8-Elec to I&T
Flight TEM Assy 9,10-Elec to I&T
Flight TEM PS Assy 9, 10-Elec to I&T
Flight TEM Assy 11, 12-Elec to I&T
Flight TEM PS Assy 11, 12-Elec to I&T
Flight TEM Assy 13, 14-Elec to I&T
Flight TEM PS Assy 13,14-El ec to I&T
Flight TEM Assy 15, 16-Elec to I&T
Flight TEM PS Assy 15,16-El ec to I&T
Flight SIU-Elec to I&T
Flight Event Processor Units-Elec to I&T
Flight ACD Elec Modul e-Elec to I&T
Flight Harness-Elec to I&T
Run Date
04/21/03 15:05
Data Date
04/01/03
© Primavera Systems, Inc.
LAT-PR-01967
Forecast
Baseline
Product Available Date
Forecast
Baseline
Integration Need Date
LT-T7: Level 3 to AV :(tb)
FL-D7 Integration Mil estones CDR
AV : Up Triangle, L3: Down Triangl e
G LA ST L A T PR OJ EC T
A V: F loa t to
Le ve l 3 M ile sto nes
v9
Sheet 4
4.1.7 Electronics Overview
71
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Critical Path
• TEM DAQ Assembly
– Flight TEM DAQ PC Board fab and loading Feb 04
• Requires flight TEM ASICs
• Tower Power Supplies
– Flight assemblies by March 04
• RFP came back, being evaluated
– Needs negotiations with supplier
LAT-PR-01967
v9
4.1.7 Electronics Overview
72
GLAST LAT Project
Budget vs Actuals vs Performance CDR/CD-3 Review, May 12-15, 2003
DOE + NASA Project Expenditures
4.1.7 Electronics
Budget, Cost, Performance
20
$M, Then-Year Dollars
15
10
5
Actual Commitments
ACWP
BCWP
BCWS+ Planned Commitments
BCWS
0
. .
. .
FY00
LAT-PR-01967
. .
. .
FY01
. .
. .
. .
. .
FY02
. .
. .
. .
. .
. .
. .
. .
FY03
. .
. .
FY04
v9
. .
. .
. .
. .
. .
FY05
4.1.7 Electronics Overview
73
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Cost/Schedule Status
•
Status as of March 31, 2003:
Item
In k$
Budget at Complete
16,672
Budgeted Cost for Work Scheduled (a)
4,898
Budgeted Cost for Work Performed (b)
4,834
Actual Cost for Work Performed
4,828
Cost Variance
6
0.1% of (b)
Schedule Variance
-64
-1.3% of (a)
LAT-PR-01967
v9
4.1.7 Electronics Overview
74
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Summary
•
•
•
•
•
Most documentation in release cycle
– Have completed parts list for each module, submitted to Parts
Control Board. Most of those parts (90%) were already approved
by PCB on DAQ parts list.
– Need to complete Parts Stress Analysis for each module, close to
complete, to be submitted to PCB one week after CDR
No major technical issues
Design mature
Technical, cost & schedule status consistent with baseline objectives
Management structure in place to guide the project to completion
•
Manufacturing process defined
•
Ready to buy flight components
LAT-PR-01967
v9
4.1.7 Electronics Overview
75
GLAST LAT Project
LAT-PR-01967
CDR/CD-3 Review, May 12-15, 2003
v9
4.1.7 Electronics Overview
76
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Backup
LAT-PR-01967
v9
4.1.7 Electronics Overview
77
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Work Authorization
• All manufacturing tasks will be performed on approved
Assembly and Inspection Data Sheets (work orders)
– Responsible Engineer
– Manufacturing Engineer
– Quality Engineer
• Assembly or test instructions
– Step-by-step procedures
– Provisions for operator and inspector sign off
– May reference other documents, such as test procedures
• Work order remains with item until item has passed final
inspection
• Work order completion results in the delivery of an item to
project stores
• Completed work orders are archived by LAT Quality Assurance
Manager
LAT-PR-01967
v9
4.1.7 Electronics Overview
78
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Manufacturing Flow - Continued
• Order Parts
– All parts approved and on the program PIL
– PWBs to be ordered from qualified suppliers
– Mechanical parts manufactured at SLAC and qualified
machine shops
– All parts received into LAT project stores
• Kitting
– Triggered by Assembly and Inspection Data Sheet (work
order)
– Parts issued from inventory to kit
LAT-PR-01967
v9
4.1.7 Electronics Overview
79
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Manufacturing Flow – Continued
• Assembly
– Performed by approved suppliers
– Completed assembly entered into inventory to close work
order Circuit cards tested at SLAC
– CCAs issued to test work order
– CCAs are tested and returned to stores to close out the test
work order
• End-item assembly parts are issued to assembly work orders
and sent to assembly supplier(s)
• End items are received into project stores as they are received
from the assembly supplier
• End items are issued to test work order for acceptance testing
• Upon completion of acceptance testing, end items are returned
to project stores where are ready for issue to I&T
LAT-PR-01967
v9
4.1.7 Electronics Overview
80
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Manpower Plan
4.1.7 Electronics
25.0
FTEs
20.0
15.0
10.0
5.0
0.0
FY00
FY01
FY02
FY03
DOE + NASA Project
LAT-PR-01967
FY04
FY05
Contributed
v9
4.1.7 Electronics Overview
81
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Power Distribution
+Y Side
LAT Radiator
+Y Side
LAT Radiator
Bay 12
EPU-B
Bay 13
Empty
Bay 14
Empty
Bay 15
Empty
Bay 12
EPU-B
Bay 13
Empty
Bay 14
Empty
Bay 15
Empty
0
0
0
0
0
0
0
0
Bay 8
PDU-B
Bay 9
GASU
Bay 10
GASU
Bay 11
SIU-B
Bay 8
PDU-B
Bay 9
GASU
Bay 10
GASU
Bay 11
SIU-B
9.9
0
0
12.4
0
Bay 6
GASU
Bay 7
SIU-A
Bay 6
GASU
Bay 7
SIU-A
9.9
21.6
18.11
12.4
27.2
0
-X Side
Bay 4
PDU-A
Bay 5
GASU
14.4
-X Side
Bay 4
PDU-A
Bay 5
GASU
Bay 0
EPU-A
Bay 1
Empty
Bay 2
Empty
Bay 3
EPU-A
Bay 0
EPU-A
Bay 1
Empty
Bay 2
Empty
Bay 3
EPU-A
19.4
0
0
19.4
24.3
0
0
24.3
Boxes
118.8
-Y Side
LAT Radiator
TEM/TPS:
241.0
X-LAT Tot
359.9
Boxes
94.4
TEM/TPS:
191.7
X-LAT Tot
286.2
LAT-PR-01967
+X Side
Sun
Side
-Y Side
LAT Radiator
LAT Top View
v9
+X
Side
Sun
Side
LAT Top View
4.1.7 Electronics Overview
82
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
Materials List
FINISHES
Finish
Specification
Color
Hard Anodize
Electroless Nickel
Part Marking
MIL-A-8625F Type III Class 2 (.002")
AMS-2404C Class 1 Grade A (MIL-C-26074) (.0005 Thick)
Mark Using Epoxy Ink A-A-56032 5mm Characters, Color: Black ro White
Black
Nickel
MATERIAL DATA
Material
Specification
Manufacturer
Aluminum 6061-T6
Aluminum 5052
Titanium
Torlon (Polyamide)
Ultem 2300
CV 2943
Cho-Therm 1671
DC 6-1104
Conformal Coating
Staking
AMS-QQ-A-250/11
AMS-QQ-A-250/8
Ti 6AL-4V
4203PAI
Ultem 2300PEI
Thermally Conductive, CV, RTV Silicone
Thermally Conductive Elastomer Insulator Pad
RTV Silicone Adhesive CV
URALANE 5750LV A/B AS 18/100 BW/F
URALANE 5753LV A/B AS 1/5 BW POLYURETHANE
Chomerics
Chomerics
Dow Corning
Furane Products
Furane Products
A286 High Tensile 160ksi Fasteners
300 CRES 80ksi Fasteners
NAS1351, NAS1352
NASM16995, NASM16996
Ink, Marking
Ink, Marking
CAT-L-INK 50-100R/CAT 9 AS 100/6 BW WHITE INK/F
CAT-L-INK 50-700R/CAT 9 AS 100/7 BW BLACK INK/F
Aircraft Wire
M22759/33
LAT-PR-01967
Dexter Hysol
Dexter Hysol
v9
TML
%
>1%
CVCM
%
>.10%
.430
.50
.76
.29
.65
.87
.01
.01
.07
.05
.01
.01
.64
.74
.01
.01
4.1.7 Electronics Overview
83
GLAST LAT Project
CDR/CD-3 Review, May 12-15, 2003
EEE Parts List
• Parts list submitted to Parts Control Board
– Resistors
– Capacitors
– Connectors/wire
– Integrated Circuits
• ACTEL 54SX32/72 FPGA
• BAE FIFO
• INTERSIL POR
• HONEYWELL RAM
• Summit MIL1553 IC
• Almost all parts are approved
• Main parts remaining are
– ASIC’s
• Requires radiation testing on flight production, can only
be implemented when flight-production is in hand
LAT-PR-01967
v9
4.1.7 Electronics Overview
84